CN202422106U

CN202422106U - High-speed bus timing error generating device

Info

Publication number: CN202422106U
Application number: CN 201120417536
Authority: CN
Inventors: 王刚; 阎海霞; 张淑舫
Original assignee: No 8357 Research Institute of Third Academy of CASIC
Current assignee: No 8357 Research Institute of Third Academy of CASIC
Priority date: 2011-10-28
Filing date: 2011-10-28
Publication date: 2012-09-05
Anticipated expiration: 2021-10-28

Abstract

The utility model belongs to a bus error injection testing technology, particularly relates to a high-speed bus timing error generating device and aims at testing the timing error condition of a high-speed bus under a communication limiting case. The timing error generating device comprises a signal selection module, wherein the signal selection module is used for controlling a bus signal source module and a timing error code insert module; a bus signal source is connected with a DA (digital-analogue) conversion chip; the DA conversion chip is connected with a bus through a coupler; the timing error code insert module is connected with an AD (analogue-digital) conversion chip; the AD conversion chip is connected with the bus through a coupler; the timing error code insert module is connected with an outer side bus tested terminal through a filtering module; and the signal selection module is connected with an external master control computer. The timing error generating device can achieve simulation test on the peculiar timing error of the high-speed bus and can be used for simulating various strict high-speed error signals in missile using environment at will.

Description

A kind of high-speed bus sequential mistake generation device

Technical field

The utility model belongs to bus error and injects measuring technology, is specifically related to a kind of high-speed bus sequential mistake generation device.

Background technology

Along with the raising of traffic rate, change for the test request of product, especially aspect random disturbance filtering and sequential error correcting thereupon; Some interference can not produce error code when low speed bus is communicated by letter, and for the high-speed bus signal, can bring the subversiveness mistake, if untimely identification, correction and processing; To directly cause mass data packet loss or systemic breakdown; Therefore must carry out the strictness test with the anti-interference of bus apparatus and sequential error correction performance to the high speed bullet,, can't simulate for the distinctive wrong sequential of high-speed bus signal because the bus test device only stresses the simulation to traditional low speed bus rub-out signal at present; Therefore; Need a kind of high-speed bus sequential mistake generation device of exploitation, simulate to the distinctive wrong sequential of high-speed bus signal, checking high speed bullet is with the error processing capacity of bus apparatus.

Summary of the invention

The purpose of the utility model is the sequential error situation under the test high-speed bus communication limiting case, and a kind of high-speed bus sequential mistake generation device is provided.

The technical scheme that the utility model adopted is:

A kind of high-speed bus sequential mistake generation device; Wherein: comprise signal selection module; Signal selection module control bus signal source module and sequential error coded insert module, the bus signals source links to each other with the DA conversion chip, and the DA conversion chip links to each other with bus through coupling mechanism; Sequential error coded insert module links to each other with the AD conversion chip, and the AD conversion chip links to each other with bus through coupling mechanism; Sequential error coded insert module is connected with outside bus dut terminal through filtration module; Signal selection module is connected with the external piloting control computing machine.

Aforesaid a kind of high-speed bus sequential mistake generation device; Wherein: said signal selection module, bus signals source module and sequential error coded insert module are realized by arm processor, fpga chip; Said arm processor carries out exchanges data through universal asynchronous serial and main control computer and bus dut terminal

Aforesaid a kind of high-speed bus sequential mistake generation device, wherein: said fpga chip is accomplished high-speed serial data transmitting-receiving logic, the modulation of output signal, is received signal filtering, smart host interface control logic and internal RAM management.

The beneficial effect of the utility model is:

1. a kind of high-speed bus sequential mistake generation device of providing of the utility model can be accomplished the simulation test of the peculiar sequential mistake of high-speed bus; Various harsh high speed rub-out signal in the simulated missile environment for use can't generate and these high speed bit error signals are traditional low speed proving installations arbitrarily;

2. realize bus signals source module and sequential error coded insert module through ARM and FPGA, flexible design, be convenient to upgrading, realize that by FPGA highspeed serial data stream controls efficient height and real-time.

Description of drawings

The composition framework of a kind of high-speed bus sequential mistake generation device that Fig. 1 provides for the utility model;

The functional structure chart of a kind of high-speed bus sequential mistake generation device that Fig. 2 provides for the utility model.

Embodiment

Below in conjunction with accompanying drawing and embodiment a kind of high-speed bus sequential mistake generation device that the utility model provides is introduced:

As shown in Figure 1; A kind of high-speed bus sequential mistake generation device; Comprise arm processor, fpga chip; Arm processor carries out exchanges data through universal asynchronous serial and main control computer and bus dut terminal, fpga chip through high-speed AD DA conversion chip and outside high-speed bus carry out exchanges data.

Wherein fpga chip is accomplished high-speed serial data transmitting-receiving logic, the modulation of output signal, is received signal filtering, smart host interface control logic and internal RAM management; High-speed serial data transmitting-receiving logic module converts the misdata that ARM generates into high-frequency serial output code flow, and input signal is carried out high-frequency sampling and decoding, synthetic parallel receive Frame.

ARM accomplishes the misdata generation, mistake injects flow process control and the fault processing result judges.

As shown in Figure 2, the signal selection module of sequential mistake generation device is selected corresponding bus signals source under the control of main control computer, and the bus signals source data is transferred on the bus through DA conversion chip, coupling mechanism; Data after the transmission reach sequential error coded insert module through coupling mechanism, AD conversion chip again, and sequential error coded insert module is inserted error coded in data under the control of signal selection module, and amended data are through filtering input bus dut terminal.

The workflow of high-speed bus sequential mistake generation device is following:

1. main control computer sends test initiation command through universal asynchronous serial;

2. after sequential mistake generation device is received enabled instruction, generate normal original test data by arm processor and write FPGA;

3. be the bus signals waveform by FPGA control high-speed D with original test data conversion, be sent to main bus through bus coupler;

4. receiving end sequential mistake generation device receives signal by the high-speed A/D converter real-time sampling, and the digital quantity of discretize is sent to FPGA, and simultaneously, arm processor is accomplished the misdata generation according to injecting wrong option;

5. accomplish the stack of multiplying each other of normal raw data and misdata in real time by FPGA, synthetic final bus error code data, and the control high-speed D exports the bus dut terminal to;

6. monitor the error code response of dut terminal in real time, judge whether the conformance with standard regulation, satisfy the error code treatment requirement;

7. accomplish the terminal error test report by arm processor, and report and submit main control computer to show and storage, accomplish once the wrong flow process of injecting.

Claims

1. high-speed bus sequential mistake generation device; It is characterized in that: comprise signal selection module; Signal selection module control bus signal source module and sequential error coded insert module, the bus signals source links to each other with the DA conversion chip, and the DA conversion chip links to each other with bus through coupling mechanism; Sequential error coded insert module links to each other with the AD conversion chip, and the AD conversion chip links to each other with bus through coupling mechanism; Sequential error coded insert module is connected with outside bus dut terminal through filtration module; Signal selection module is connected with the external piloting control computing machine.

2. a kind of high-speed bus sequential mistake generation device according to claim 1; It is characterized in that: said signal selection module, bus signals source module and sequential error coded insert module realize by arm processor, fpga chip, and said arm processor carries out exchanges data through universal asynchronous serial and main control computer and bus dut terminal.