CN210467764U - Soft circuit substrate with coarsening solder mask layer - Google Patents
Soft circuit substrate with coarsening solder mask layer Download PDFInfo
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- CN210467764U CN210467764U CN201921156399.7U CN201921156399U CN210467764U CN 210467764 U CN210467764 U CN 210467764U CN 201921156399 U CN201921156399 U CN 201921156399U CN 210467764 U CN210467764 U CN 210467764U
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Abstract
The utility model provides a soft circuit substrate with coarsening solder mask, it contains: a conductive copper layer having a wiring pattern on an insulating substrate; a first tin layer located over the conductive copper layer; a second tin layer located above the first tin layer; a first solder mask layer covering the conductive copper layer uncovered by the first tin layer and the second tin layer, and the first solder mask layer partially covering the second tin layer; and the second solder mask layer partially covers the second tin layer and at least partially covers the first solder mask layer, wherein the second solder mask layer is provided with a roughened surface. As described above, in one aspect, the present invention provides a novel flexible circuit substrate without two times of tin plating and interleaving treatment of solder mask ink. The utility model discloses also coating top layer solder mask printing ink after the tin layer is accomplished at last to the top layer solder mask printing ink soaks in the tinning bath. Simultaneously the utility model discloses still provide a soft circuit substrate, can the coarsening weld layer in order to reduce the difference in height of outer pin and weld layer, improve the bad phenomenon of crimping.
Description
Technical Field
The present invention relates to flexible circuit substrates, and more particularly to a flexible circuit substrate capable of supporting semiconductor chips.
Background
The soft circuit substrate for bearing the chip is mostly a rolling strip film. The combination of flexible circuit substrate and Chip is known in the industry according to different mounting modes, such as TCP (Tape Carrier Package) or COF (Chip On Film Chip On Package). Both the TCP and the COF use a flexible circuit board as a carrier for packaging a chip, and a Gold Bump (Gold Bump) on the chip is bonded to an Inner Lead (Inner Lead) of a copper wiring pattern on a flexible circuit board by thermocompression bonding.
In order to connect the flexible substrate circuit with the gold bumps of the chip, a gold-tin eutectic is required, wherein gold is provided by the gold bumps of the chip and tin is provided by tin formed on the surface of the inner leads, so that the surface of the inner leads is plated with a tin layer. In addition to the inner leads, the copper wiring pattern includes conductive terminals connected to other electronic components, such as outer leads, and these terminals also have a tin plating layer. The portion of the copper wiring pattern not plated with tin is additionally protected by being covered with solder ink.
The existing flexible substrate circuit is easy to generate the following problems that firstly, whiskers are formed on the surface of a tin coating, so that adjacent circuits are short-circuited; the second is that the interface of the solder resist ink and the tin coating generates pits, which leads to the fracture of the circuit. Patent document 1 (japanese patent JP3061613) discloses a method of forming a thin tin-plated layer (a) over the entire surface of a copper wiring pattern, then applying a solder resist ink to the non-lead area of the wiring pattern, and then forming a thick tin-plated layer (b) in the lead area. Patent document 1 suggests that the formation of pits can be prevented by the thin tin plating layer (a) formed on the entire surface of the copper wiring pattern, and the formation of whiskers can be prevented by the thick tin plating layer (b). Patent document 2 (taiwan patent TW531864) discloses another method, which sequentially forms a first solder mask ink on a non-lead region, a thin tin-plated layer on the lead region, a second solder mask ink covering a boundary between the first solder mask ink and the thin tin layer, and a thick tin-plated layer on the thin tin layer.
SUMMERY OF THE UTILITY MODEL
The present inventors have found that there are still many practical problems in the prior art. For example, patent document 1 discloses a thin tin plating layer formed over the entire surface of a copper wiring pattern, which is disadvantageous for products requiring bending because the tin plating layer is generally high in hardness. Further, in either patent document 1 or patent document 2, since the thick tin plating layer is formed after the solder resist ink is finally applied, the solder resist ink of the top layer is still soaked in the tin plating bath for a certain period of time, and particularly, the time for plating the thick tin layer is long, which increases the chance of generating pits at the interface between the solder resist ink of the top layer and the thick tin plating layer. Further, patent document 2 has a process of feeding the solder resist ink into the tin bath after applying the solder resist ink twice, resulting in high cost for cleaning the tin bath contaminated with the solder resist ink. In addition, the two-time tin plating of the two-time solder resist ink described in patent document 2 is performed alternately, which is easy to be confused in practice and causes troubles in the production line arrangement. In addition, the inventor also finds that the traditional method of coating the solder mask ink twice easily causes the solder mask ink to generate a thickened edge in practice. When the outer lead of COF is to be pressed with the conductive glass substrate of display, the outer lead is easily affected by the thickened edge of solder resist ink to generate poor pressing.
The utility model relates to a soft circuit substrate with coarsening solder mask layer contains: a conductive copper layer having a wiring pattern on an insulating substrate; a first tin layer located above the conductive copper layer; a second tin layer over the first tin layer; a first solder mask layer covering the conductive copper layer uncovered by the first tin layer and the second tin layer, and the first solder mask layer partially covering the second tin layer; and a second solder mask layer partially covering the second tin layer and at least partially covering the first solder mask layer, wherein the second solder mask layer has a roughened surface, and the roughness Rz of the roughened surface is in the range of: 0.04 to 5 μm.
The flexible circuit substrate is characterized in that the surface roughness Rz of the roughened surface is in the range of: 0.16 to 4.5 μm.
The flexible circuit substrate is characterized in that the surface roughness Rz of the roughened surface is in the range of: 0.6 to 4.0 μm.
The flexible circuit substrate is characterized in that the first solder mask layer has a first edge contacting the second tin layer.
The flexible circuit substrate is characterized in that the first tin layer has a first longitudinal interface contacting the conductive copper layer, the first solder mask layer has a first edge contacting the second tin layer, and a transverse distance between the first longitudinal interface and the first edge is greater than a thickness of the first tin layer.
The flexible circuit substrate is characterized in that the second tin layer has a second longitudinal interface contacting the first tin layer, and the first solder mask layer covers the second longitudinal interface.
The flexible circuit substrate is characterized in that the second tin layer has a second longitudinal interface contacting the first tin layer, the second solder mask layer has a second edge contacting the second tin layer, and the transverse distance between the second longitudinal interface and the two edges is greater than the thickness of the second tin layer.
The flexible circuit substrate is characterized in that the interface between the first tin layer and the second tin layer is conformal to the interface between the first tin layer and the conductive copper layer.
The flexible circuit board is characterized in that the wiring pattern has a test pin area, an inner pin area and an outer pin area, and the first solder mask layer does not cover the wiring pattern between the test pin area and the inner pin area.
The utility model discloses another aspect relates to a soft circuit substrate with coarsening solder mask, a serial communication port, contains: a conductive copper layer having a wiring pattern provided on an insulating substrate; a tin layer over the conductive copper layer, wherein the conductive copper layer has an exposed portion not covered by the tin layer; and a solder mask covering the exposed portion and partially covering the tin layer, wherein the solder mask has a roughened surface, and the roughness Rz of the roughened surface is within the range of: 0.04 to 5.0 μm.
The flexible circuit substrate is characterized in that the surface roughness Rz of the roughened surface is in the range of: 0.16 to 4.5 μm.
The flexible circuit substrate is characterized in that the surface roughness Rz of the roughened surface is in the range of: 0.6 to 4.0 μm.
The solder mask layer has an edge contacting the solder layer, wherein a lateral distance between the longitudinal interface and the edge is greater than a thickness of the solder mask layer plus a thickness of the solder layer.
The above flexible circuit substrate is characterized in that the thickness of the solder mask layer ranges from 6um to 35 um.
The above-mentioned flexible circuit board is characterized in that the thickness of the tin layer ranges from 0.1um to 0.6 um.
In view of the above, in one aspect, the present invention provides a novel flexible circuit substrate without two times of tin plating and interleaving with solder resist ink. The utility model discloses also coating top layer solder mask printing ink after the tin layer is accomplished at last to the top layer solder mask printing ink soaks in the tinning bath. Simultaneously the utility model discloses still provide a soft circuit substrate, can the coarsening weld layer in order to reduce the difference in height of outer pin and weld layer, improve the bad phenomenon of crimping.
Drawings
Fig. 1A is a schematic top view of a semi-finished product of a soft wire roadbed slab according to an embodiment of the present invention.
FIG. 1B is a schematic cross-sectional view of a specific area of the semi-finished product of FIG. 1A.
Fig. 1B and fig. 2 to 6 are schematic cross-sectional views illustrating steps of a manufacturing process of a flexible circuit substrate according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of a flexible circuit substrate according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention will be exemplified below with reference to the accompanying drawings. In order to avoid obscuring the present invention, the following description also omits conventional components, associated materials, and associated processing techniques. Also, for clarity of description, elements in the figures are not necessarily drawn to scale or relative proportions.
The utility model discloses a manufacturing method of soft circuit substrate
According to a first embodiment of the present invention, a method for manufacturing a flexible circuit board for carrying a chip, sequentially comprises:
the step (a) of providing a conductive copper layer having a wiring pattern on an insulating substrate;
step (b) forming a first solder resist partially covering the wiring pattern;
step (c) forming a first tin layer on the conductive copper layer by using the first solder mask layer as a shield;
step (d) forming a second tin layer on the first tin layer by using the first solder mask layer as a shield;
step (e) forming a second solder mask layer partially covering the second tin layer and at least partially covering the first solder mask layer; and
and (f) roughening the second solder mask layer to make the second solder mask layer have a roughened surface.
The step (a) provides a conductive copper layer having a wiring pattern on an insulating substrate.
Fig. 1A is a schematic top view of a semi-finished product 10 of a soft line roadbed slab of the present invention. Referring to fig. 1A, a plurality of wiring patterns P made of conductive copper layers 110 are continuously formed on one surface of a film-tape-shaped insulating base material 100 of a flexible wiring substrate semi-finished product 10. The insulating base material 100 has a plurality of transmission holes 101 for transfer on both upper and lower sides. The conductive copper layer 110 (or wiring pattern P) defines a non-lead area Ps (portion outlined by a dotted line) which is to be subsequently covered by a solder mask to protect the wiring. The area outside the non-lead area Ps of the wiring pattern P, i.e., the lead area, can be further divided into an inner lead area Ln to be connected to a chip, an outer lead area Lo to be connected to an external circuit board or other electronic device, and an optional test lead area Lt to be connected to a measuring instrument for testing the quality of the packaged chip. Fig. 1B is a schematic cross-sectional view of the area indicated by the arrow 1B in fig. 1A (i.e., one of the wirings in the wiring pattern P). Referring to fig. 1B, it can be clearly understood that the conductive copper layer 110 is located on the insulating substrate 100. As the insulating substrate 100, a material that is soft and has chemical resistance and heat resistance, such as polyester, polyamide, and polyimide, can be used. The thickness of the insulating substrate 100 is generally 12 to 85um, preferably 20 to 50 um. The conductive copper layer 110 having the wiring pattern P is formed on the insulating substrate 100 by a conventional photolithography method. The thickness of the conductive copper layer 110 is, for example, 2 to 20um, preferably 5 to 12 um.
The step (b) forms a first solder resist partially covering the wiring pattern.
Referring to fig. 1A and 2, a first solder mask layer 121 is formed to at least partially cover the wiring pattern P, for example, a part or all of the non-lead area Ps. In the preferred embodiment, the first solder mask layer 121 only needs to be applied to certain specific areas of the non-lead area Ps, such as only the bending area generated during the rear end application of the flexible circuit substrate product. The actual position of the bending region varies according to the characteristics of the rear-end application product, wherein the region between the inner lead region Ln and the outer lead region Lo is the conventional common bending region. Therefore, in the preferred embodiment of the present invention, the first solder mask layer 121 does not cover the non-lead area Ps between the test lead area Lt and the inner lead area Ln, however, the present invention is not limited thereto. The present invention also has an embodiment in which the first solder mask layer 121 completely covers all the non-lead areas Ps. This step can be accomplished by screen printing techniques using an existing epoxy (o-CresolNovalac/Phenol/DGEBA) type ink or other suitable ink. The thickness of the first solder mask layer 121 may be in the range of 3 to 15 um.
And (c) forming a first tin layer on the conductive copper layer by using the first solder mask layer as a mask.
Referring to fig. 3, a first tin layer 131 is formed on the conductive copper layer 110 by using the first solder mask layer 121 as a mask. The first tin layer 131 is formed by a conventional electroless plating (i.e., electroless plating) technique. For example, the semi-finished product formed in step (b) is soaked in a tin bath of tin plating solution containing sulfuric acid, potassium persulfate or tin fluoborate for a predetermined period of time, then washed with water and dried, and then put into an oven for heat treatment. In this step, the first tin layer 131 is plated on the surface of the conductive copper layer 110 not covered by the first solder mask layer 121, and the tin plating solution can further intrude into the conductive copper layer 110 under the first edge 121a of the first solder mask layer 121, thereby forming a structure in which the first edge 121a of the first solder mask layer 121 covers the first side 131a of the first tin layer 131. The thickness of the first tin layer 131 may range from 0.02 to 0.16um, with the thickness of the first tin layer 131 of the preferred embodiment being 0.10 um.
Step (d): a second tin layer is formed on the first tin layer by using the first solder mask layer as a mask.
Referring to fig. 4, a second tin layer 133 is formed on the first tin layer 131 by using the first solder mask layer 121 as a mask. Preferably, there is no additional step of forming a solder mask layer between step (c) and step (d). The second tin layer 133 may be formed by conventional electroless plating (i.e., electroless plating) techniques, as in step (c). For example, the semi-finished product formed in step (c) is soaked in a tin bath of tin plating solution containing sulfuric acid, potassium persulfate or tin fluoborate for a predetermined period of time, then washed with water and dried, and then put into an oven for heat treatment. The tin-copper alloy layer obtained by the first tin plating in the step (c) generates Cu through a heat treatment at a high temperature3Sn which slows down the Cu of the tin layer produced by the second tin plating of step (d)6Sn5The diffusion rate is generated, so that the loss rate of the pure tin layer is reduced, the eutectic bonding yield between the circuit and the chip is improved, and tin whiskers are avoided. In this step, the tin plating solution may further intrude under the first edge 121a of the first solder mask layer 121, so as to form a structure in which the first edge 121a of the first solder mask layer 121 covers the second side 132a of the second tin layer 132. The thickness of the second tin layer 132 may range from 0.12 to 0.5um, with the thickness of the first tin layer 132 of the preferred embodiment being 0.28 um. Since both steps (c) and (d) use electroless plating (i.e., chemical plating) and the first solder mask layer 121 is used as a mask, the first tin layer 131 is pushed by the second tin layer 132 toward the region with high copper density in step (d), so that the interface Iss between the first tin layer 131 and the second tin layer 132 and the interface Isc between the first tin layer 131 and the conductive copper layer 110 are conformal (conformal).
Step (e) forming a second solder mask layer partially covering the second tin layer and at least partially covering the first solder mask layer.
Referring to fig. 5, a second solder mask layer 122 is formed to partially cover the second tin layer 132 and at least partially cover the first solder mask layer 121. Preferably, the step of forming the second solder mask 122 at least covers the contact surface formed by the second tin layer 132 and the first solder mask 121 in the step (d). In step (d), the first solder mask layer 121 is soaked in the tin bath, which may weaken the contact surface between the first solder mask layer 121 and the second tin layer 132, so that the second solder mask layer 122 is used to cover the contact surface to prevent the solder mask layer from peeling off from the tin layer. This step can be carried out by screen printing techniques using an existing ink of the epoxy (o-Cresol Novalac/Phenol/DGEBA type) type or other suitable inks. The thickness of the second solder mask layer 122 may be in the range of 3 to 20 um. In this embodiment, the second solder mask layer 122 is printed on the non-lead area Ps, thereby completely covering the first solder mask layer 121, but the present invention is not limited thereto. The present invention also includes embodiments in which the second solder mask 122 only partially covers the first solder mask 121 (only covers the outer edge thereof) and partially covers the second solder layer 132.
(f) The second solder mask layer is roughened to make the second solder mask layer have a roughened surface.
Referring to fig. 6, after the printing and the heat treatment curing of the second solder mask layer 122 are completed, a surface roughening step is performed to form a second solder mask layer 122' having a roughened surface 601. This step may be accomplished using any suitable method. For example, by physical roughening, such as by rolling, brushing or sanding. Preferably, the position difference brushing method is used, in which a continuous and constant distance range is maintained between the brushing equipment and the surface of the second solder mask layer 122 by using an aluminum oxide abrasive or a silicon carbide abrasive, so that the elastic brushing and the light cutting are performed to achieve a roughening effect. Since the second solder resist layer 122 and the second tin layer 132 have a difference in level between their surfaces, the tin layer and the wiring pattern are not abraded during polishing. As shown in fig. 6, after roughening, the height difference between the second tin layer 132 and the second solder mask layer 122' is decreased, so as to improve the poor bonding. Moreover, the surface of the second solder mask layer 122' has high roughness, which also increases the surface area and enhances the bonding degree between the second solder mask layer and the potting adhesive. The encapsulant is usually used to encapsulate the inner lead area Ln, which needs to be tightly combined with the solder mask layer to protect the circuit connected to the IC chip and the inner lead. In this embodiment, preferably, the surface roughness Rz of the roughened surface 601 of the second solder mask layer 122' is in the range of: 0.04 to 5.0 μm, preferably 0.16 to 4.5 μm, and more preferably 0.6 to 4.0. mu.m. The surface roughness Rz is measured by cutting the roughened sample to about 5cm × 5cm and measuring with a non-contact shape measuring laser microscope (model VK-X100 of Keyence, Taiwan Keyance). The measurement is performed by using a laser spot diameter of about 1um, an objective lens magnification of 10X, a field of view of 1350um X1012 um, an objective lens magnification of 20X, a field of view of 675um X506 um, a scanning time of about 10 to 20 seconds, and a line pitch of 2 um.
The structure of the soft circuit substrate of the utility model
Referring to fig. 1A and fig. 6, in a first embodiment of the present invention, the flexible circuit board for chip mounting includes a conductive copper layer 110 having a wiring pattern P on an insulating substrate 100; a first tin layer 131 over the conductive copper layer 110; the second tin layer 132 is located over the first tin layer 131; the first solder mask layer 121 covers the conductive copper layer 110 uncovered by the first tin layer 131 and the second tin layer 132, and the first solder mask layer 121 partially covers the second tin layer 132; and the second solder mask layer 122 'partially covers the second tin layer 132 and at least partially covers the first solder mask layer 121, wherein the second solder mask layer 122' has a roughened surface 601, and the roughness Rz of the roughened surface 601 ranges from: 0.04 to 5 μm, preferably 0.16 to 4.5 μm, and more preferably 0.6 to 4.0 μm.
In another embodiment, referring to fig. 6, the present invention provides a flexible circuit substrate for carrying chips, wherein the first solder mask layer 121 has a first edge 121a contacting the second tin layer 132.
In another embodiment, referring to fig. 6, the present invention provides a flexible circuit substrate for carrying chips, wherein the first tin layer 131 has a first longitudinal interface 131a contacting the conductive copper layer 110, the first solder mask layer 121 has a first edge 121a contacting the second tin layer 132, and a lateral distance X between the first longitudinal interface 131a and the first edge 121a is greater than a thickness of the first tin layer 131.
In another embodiment, referring to fig. 6, the present invention provides a flexible circuit substrate for carrying chips, wherein the second tin layer 132 has a second longitudinal interface 132a contacting the first tin layer 131, and the first solder mask layer 121 covers the second longitudinal interface 132 a.
In another embodiment, referring to fig. 6, the present invention provides a flexible circuit substrate for carrying chips, wherein the second tin layer 132 has a second longitudinal interface 132a contacting the first tin layer 131, the second solder mask layer 122' has a second edge 122a contacting the second tin layer 132, and a lateral distance Y between the second longitudinal interface 132a and the second edge 122a is greater than a thickness of the second tin layer 132.
In another embodiment, referring to fig. 6, the present invention provides a flexible circuit substrate for carrying chips, wherein the interface Iss between the first tin layer 131 and the second tin layer 132 is conformal to the interface Isc between the first tin layer 131 and the conductive copper layer 110.
Fig. 7 shows that when the first tin layer 131 and the second tin layer 132 are considered as a tin layer 161 and the first solder mask layer 121 and the second solder mask layer 122' are considered as a solder mask layer 162, the flexible circuit substrate for chip mounting according to the present invention is characterized in that the flexible circuit substrate comprises a conductive copper layer 110 having a wiring pattern P disposed on an insulating substrate 100; a tin layer 161 overlying the conductive copper layer 110, wherein the conductive copper layer 110 has an exposed portion 163 not covered by the tin layer 161; and a solder mask layer 162 partially covering the exposed portion and partially covering the tin layer 161, wherein the tin layer 161 has a longitudinal interface 161a contacting the conductive copper layer 110, the solder mask layer 162 has an edge 162a contacting the tin layer 161, and a lateral distance Z between the longitudinal interface 161a and the edge 162a is greater than the thickness of the solder mask layer 162 plus the thickness of the tin layer 161. In a preferred embodiment, the thickness of the solder mask layer 162 ranges from 6um to 35 um. In a preferred embodiment, the tin layer 161 has a thickness ranging from 0.1um to 0.6 um.
The present invention also has an embodiment in which only step (c) is performed without step (d), in which case the thickness of the tin layer ranges from 0.1um to 0.6 um.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the claims; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention.
[ description of symbols ]
10 soft line roadbed slab semi-finished product
100 insulating base material
101 drive hole
110 conductive copper layer
P wiring pattern
1B reference diagram
Lo outer lead area
Ps non-pin area
Ln inner pin area
Lt test pin area
121 first solder mask layer
121a first edge
131 first tin layer
131a first side edge
Iss interface
Isc interface
132 second tin layer
122 second solder mask layer
122' second solder mask
122a second edge
132a second side edge
X lateral distance
Distance in the Y transverse direction
161 tin layer
161a longitudinal interface
162 solder mask layer
162a edge
163 exposed part
Z lateral distance.
Claims (15)
1. A soft circuit substrate with a roughened solder mask layer is characterized by comprising:
a conductive copper layer having a wiring pattern on an insulating substrate;
a first tin layer located above the conductive copper layer;
a second tin layer located above the first tin layer;
a first solder mask layer covering the conductive copper layer uncovered by the first tin layer and the second tin layer, and the first solder mask layer partially covering the second tin layer; and
a second solder mask layer partially covering the second tin layer and at least partially covering the first solder mask layer, wherein the second solder mask layer has a roughened surface, and the roughness Rz of the roughened surface is in the range of: 0.04 to 5 μm.
2. The flexible circuit substrate as claimed in claim 1, wherein the roughened surface has a surface roughness Rz in the range of: 0.16 to 4.5 μm.
3. The flexible circuit substrate as claimed in claim 2, wherein the roughened surface has a surface roughness Rz in the range of: 0.6 to 4.0 μm.
4. The flexible circuit substrate as claimed in claim 1, wherein the first solder mask layer has a first edge contacting the second tin layer.
5. The flexible circuit substrate of claim 1, wherein the first tin layer has a first longitudinal interface contacting the conductive copper layer, the first solder mask layer has a first edge contacting the second tin layer, and the first longitudinal interface is spaced apart from the first edge by a distance greater than the thickness of the first tin layer.
6. The flexible circuit substrate as claimed in claim 1, wherein the second tin layer has a second longitudinal interface contacting the first tin layer, and the first solder mask layer covers the second longitudinal interface.
7. The flexible circuit substrate of claim 1, wherein the second tin layer has a second longitudinal interface contacting the first tin layer, the second solder mask layer has a second edge contacting the second tin layer, and the second longitudinal interface is spaced apart from the second edge by a distance greater than the thickness of the second tin layer.
8. The flexible circuit substrate of claim 1, wherein the interface of the first tin layer and the second tin layer is conformal to the interface of the first tin layer and the conductive copper layer.
9. The flexible circuit substrate as claimed in claim 1, wherein said wiring pattern has a test pin area, an inner pin area and an outer pin area, said first solder mask layer does not cover said wiring pattern between said test pin area and said inner pin area.
10. A soft circuit substrate with a roughened solder mask layer is characterized by comprising:
a conductive copper layer having a wiring pattern provided on an insulating substrate;
a tin layer over the conductive copper layer, wherein the conductive copper layer has an exposed portion not covered by the tin layer; and
a solder mask covering the exposed portion and partially covering the tin layer, wherein the solder mask has a roughened surface, and the roughness Rz of the roughened surface is within the range of: 0.04 to 5.0 μm.
11. The flexible circuit substrate of claim 10, wherein the roughened surface has a surface roughness Rz in the range of: 0.16 to 4.5 μm.
12. The flexible circuit substrate of claim 11, wherein the roughened surface has a surface roughness Rz in the range of: 0.6 to 4.0 μm.
13. The flexible circuit substrate of claim 10, wherein the tin layer has a longitudinal interface contacting the conductive copper layer, the solder mask has an edge contacting the tin layer, and wherein the longitudinal interface is spaced apart from the edge by a distance greater than the thickness of the solder mask plus the thickness of the tin layer.
14. The flexible circuit substrate as claimed in claim 10, wherein the solder mask layer has a thickness ranging from 6um to 35 um.
15. The flexible circuit substrate of claim 10, wherein the tin layer has a thickness ranging from 0.1um to 0.6 um.
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| CN201921156399.7U CN210467764U (en) | 2019-07-22 | 2019-07-22 | Soft circuit substrate with coarsening solder mask layer |
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| CN201921156399.7U CN210467764U (en) | 2019-07-22 | 2019-07-22 | Soft circuit substrate with coarsening solder mask layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112259461A (en) * | 2019-07-22 | 2021-01-22 | 颀邦科技股份有限公司 | Soft circuit substrate with coarsening solder mask layer and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112259461A (en) * | 2019-07-22 | 2021-01-22 | 颀邦科技股份有限公司 | Soft circuit substrate with coarsening solder mask layer and manufacturing method thereof |
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