CN113556883B

CN113556883B - Preparation method of circuit board packaging structure and circuit board packaging structure

Info

Publication number: CN113556883B
Application number: CN202010328789.9A
Authority: CN
Inventors: 周琼; 刘瑞武; 郭志
Original assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Current assignee: Avary Holding Shenzhen Co Ltd; Qing Ding Precision Electronics Huaian Co Ltd
Priority date: 2020-04-23
Filing date: 2020-04-23
Publication date: 2022-11-15
Anticipated expiration: 2040-04-23
Also published as: CN113556883A

Abstract

A preparation method of a circuit board packaging structure comprises the following steps: providing a packaging substrate, wherein the packaging substrate comprises a base layer and a conductive circuit layer formed on the base layer, the conductive circuit layer comprises a pin area, and the pin area comprises a first surface far away from the base layer; performing a solder paste spraying process on the lead area to form an alloy layer on the first face, wherein the alloy layer comprises tin and a metal element different from the tin; and providing an integrated circuit, and electrically connecting the integrated circuit with the alloy layer to obtain the circuit board packaging structure. The application also provides a circuit board packaging structure prepared by the preparation method of the circuit board packaging structure.

Description

Preparation method of circuit board packaging structure and circuit board packaging structure

Technical Field

The present disclosure relates to the field of circuit board packaging, and more particularly, to a method for manufacturing a circuit board packaging structure and a circuit board packaging structure.

Background

Chip On Film (COF) and System On Film (SOF) are packaging technologies that join conductive bumps to pins On a circuit board and a Chip. As the manufacturing technology advances and the density of integrated circuits increases, the size and pitch of the leads and conductive bumps also decreases. Generally, the leads need to be surface treated with tin prior to connecting the conductive bumps.

However, tin compounds have the following problems: after tin production, the tin layer on the leads and the copper may migrate to form Intermetallic compounds (Intermetallic compounds), such as Cu, during subsequent thermal processing or long term placement ₃ Sn、Cu ₆ Sn ₅ Etc., reducing product reliability. Moreover, the thickness of the tin product is typically reduced based on the amount of pure tin subsequently removed and the lead requirementsThe pure tin amount is calculated, so that the heating process is needed more after the SOF product is tin-melted, the needed thickness exceeds the maximum tin thickness, and the tin melting process cannot be continuously used.

Disclosure of Invention

In view of the above, it is desirable to provide a method for manufacturing a circuit board package structure that can avoid or reduce the formation of intermetallic compounds.

In addition, it is necessary to provide a circuit board package structure.

A preparation method of a circuit board packaging structure comprises the following steps:

providing a packaging substrate, wherein the packaging substrate comprises a base layer and a conductive circuit layer formed on the base layer, the conductive circuit layer comprises a pin area, and the pin area comprises a first surface far away from the base layer;

performing a solder paste spraying process on the lead area to form an alloy layer on the first face, wherein the alloy layer comprises tin and a metal element different from the tin; and

and providing an integrated circuit, and electrically connecting the integrated circuit with the alloy layer to obtain the circuit board packaging structure.

In one embodiment of the present application, the metal element includes at least one of silver, copper, bismuth, and indium.

In an embodiment of the present application, before the solder paste spraying process, the method further includes the following steps:

forming a covering film on part of the pin area;

wherein the remaining portion of the lead region is exposed to the cover film, and the alloy layer is formed on the exposed portion of the lead region.

In one embodiment of the present application, the lead area further includes a second surface connected to the first surface, and before the solder paste spraying process, the method further includes the steps of:

a protective layer is formed on the first and second sides of the lead area.

In an embodiment of the present application, the conductive circuit layer further includes a pad area, and before the solder paste spraying process is performed, the method for manufacturing the circuit board package structure further includes the following steps:

and mounting an electronic element on the bonding pad area.

In an embodiment of the present application, the circuit board package structure includes a package substrate, an alloy layer, and an integrated circuit. The packaging substrate comprises a base layer and a conductive circuit layer formed on the base layer, wherein the conductive circuit layer comprises a pin area, and the pin area comprises a first surface far away from the base layer; the alloy layer covers the first surface of the pin area, wherein the alloy layer contains a metal element different from tin; the integrated circuit is electrically connected with the alloy layer.

In one embodiment of the present application, the lead region further comprises a second face connected to the first face, the second face being loaded with the alloy layer.

In an embodiment of the present application, the circuit board package structure further includes a protection layer disposed on the first surface and the second surface.

In an embodiment of the present application, the circuit board package structure further includes an electronic component, the conductive trace layer further includes a pad area, and the electronic component is electrically connected to the pad area.

According to the preparation method of the circuit board packaging structure, the alloy layer is formed on the surface of the pin area by adding other metal elements into the tin paste, and the alloy layer replaces metal tin, so that the phenomenon that the metal tin is directly contacted with copper in the pin area and generates intermetallic compounds in a subsequent thermal process or long-term placement can be reduced or avoided.

Drawings

Fig. 1 is a schematic cross-sectional view of a package substrate according to an embodiment of the present disclosure.

Fig. 2 is a schematic cross-sectional view of the portion of the lead area shown in fig. 1 after a cover film is formed thereon.

Fig. 3 is a top view of the portion of the lead area shown in fig. 2 after a cover film is formed thereon.

Fig. 4 is a schematic cross-sectional view of the bonding pad region shown in fig. 2 after a protective layer and an electronic component are formed thereon.

Fig. 5 is a schematic cross-sectional view after an alloy layer is formed on a portion of the lead region shown in fig. 4.

Fig. 6 is a schematic cross-sectional view of the alloy layer covering the first side of the lead region.

Fig. 7 is a schematic cross-sectional view of the alloy layer covering the first side and a portion of the second side of the lead area.

Fig. 8 is a schematic cross-sectional view of the alloy layer covering the first face and all of the second face of the lead area.

Fig. 9 is a schematic cross-sectional view of a circuit board package structure formed after an integrated circuit is connected to the alloy layer shown in fig. 5.

Fig. 10 is a schematic cross-sectional view of a circuit board package structure according to another embodiment of the disclosure.

Description of the main elements

Circuit

board packaging structure

100, 200

Package substrate 10

Base layer 11

Conductive circuit layer 12

First side 122

Second side 124

Alloy layer 126

Lead area 13

Pad area 14

Electronic component 20

Cover film 30

Integrated circuit 50

Protective layer

60, 60a

The following detailed description will further illustrate the present application in conjunction with the above-described figures.

Detailed Description

In order that the above objects, features and advantages of the present application can be more clearly understood, a detailed description of the present application will be given below with reference to the accompanying drawings and detailed description. In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, and the described embodiments are merely some, but not all embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes all and any combination of one or more of the associated listed items.

In various embodiments of the present application, for convenience in description and not limitation, the term "coupled" as used in the specification and claims of the present application is not limited to physical or mechanical connections, either direct or indirect. "upper", "lower", "above", "below", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships are changed accordingly.

Referring to fig. 1 to 10, the present application provides a method for manufacturing a circuit board package structure 100, including the following steps:

step S1: referring to fig. 1, a package substrate 10 is provided, where the package substrate 10 includes a base layer 11 and a conductive trace layer 12 formed on the base layer 11.

As shown in fig. 1, in the present embodiment, the number of the conductive trace layers 12 is two, and the two conductive trace layers are respectively formed on two opposite surfaces of the base layer 11.

Wherein the conductive circuit layer 12 includes a lead area 13 and a pad area 14. The lead area 13 includes a plurality of leads. The pad area 14 includes at least two pads.

Step S2: referring to fig. 2 and 3, a cover film 30 is formed on a portion of the lead region 13, such that the pad region 14 and the remaining portion of the lead region 13 are exposed to the cover film 30.

The cover film 30 is formed by, but not limited to, covering the cover film 30 on the first surface 122 of the conductive circuit layer 12 away from the package substrate 10 (i.e., the upper surface of the conductive circuit layer 12), or forming the cover film 30 by liquid curing.

And step S3: referring to fig. 4, an electronic component 20 is mounted on the surface of the pad area 14 away from the package substrate 10.

Before the step of surface mounting an electronic component 20, the method further includes a step of forming a protective layer 60a on the surface of the pad area 14, wherein the protective layer 60a covers the top surface and the side surface of the pad area 14. The protective layer 60a is used to prevent oxidation or corrosion of the pad area 14, and the protective layer 60a can also function as an electrical connection. The surface treatment mode includes but is not limited to nickel-gold, palladium-gold and the like.

And step S4: referring to fig. 5 to 8, a solder paste spraying process is performed on the exposed first side 122 of the lead region 13 to form an alloy layer 126.

Specifically, a nozzle is used to perform a solder paste spraying process on the lead area 13, so as to form a layer of solder paste on the first surface 122 of the lead area 13, the solder paste further contains other metal elements, the metal elements include at least one of silver (Ag), copper (Cu), bismuth (Bi), and indium (In), and the solder paste forms the alloy layer 126 on the first surface 122 of the lead area 13 to form the lead.

Forming the alloy layer 126 on the first side 122 of the lead region 13, wherein the alloy layer 126 replaces a tin layer in the prior art, so as to reduce or prevent the metal tin from directly contacting with the leads of the lead region 13 and generating an intermetallic compound in a subsequent thermal process or long-term placement; on the other hand, by using the solder paste spraying treatment instead of the tin melting treatment, the solder paste containing the metal element can reduce or avoid the pin area 13 covering the cover film 30 and the connecting area not covering the cover film 30 from corroding to form a cavity due to galvanic reasons in the tin melting process.

The alloy layer 126 is at least loaded on the first surface 122 of the lead region 13 away from the package substrate 10 (see fig. 6). In other embodiments, the alloy layer 126 is further supported on the second side 124 of the lead region 13 (i.e., the side of the lead region 13), the direction of the second side 124 is different from the direction of the first side 122, and the second side 124 is connected to the first side 122. The solder paste may cover a portion of the second surface 124 of the lead area 13 (see fig. 7), or cover the entire second surface 124 of the lead area 13 (see fig. 8). The amount of solder paste loaded on the second surface 124 is related to the distance between the adjacent leads in the lead area 13, the accuracy of the solder paste processing equipment, and the cost. In the subsequent processing, the lead area 13 not covered by the alloy layer 126 is sealed by dispensing, and the solder paste on the second surface 124 does not affect the reliability of the circuit board package structure 100.

In other embodiments, before the solder paste spraying process is performed on the lead area 13, a step of cleaning the lead area 13 is further included to remove oxides and other impurities on the surface of the lead area 13.

Step S5: referring to fig. 9, an Integrated Circuit (IC) 50 is provided, and the IC 50 is electrically connected to the alloy layer 126 to obtain the circuit board package structure 100.

Specifically, a bump (not shown) is disposed on a surface of the integrated circuit 50, the bump is matched with the alloy layer 126, and the bump is electrically connected to the alloy layer 126 by hot pressing, so that the integrated circuit 50 is electrically connected to the alloy layer 126.

Further, the pads of the pad area 14 are used for electrically connecting the electronic component 20. In the present embodiment, the electronic component 20 is electrically connected to the pad area 14 by surface mount technology, and the step of connecting the electronic component 20 to the pad area 14 can be performed before forming the alloy layer 126, so as to reduce the heat treatment process after connecting the integrated circuit 50. In another embodiment, the electronic component 20 may be connected to the pad area 14 after the step of connecting the integrated circuit 50.

Referring to fig. 10, another embodiment of the present application further provides a method for manufacturing a circuit board package structure 200. The difference from the above-mentioned preparation method is that before the step of processing the solder paste, a step of forming a protective layer 60 on the surface of the lead area 13 is further included, and the protective layer 60 covers the first surface 122 and the second surface 124 of the lead area 13. The protective layer 60 serves to prevent oxidation or corrosion of the lead region 13 and also serves as an electrical connection. The surface treatment mode includes but is not limited to nickel-gold, palladium-gold and the like.

It is understood that, in the present embodiment, the alloy layer 126 is formed on the surface of the protection layer 60 during the subsequent tin spraying paste treatment.

In the present embodiment, the step of providing the protective layer 60a is performed before the surface mounting of the electronic component 20. When the step of surface mounting the electronic component 20 is performed after the step of forming the alloy layer 126, the protective layer 60a may be formed on the surface of the pad region 14 at the same time as the step of forming a protective layer 60 on the surface of the lead region 13.

Referring to fig. 9, the present application further provides a circuit board package structure 100, wherein the circuit board package structure 100 includes a package substrate 10, an alloy layer 126 and an integrated circuit 50.

Referring to fig. 1, the package substrate 10 includes a base layer 11 and a conductive trace layer 12 formed on the base layer 11. The conductive circuit layer 12 includes a lead area 13 and a pad area 14, and the conductive circuit layer 12 is disposed on at least one surface of the package substrate 10. Wherein the lead area 13 includes a plurality of leads, and the pad area 14 includes at least two pads.

The alloy layer 126 is loaded on at least a portion of the lead region 13 at the first side 122 of the lead region 13 away from the package substrate 10. The integrated circuit 50 includes bumps that are electrically connected to the alloy layer 126.

Further, the lead area 13 also includes a second face 124, the direction of the second face 124 is different from the direction of the first face 122, and the second face 124 connects the first face 122. The alloy layer 126 is further supported on the second surface 124 of the lead region 13, and the alloy layer 126 may cover a part of the second surface 124 of the lead region 13 or cover the entire second surface 124 of the lead region 13.

The circuit board package structure 100 further includes an electronic component 20, and the electronic component 20 is electrically connected to the pad area 14.

Referring to fig. 10, another embodiment of the present application further provides a circuit board package structure 200, which is different from the circuit board package structure 100 in that the circuit board package structure 200 further includes a protection layer 60, the protection layer 60 is disposed between the pin area 13 and the alloy layer 126, and the protection layer 60 is used for preventing the pin area 13 from being oxidized or corroded and also has an electrical connection function.

According to the preparation method of the circuit board package structure 100 provided by the application, the alloy layer 126 is formed on the surface of the lead area 13 by adding other metal elements into the solder paste, and the alloy layer 126 replaces the metal tin, so that the generation of intermetallic compounds caused by the direct contact between the metal tin and the copper in the lead area 13 in a subsequent thermal process or long-term placement can be reduced or avoided.

Although the present application has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the spirit and scope of the present application.

Claims

1. A preparation method of a circuit board packaging structure is characterized by comprising the following steps:

providing a packaging substrate, wherein the packaging substrate comprises a base layer and a conductive circuit layer formed on the base layer, the conductive circuit layer comprises a pin area and a welding pad area, and the pin area comprises a first surface far away from the base layer;

forming a cover film on part of the lead area, exposing the rest of the lead area to the cover film, and mounting an electronic element on the pad area;

performing solder paste spraying treatment on the lead area which is not covered with the cover film after the electronic element is mounted so as to form an alloy layer on the first face, wherein the alloy layer comprises tin and a metal element different from tin, and the metal element comprises at least one of silver, copper and bismuth; and

2. The method for manufacturing a circuit board package structure according to claim 1, wherein the lead area further includes a second surface connected to the first surface, and further comprising the following steps before performing the solder paste spraying process:

a protective layer is formed on the first and second sides of the lead area.

3. A circuit board package structure, comprising:

the packaging substrate comprises a base layer and a conductive circuit layer formed on the base layer, wherein the conductive circuit layer comprises a pin area and a welding pad area, and the pin area comprises a first surface far away from the base layer;

a cover film covering part of the lead area, and the rest part of the lead area is exposed to the cover film,

an alloy layer covering a portion of the first side of the lead region exposed to the cap film, wherein the alloy layer contains a metal element other than tin, the metal element including at least one of silver, copper, and bismuth;

an electronic component electrically connected to the pad area; and

an integrated circuit electrically connected with the alloy layer.

4. The circuit board package structure of claim 3, wherein the lead area further comprises a second side connected to the first side, the second side carrying the alloy layer thereon.