TWM596459U - Flexible circuit board having rough solder resist layer and manufacturing method thereof - Google Patents

Abstract

The invention provides a flexible circuit board for carrying a chip. The flexible circuit board comprises: a conductive copper layer having a wiring pattern on an insulating substrate; a first tin layer on the conductive copper layer; a first solder resist layer covering the conductive copper layer not covered by the first tin layer and the second tin layer, and the first solder resist layer partially covering the second tin layer; and a second solder resist layer partially covering the second tin later and at least partially covering the first solder resist layer, wherein the second solder resist layer is formed with a rough surface.

Description

Soft circuit board with rough solder mask

This creation is about soft circuit substrates, especially about soft circuit substrates that can carry semiconductor chips.

Most of the flexible circuit substrates for carrying wafers are reel-shaped films. The combination of flexible circuit substrates and wafers in the industry has various names according to different assembly modes, such as TCP (Tape Carrier Package) or COF (Chip On Film). Both TCP and COF use a flexible circuit substrate as a carrier for packaging the chip, and the gold bump on the chip is bonded to the inner lead of the copper wiring pattern on the flexible substrate circuit by thermocompression bonding .

In order to connect the flexible substrate circuit to the gold bumps of the chip, there must be the presence of gold-tin eutectics, where gold is provided by the gold bumps of the chip, and tin is supplied by the tin formed on the surface of the inner pin. The surface of the pin is plated with tin. In addition to the inner leads, the copper wiring pattern also has conductive terminals such as outer leads connected to other electronic components, and these terminals also have a tinned layer. The part of the copper wiring pattern that does not have a tinned layer will be covered with solder resist ink to protect it.

The conventional flexible substrate circuit is susceptible to the following problems. One is the formation of whiskers on the surface of the tinned layer, which leads to short circuit of the adjacent circuit; the other is that the interface between the solder resist ink and the tinned layer creates a hole, which causes the circuit to break. Patent Document 1 (Japanese Patent JP3061613) discloses a scheme in which copper wiring patterns First, a thin tin plating layer (a) is formed in an all-round way, and then solder resist ink is coated on the non-lead area of the wiring pattern, and then a thick tin plating layer (b) is formed on the lead area. Patent Document 1 considers that a thin tin-plated layer (a) formed with copper wiring patterns all over can prevent the occurrence of pits, and a thick tin-plated layer (b) can prevent the generation of whiskers. Patent Document 2 (Taiwan Patent TW531864) discloses another method of sequentially forming a first solder resist ink in the non-lead area, forming a thin tinned layer on the lead area, and then forming a second solder resist ink to cover the first solder resist The junction of ink and thin tin layer, and finally a thick tin plating layer is formed on the thin tin layer.

After investigation, the inventor of the present case found that the above-mentioned conventional technology still has many problems in practice. For example, Patent Document 1 has a thin tin plating layer formed on the entire copper wiring pattern, which is unfavorable for products that need to be bent, because the hardness of the tin plating layer is usually high. Furthermore, both Patent Document 1 and Patent Document 2 teach that a thick tinned layer is formed after the last application of solder resist ink, so the solder resist ink on the top layer will still be immersed in the tin plating tank for a period of time, especially thick tin plating The time is longer, which increases the chance that the interface between the top solder resist ink and the thick tin plating layer will have pits. In addition, Patent Document 2 has two processes of applying solder resist ink before entering the tin bath, resulting in a high cost of cleaning the tin bath contaminated with solder resist ink. In addition, Patent Document 2 teaches that two solder resist inks and two tin plating are staggered to implement the process, which is actually confusing in practice and causes troubles in the production line arrangement. In addition, the inventor of the present invention has further found that the practice of applying the solder resist ink twice in practice is prone to cause the solder resist ink to have thick edges in practice. When the outer leads of the COF are to be crimped with the conductive glass substrate of the display, they are easily affected by the thick edges of the solder resist ink and cause poor crimping.

In view of the above, on the one hand, this creation proposes a novel method for manufacturing a flexible circuit substrate, without two solder resist inks and two tin plating staggered implementation processes. This creation also applies the top solder resist ink after the final tin layer is completed, so as not to immerse the top solder resist ink in the tin plating bath. At the same time, this creation also further coarsened the solder mask to reduce the height difference between the outer leads and the solder mask, and improved the phenomenon of poor crimping.

According to an embodiment, the present invention provides a flexible circuit base for carrying chips The manufacturing method of the board includes the following steps in sequence: (a) providing a conductive copper layer with a wiring pattern on an insulating substrate; (b) forming a first solder mask to partially cover the wiring pattern; (c) Forming a first tin layer on the conductive copper layer using the first solder mask as a mask; (d) forming a second tin layer on the first tin layer using the first solder mask as a mask; And (e) forming a second solder mask to partially cover the second tin layer and at least partially covering the first solder mask; and (f) roughening the second solder mask to make the second solder mask The layer has a roughened surface.

According to an embodiment, the present invention provides the manufacturing method as described above, wherein there is no step of forming a solder mask layer between step (c) and step (d).

According to an embodiment, the present invention provides the manufacturing method as described above, wherein the first solder mask layer is at least partially covered with the second tin layer through the step (d).

According to an embodiment, the present invention provides the manufacturing method as described above, wherein through the step (d), the interface between the first tin layer and the second tin layer is conformal to the interface between the first tin layer and the conductive copper layer .

According to an embodiment, the present invention provides the manufacturing method as described above, wherein the second solder resist layer is not in contact with the tin plating solution.

On the other hand, the present invention provides a method for manufacturing a flexible circuit board, which reduces the coating area of the first solder mask layer or the second solder mask layer to reduce the amount of solder mask contamination on the tin bath. For example, the first solder mask layer can selectively coat only the areas where the flexible circuit substrate bends at the product application end; or the second solder mask layer can selectively cover the outer edge of the first solder mask layer Without completely covering the first solder mask.

According to an embodiment, the present invention provides a method for manufacturing a flexible circuit substrate for carrying a chip, including the following steps in sequence: (a) providing a conductive copper layer with a wiring pattern on an insulating substrate, wherein the wiring pattern It has a test pin area, an inner pin area and an outer pin area, (b) forming a first solder mask to partially cover the wiring pattern, the first solder mask does not cover the wiring pattern between the test pin area and the inner pin area; (c) with the first A solder mask is formed as a mask to form a first tin layer on the conductive copper layer; (d) A second solder layer is formed on the first tin layer using the first solder mask as a mask; (e) Forming a second solder mask to partially cover the second tin layer and at least partially to cover the first solder mask; and (f) roughening the second solder mask so that the second solder mask has a roughness化面。 Surface.

According to an embodiment, the present invention provides the aforementioned manufacturing method, wherein in the step (e) the second solder mask layer does not completely cover the first solder mask layer.

On the other hand, the creation further includes various structures of the flexible circuit substrate formed by the above-mentioned methods.

10: Semi-finished flexible circuit board

100: insulating substrate

101: Transmission hole

110: conductive copper layer

P: Wiring pattern

1B: Arrow

Lo: outer pin area

Ps: non-pin area

Ln: inner pin area

Lt: test pin area

121: The first solder mask

121a: the first edge

131: The first tin layer

131a: first side

131a’: the first vertical interface

Iss: interface

Isc: interface

132: Second tin layer

122: Second solder mask

122’: Second solder mask

122a: second edge

132a: second side

132a’: Second vertical interface

X: horizontal distance

Y: horizontal distance

161: Tin layer

161a: Portrait interface

162: Solder mask

162a: edge

163: Exposed part

Z: lateral distance

FIG. 1A is a schematic top view of a semi-finished flexible circuit board according to an embodiment of the invention.

FIG. 1B is a schematic cross-sectional view of a specific area in the semi-finished product of FIG. 1A.

2 to 6 are schematic cross-sectional views of the steps of the manufacturing process of the flexible circuit substrate according to an embodiment of the present invention.

FIG. 7 is a schematic structural diagram of a flexible circuit substrate created according to an embodiment.

The preferred embodiments of the present invention will be demonstrated below with reference to the attached drawings. In order to avoid obscuring the content of this creation, the following description also omits conventional components, related materials, and related processing technologies. At the same time, in order to clearly illustrate the creation, the elements in the drawings are not necessarily drawn according to actual size or relative proportion.

Manufacturing method of original soft circuit board

According to the first embodiment, the method for manufacturing a flexible circuit substrate for carrying a chip includes: step (a) providing a conductive copper layer with a wiring pattern on an insulating substrate; step (b) forming a The first solder mask layer partially covers the wiring pattern; step (c) forms a first tin layer on the conductive copper layer using the first solder mask layer as a mask; step (d) uses the first solder mask layer Forming a second tin layer on the first tin layer for the mask; step (e) forming a second solder resist layer partially covering the second tin layer and at least partially covering the first solder resist layer; and steps (f) Roughening the second solder resist layer so that the second solder resist layer has a roughened surface.

Step (a) provides a conductive copper layer with wiring patterns on an insulating substrate.

FIG. 1A is a schematic top view of a semi-finished flexible circuit board 10 created in this invention. Referring to FIG. 1A, a plurality of wiring patterns P composed of a conductive copper layer 110 are continuously formed on one surface of a thin-film strip-shaped insulating base material 100 of a semi-finished flexible circuit board 10. The insulating base material 100 has a plurality of transmission holes 101 for transfer on the upper and lower sides. The conductive copper layer 110 (or the wiring pattern P) defines a non-lead area Ps (the portion framed by the dotted line), which will be covered by the solder mask layer later to protect the circuit. The area other than the non-pin area Ps of the wiring pattern P is the pin area, which can be further divided into the inner pin area Ln, the outer pin area Lo, and the test pin area Lt as needed. The inner pin area Ln will be The chips are connected, the outer pin area Lo will be connected to a circuit board or other electronic devices, and the test pin area Lt is used to connect with a measuring instrument to detect the quality of the packaged chip. FIG. 1B is a schematic cross-sectional view of the place indicated by the arrow 1B in FIG. 1A (that is, one line of the wiring pattern P). Referring to FIG. 1B, it can be clearly understood that the conductive copper layer 110 is located on the insulating substrate 100. For the insulating base material 100, a material that is soft and has chemical resistance and heat resistance, such as polyester, polyamide, polyimide, or the like, can be used. The thickness of the insulating substrate 100 is generally 12 to 85 μm, preferably 20 to 50 μm. The formation of the conductive copper layer 110 with the wiring pattern P on the insulating substrate 100 is by a conventional lithography method. The thickness of the conductive copper layer 110 is, for example, 2 to 20 μm, preferably 5 to 12 μm.

Step (b): Form a first solder mask to partially cover the wiring pattern.

Referring to FIGS. 1A and 2, a first solder mask 121 is formed so as to cover at least partially The cover wiring pattern P covers, for example, a part or all of the non-lead area Ps. In the preferred embodiment, the first solder resist layer 121 only needs to be applied to certain specific areas of the non-lead area Ps, for example, only to be applied to the bending area generated when the rear end of the flexible circuit board product is applied. The actual position of this bending area varies depending on the characteristics of the back-end application product, and the area between the inner lead area Ln and the outer lead area Lo is the existing common bending area. Therefore, in the preferred embodiment of the present invention, the first solder mask 121 does not cover the non-pin area Ps between the test pin area Lt and the inner pin area Ln, but the present creation is not limited to this. This creation also has an embodiment in which the first solder mask 121 completely covers all the non-lead areas Ps. This step can be accomplished using screen printing techniques using conventional epoxy (o-Cresol Novalac/Phenol/DGEBA) type inks or other suitable inks. The thickness of the first solder resist layer 121 may be in the range of 3 to 15 μm.

Step (c) forming a first tin layer on the conductive copper layer using the first solder mask as a mask.

Referring to FIG. 3, a first tin layer 131 is formed on the conductive copper layer 110 using the first solder mask 121 as a mask. The first tin layer 131 is formed by conventional electroless plating (ie, electroless plating) technology. For example, the semi-finished product formed in step (b) is immersed in a tin bath containing sulfuric acid, potassium persulfate, or tin borofluoride for a predetermined period of time, washed with water, then blow dried, and then put into the oven for heat treatment. In this step, the first tin layer 131 is plated on the surface of the conductive copper layer 110 that is not covered by the first solder mask 121, and can further allow the tin plating solution to invade under the first edge 121a of the first solder mask 121 The conductive copper layer 110 thus forms a structure in which the first edge 121a of the first solder mask 121 covers the first side 131a of the first tin layer 131. The thickness of the first tin layer 131 may be in the range of 0.02 to 0.16 μm. In the preferred embodiment, the thickness of the first tin layer 131 is 0.10 μm.

Step (d): forming a second tin layer on the first tin layer using the first solder mask as a mask.

Referring to FIG. 4, a second tin layer 132 is formed on the first tin layer 131 using the first solder mask 121 as a mask. Preferably, there is no additional step of forming a solder mask between step (c) and step (d). As in step (c), the second tin layer 132 can be formed by a conventional electroless plating (ie, electroless plating) technique. For example, the semi-finished product formed in step (c) is immersed in a tin bath containing sulfuric acid, potassium persulfate, or tin fluoroboride for a predetermined period of time, washed with water, then blow dried, and then put into the oven for heat treatment. Step (c) The tin-copper alloy layer obtained by the first tin plating will generate Cu ₃ Sn through heat treatment at high temperature, which can slow down the formation and diffusion of Cu ₆ Sn ₅ of the tin layer produced by the second tin plating in step (d) Rate, which in turn slows down the pure tin layer loss rate, improves the eutectic bonding yield between the circuit and the wafer, and avoids tin whiskers. In this step, the tin plating solution can further invade under the first edge 121a of the first solder mask 121, forming the first edge 121a of the first solder mask 121 to cover the second side 132a of the second tin layer 132 Structure. The thickness of the second tin layer 132 may be in the range of 0.12 to 0.5 μm. In the preferred embodiment, the thickness of the second tin layer 132 is 0.28 μm. Because both steps (c) and (d) use electroless plating (ie, electroless plating) technology, and both use the first solder mask 121 as a mask, the first tin layer 131 will be covered by the second tin in step (d) The layer 132 advances toward a region with a high copper density, so that the interface Iss between the first tin layer 131 and the second tin layer 132 and the interface Isc between the first tin layer 131 and the conductive copper layer 110 are conformal.

Step (e) forming a second solder resist layer partially covering the second tin layer and at least partially covering the first solder resist layer.

Referring to FIG. 5, a second solder resist layer 122 is formed to partially cover the second tin layer 132 and at least partially cover the first solder resist layer 121. Preferably, the second solder resist layer 122 formed in this step at least covers the contact surface formed by the second tin layer 132 and the first solder resist layer 121 in step (d). In step (d), the first solder mask 121 is immersed in the tin bath, which may weaken the contact surface of the first solder mask 121 and the second tin layer 132, so the contact surface is covered by the second solder mask 122 It can prevent the solder mask from peeling off from the tin layer. Screen printing technology can be used to complete this step using conventional epoxy resin (o-Cresol Novalac/Phenol/DGEBA type) ink or other suitable inks. The thickness of the second solder resist layer 122 may be in the range of 3 to 20 μm. In this embodiment, the second solder mask layer 122 is printed on the entire area of the non-lead area Ps and thus completely covers the first solder mask layer 121, but the original creation is not limited to this. This composition also includes an embodiment in which the second solder resist layer 122 only partially covers the first solder resist layer 121 (only the outer edge thereof) and partially covers the second tin layer 132.

(f) Roughening the second solder resist layer so that the second solder resist layer has a roughened surface.

Referring to FIG. 6, after the printing and heat treatment curing of the second solder resist layer 122 is completed, a surface roughening treatment step is performed to form a second solder resist layer 122' having a roughened surface 601. This step can be accomplished using any suitable method. For example, physical roughening methods such as ball rolling, brushing, or frosting are used. The differential positioning brushing method is preferred. This method can control the brushing equipment and the surface of the second solder mask layer 122 to maintain a continuous and constant distance range through alumina abrasives or silicon carbide abrasives, thereby performing elastic brushing Grinding and lightweight cutting to achieve a roughening effect. Due to the difference in height between the surface of the second solder resist layer 122 and the second tin layer 132, the tin layer or wiring pattern is not rubbed during polishing. As shown in FIG. 6, after the roughening, the difference in height between the second tin layer 132 and the second solder resist layer 122' decreases, which can improve the phenomenon of poor crimping. Furthermore, the surface of the second solder resist layer 122' has a high roughness, which can also increase the surface area and strengthen the degree of bonding between it and potting glue. The potting compound is usually used to cover the inner lead area Ln, which needs to be tightly combined with the solder mask to protect the circuit between the IC chip and the inner lead. In this embodiment, preferably, the surface roughness Rz of the roughened surface 601 of the second solder resist layer 122' is: 0.04~5.0μm, preferably 0.16~4.5μm, more preferably 0.6~ 4.0μm. The surface roughness Rz is measured by cutting the roughened sample to a size of approximately 5 cm × 5 cm, and measuring it with a non-contact shape measurement laser microscope (KEYENCE Model VK-X100, Taiwan Keynes). During the measurement, the laser spot diameter is about 1μm, the objective magnification is set to 10X, the field of view is 1350μm x 1012μm, and the objective magnification is set to 20X, the field of view is 675μm x 506μm, the scanning time is about 10 to 20 seconds, and the line pitch is set to 2μm. .

The structure of the original soft circuit substrate

Referring to FIGS. 1A and 6 at the same time, in the first embodiment, the soft circuit substrate created for carrying a chip includes a conductive copper layer 110 having a wiring pattern P on an insulating substrate 100; a first tin layer 131 is located on the conductive copper layer 110 Above; the second tin layer 132 is located above the first tin layer 131; the first solder mask 121 covers the conductive copper layer 110 not covered by the first tin layer 131 and the second tin layer 132, and the first solder mask 121 is partially The second tin layer 132; and the second solder resist layer 122' partially covers the second tin layer 132 and at least partially covers the first solder resist layer 121, wherein the second solder resist layer 122' has a roughened surface In the surface 601, the surface roughness Rz of the roughened surface 601 ranges from 0.04 to 5 μm, preferably from 0.16 to 4.5 μm, and more preferably from 0.6 to 4.0 μm.

In another embodiment, referring to FIG. 6, the present invention provides a flexible circuit substrate for carrying a chip, wherein the first solder resist layer 121 has a first edge 121 a contacting the second tin layer 132.

In another embodiment, referring to FIG. 6, the present invention provides a flexible circuit substrate for carrying a wafer, wherein the first tin layer 131 has a first longitudinal interface 131 a ′ contacting the conductive copper layer 110, and the first solder mask layer 121 has a An edge 121a contacts the second tin layer 132, and the lateral distance X between the first longitudinal interface 131a' and the first edge 121a is greater than the thickness of the first tin layer 131.

In another embodiment, referring to FIG. 6, the present invention provides a flexible circuit substrate for carrying a chip, wherein the second tin layer 132 has a second longitudinal interface 132 a ′ contacting the first tin layer 131 and the first solder mask 121 Cover the second longitudinal interface 132a'.

In another embodiment, referring to FIG. 6, the present invention provides a flexible circuit substrate for carrying a chip, wherein the second tin layer 132 has a second longitudinal interface 132 a ′ contacting the first tin layer 131 and the second solder mask layer 122 ′ The second edge 122a contacts the second tin layer 132, and the lateral distance Y between the second longitudinal interface 132a' and the second edge 122a is greater than the thickness of the second tin layer 132.

In another embodiment, referring to FIG. 6, the present invention provides a flexible circuit substrate for carrying a chip, wherein the interface Iss of the first tin layer 131 and the second tin layer 132 is conformal to the first tin layer 131 and the conductive copper layer Interface of 110 Isc.

FIG. 7 shows that the first tin layer 131 and the second tin layer 132 are regarded as the tin layer 161 together, and the first solder mask 121 and the second solder resist layer 122' are regarded as the solder mask 162 together. The structural features of the flexible circuit substrate for carrying the chip include a conductive copper layer 110 with a wiring pattern P disposed on the insulating substrate 100; a tin layer 161 is located above the conductive copper layer 110, wherein the conductive copper layer 110 has a non-tin layer An exposed portion 163 covered by 161; and a solder resist layer 162 covering the exposed portion and partially covering the tin layer 161, wherein the tin layer 161 has a longitudinal interface 161a contacting the conductive copper layer 110, and the solder resist layer 162 has an edge 162a contacting The tin layer 161, wherein the lateral distance Z between the longitudinal interface 161a and the edge 162a is greater than the thickness of the solder resist layer 162 plus the thickness of the tin layer 161. In a preferred implementation For example, the thickness of the solder resist layer 162 ranges from 6 μm to 35 μm. In a preferred embodiment, the thickness of the tin layer 161 ranges from 0.1 μm to 0.6 μm.

This creation also has an embodiment that only performs step (c) without step (d). In this example, the thickness of the tin layer ranges from 0.1 μm to 0.6 μm.

The above are only the preferred embodiments of this creation and are not intended to limit the scope of patent applications for this creation; all other equivalent changes or modifications that have been made without departing from the spirit disclosed in this creation should be included in the following Within the scope of patent application.

100: insulating substrate

110: conductive copper layer

121: The first solder mask

121a: the first edge

122’: Second solder mask

122a: second edge

131: The first tin layer

131a: first side

131a’: the first vertical interface

132: Second tin layer

132a: second side

132a’: Second vertical interface

Ps: non-pin area

Iss: interface

Isc: interface

X: horizontal distance

Y: horizontal distance

Claims (15)

A flexible circuit substrate for carrying a chip includes: a conductive copper layer with a wiring pattern on an insulating substrate; a first tin layer above the conductive copper layer; and a second tin layer on the first tin layer Above; a first solder mask layer covers the conductive copper layer not covered by the first tin layer and the second tin layer, and the first solder mask layer partially covers the second tin layer; and a second solder mask The solder layer partially covers the second tin layer and at least partially covers the first solder mask layer, wherein the second solder mask layer has a roughened surface, and the surface roughness Rz of the roughened surface ranges from 0.04 to 5 μm. The flexible circuit board according to claim 1, wherein the surface roughness Rz ranges from 0.16 to 4.5 μm. The flexible circuit board according to claim 1, wherein the surface roughness Rz ranges from 0.6 to 4.0 μm. The flexible circuit board according to claim 1, wherein the first solder resist layer has a first edge contacting the second tin layer. The flexible circuit substrate of claim 1, wherein the first tin layer has a first longitudinal interface contacting the conductive copper layer, the first solder mask layer has a first edge contacting the second tin layer, the first The lateral distance between the longitudinal interface and the first edge is greater than the thickness of the first tin layer. The flexible circuit substrate according to claim 1, wherein the second tin layer has a second longitudinal interface contacting the first tin layer, and the first solder mask layer covers the second longitudinal interface. The flexible circuit substrate according to claim 1, wherein the second tin layer has a second longitudinal interface contacting the first tin layer, the second solder mask layer has a second edge contacting the second tin layer, the first The lateral distance between the two longitudinal interfaces and the second edge is greater than the thickness of the second tin layer. The flexible circuit substrate according to claim 1, wherein the interface between the first tin layer and the second tin layer is conformal to the interface between the first tin layer and the conductive copper layer. The flexible circuit substrate according to claim 1, wherein the wiring pattern has a test pin area, an inner pin area and an outer pin area, and the first solder mask layer is not covered between the test pin area and The wiring pattern between the inner pin areas. A flexible circuit substrate for carrying a chip, comprising: a conductive copper layer with a wiring pattern on an insulating substrate; a tin layer on top of the conductive copper layer, wherein the conductive copper layer is not covered by the tin layer An exposed portion covered; and a solder mask covering the exposed portion and partially covering the tin layer, wherein the solder mask has a roughened surface, and the surface roughness Rz of the roughened surface ranges from 0.04 to 5.0 μm. The flexible circuit board according to claim 10, wherein the surface roughness Rz of the roughened surface ranges from 0.16 to 4.5 μm. The flexible circuit board according to claim 10, wherein the roughness Rz of the roughened surface is 0.6 to 4.0 μm. The flexible circuit substrate according to claim 10, wherein the tin layer has a longitudinal interface contacting the conductor An electrical copper layer, the solder resist layer having an edge contacting the tin layer, wherein the lateral distance between the longitudinal interface and the edge is greater than the thickness of the solder resist layer plus the thickness of the tin layer. The flexible circuit board according to claim 10, wherein the thickness of the solder resist layer ranges from 6 μm to 35 μm. The flexible circuit substrate according to claim 10, wherein the thickness of the tin layer ranges from 0.1 μm to 0.6 μm.

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