CN209515608U - For carrying the soft circuit base plate of chip - Google Patents
For carrying the soft circuit base plate of chip Download PDFInfo
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- CN209515608U CN209515608U CN201920682560.8U CN201920682560U CN209515608U CN 209515608 U CN209515608 U CN 209515608U CN 201920682560 U CN201920682560 U CN 201920682560U CN 209515608 U CN209515608 U CN 209515608U
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Abstract
The utility model provides a kind of for carrying the soft circuit base plate of chip, and include: the conductive copper layer with Wiring pattern is located on an insulating substrate；One first tin layers are located above the conductive copper layer；One second tin layers are located above first tin layers；One first soldermask layer, the conductive copper layer that covering is not covered by first tin layers and second tin layers, and first soldermask layer partly covers second tin layers；And one second soldermask layer, it partly covers second tin layers and at least partly covers first soldermask layer.The soft circuit base plate of the utility model to be coated with top layer anti-solder ink after the completion of last tin layers, in case top layer anti-solder ink is immersed in pot.
Description
Technical field
The utility model relates to soft circuit base plates, in particular to can bearing semiconductor chip soft circuit base plate.
Background technique
The soft circuit base plate for carrying chip is mostly to roll strip form film.The in the industry cycle knot of soft circuit base plate and chip
Closing has various addresses, such as TCP (Tape Carrier Package tape-carrier-package) or COF according to different assembly modes
(Chip On Film thin membrane flip chip encapsulation).TCP and COF is the carrier with soft circuit base plate as encapsulation chip, is led to
Hot pressing is crossed by the interior pin of the copper wiring pattern of golden convex block (Gold B μm p) and position on flexible base plate circuit on chip
(Inner Lead) engagement.
In order to connect the golden convex block of flexible base plate circuit and chip, it is necessary to have the presence of Sn/Au eutectic object, wherein gold
It is provided by the golden convex block of chip, tin is just supplied by the tin for being formed in interior pin surface, and therefore, the surface of interior pin is coated with tin layers.
Other than interior pin, for copper wiring pattern there are also the conductive terminal that outer pin etc. is connect with other electronic building bricks, these terminals are usual
Also there is tin coating.Non-pinned area can be separately protected with anti-solder ink covering on copper wiring pattern.
Existing flexible base plate circuit is also easy to produce following problems, and one is that tin plating layer surface forms whisker, leads to adjacent lines
Short out road；Secondly generating pothole for the interface of anti-solder ink and tin coating, lead to rupture of line.1 (Japan Patent of patent document
JP3061613) scheme disclosed is first comprehensively to form flash plating tin layers (a) on copper wiring pattern, then in Wiring pattern
Non-pinned area is coated with anti-solder ink, forms thick tin coating (b) then at pin area later.Patent document 1 thinks that copper wiring pattern is complete
The flash plating tin layers (a) that face is formed can prevent pothole from generating, and thick tin coating (b) can prevent whisker.(Taiwan is special for patent document 2
Sharp TW531864) another method is disclosed, it is to sequentially form the first anti-solder ink in non-pinned area, formation flash plating tin layers in pin
Area re-forms the second anti-solder ink and covers the intersection of the first anti-solder ink and thin layer of tin and eventually form thick tin coating thin
In tin layers.
Utility model content
The bright people of the application has found the above-mentioned prior art after studying, and there are still many problems in practical operation.Citing and
Speech, the flash plating tin layers that patent document 1 is formed comprehensively in copper wiring pattern, this product bent to needs is unfavorable, because of plating
The hardness of tin layers is usually higher.In addition, whether patent document 1 or patent document 2 all indicate finally coating anti-solder ink it
Form thick tin coating afterwards, therefore the anti-solder ink of top layer can still be immersed in a period of time in pot, especially plate thick tin when
Between it is again longer, this chance for making the interface of top layer anti-solder ink and thick tin coating generate pothole increases.In addition, patent document 2
Have and, just into the processing procedure of molten tin bath, causes to clean by the high cost of anti-solder ink pollution molten tin bath after applying anti-solder ink twice.Also, patent
Anti-solder ink is tin plating twice twice indicated by document 2 staggeredly implements processing procedure, easily obscures in practical operation, causes production moving-wire peace
The puzzlement of row.
In view of above-mentioned, on the one hand, the utility model proposes a kind of manufacturing methods of novel soft circuit base plate, are not necessarily to
Anti-solder ink is tin plating twice twice staggeredly implements processing procedure.Meanwhile the utility model is also coated with top layer after the completion of last tin layers and prevents
Solder paste ink, in case top layer anti-solder ink is immersed in pot.
It is preferred that another aspect the utility model also includes to be formed by soft circuit base plate by above-mentioned various methods
Various structures.
According to an embodiment, the utility model provides a kind of for carrying the soft circuit base plate of chip, includes:
A conductive copper layer with Wiring pattern is located on an insulating substrate；One first tin layers are located on the conductive copper layer
Side；One second tin layers are located above first tin layers；One first soldermask layer covers not by first tin layers and second tin layers
The conductive copper layer of covering, and first soldermask layer partly covers second tin layers；And one second soldermask layer, it partly covers
Second tin layers and at least partly cover first soldermask layer.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has one the
One EDGE CONTACT, second tin layers.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has one first
There is a first edge to contact second tin layers, first longitudinal direction circle for longitudinal interfacial contact conductive copper layer, first soldermask layer
The lateral distance of face and the first edge is greater than the thickness of first tin layers.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has one second
Longitudinal interfacial contact first tin layers, first soldermask layer cover the second longitudinal direction interface.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has one second
There is a second edge to contact second tin layers, second longitudinal direction circle for longitudinal interfacial contact first tin layers, second soldermask layer
The lateral distance of face and the second edge is greater than the thickness of second tin layers.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, first tin layers and second tin
The conformal interface in first tin layers and the conductive copper layer in interface of layer.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a test
Pin area, pin area and an outer pin area in one, first soldermask layer do not cover between the test pin area and the interior pin area
Between the Wiring pattern.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a roughening
Copper face.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a roughening
Tin face, the surface roughness range in the roughening tin face are as follows: 0.045 μm~0.5 μm.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a roughening
Tin face, the surface roughness range in the roughening tin face are 0.06 μm~0.35 μm.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a roughening
Tin face, the surface roughness range in the roughening tin face are 0.1 μm~0.3 μm.
On the other hand, the utility model provides a kind of for carrying the soft circuit base plate of chip, includes: a conductive copper
Layer has a Wiring pattern and is arranged on an insulating substrate；One tin layers are located above the conductive copper layer, wherein the conductive copper
Layer has the exposed portion not covered by the tin layers；And one soldermask layer cover the exposed portion and partly cover the tin
Layer, wherein the tin layers have the longitudinal interfacial contact conductive copper layer, which has the EDGE CONTACT tin layers, wherein should
The lateral distance at longitudinal interface and the edge is greater than the thickness of the tin layers.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, and the thickness range of the soldermask layer is from 6
μm to 35 μm.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, and the thickness ranges of the tin layers is from 0.1
μm to 0.6 μm.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a roughening tin face,
The surface roughness range in the roughening tin face are as follows: 0.045 μm~0.5 μm.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, which has a roughening tin face,
The surface roughness range in the roughening tin face are as follows: 0.06 μm~0.35 μm.
According to an embodiment, the utility model provides soft circuit base plate as the aforementioned, the surface roughness in the roughening tin face
Range is 0.1 μm~0.3 μm.
Detailed description of the invention
Figure 1A is soft circuit base plate semi-finished product schematic top plan view of the utility model according to an embodiment.
Figure 1B is the diagrammatic cross-section of certain specific region in the semi-finished product of Figure 1A.
Figure 1B and Fig. 2 to Fig. 5 shows that the utility model is each according to the soft circuit base plate manufacturing process of a first embodiment
Step diagrammatic cross-section.
Fig. 6 is structural schematic diagram of the utility model according to the soft circuit base plate of an embodiment.
Fig. 7 is structural schematic diagram of the utility model according to the soft circuit base plate of a second embodiment.
Specific embodiment
It demonstrates the preferred embodiment of the utility model below with reference to institute's accompanying drawings.To avoid in fuzzy the utility model
Hold, illustrates also to omit existing component, associated materials and its correlation processing technique below.Meanwhile this is practical new to clearly illustrate
Type, each component may not be drawn by actual size or relative scale in institute's accompanying drawings.
The manufacturing method of the soft circuit base plate of the utility model
The manufacturing method of the soft circuit base plate for carrying chip according to first embodiment the utility model, is sequentially wrapped
Contain:
Step (a), which provides, has a conductive copper layer of Wiring pattern on an insulating substrate；
Step (b) forms one first soldermask layer and partly covers the Wiring pattern；
Step (c) is that shielding forms one first tin layers on the conductive copper layer with first soldermask layer；
Step (d) is that shielding forms one second tin layers in first tin layers with first soldermask layer；And step (e) formation
One second soldermask layer partly covers second tin layers and at least partly covers first soldermask layer.
Step (a), which provides, has a conductive copper layer of Wiring pattern on an insulating substrate.
Figure 1A is soft 10 schematic top plan view of circuit base plate semi-finished product of the utility model.With reference to Figure 1A, soft route base
It is continuously formed in the one side of the insulating substrate 100 of the film type of boards half-finished product 10 and multiple to be made of conductive copper layer 110
Wiring pattern P.The two sides up and down of insulating substrate 100 have multiple driving holes 101 of transfer.Conductive copper layer 110 (or wiring diagram
Case P) a non-pinned area Ps (part being framed with dotted line) is defined, this region will be covered in subsequent by soldermask layer with protective wire
Road.Region, that is, pin area other than the non-pinned area Ps of Wiring pattern P, can repartition into interior pin area Ln, outer pin area Lo and
Optionally existing test pin area Lt, interior pin area Ln will connect with chip, outer pin area Lo by external circuits plate or other
Electronic device, test pin area Lt are then used to connect with measuring instrument, to detect the quality of encapsulation chip.Figure 1B is arrow in Figure 1A
The diagrammatic cross-section of the signified place of head 1B (i.e. Wiring pattern P wherein a route).With reference to Figure 1B, it will be clearly understood that conductive copper layer
110 are located on insulating substrate 100.Soft and material with resistance to chemical reagents and heat resistance can be used in insulating substrate 100, such as poly-
Ester, polyamide, polyimides etc..The thickness of insulating substrate 100 is generally 12 μm to 85 μm, preferably 20 μm to 50 μm.Exhausted
The conductive copper layer 110 that tool Wiring pattern P is formed on edge substrate 100 is by existing lithography process.The thickness example of conductive copper layer 110
Such as 2 μm to 20 μm, preferably 5 μm to 12 μm.
Step (b) forms one first soldermask layer and partly covers the Wiring pattern.
With reference to Figure 1A and Fig. 2, forming one first soldermask layer 121 makes it at least partly cover Wiring pattern P, such as covers
Part or all of non-pinned area Ps.In preferred embodiment, the first need of soldermask layer 121 are applied to the certain of non-pinned area Ps
Specific region, the bending region generated when for example need to only be applied to the backend application of this soft circuit base plate product.This bent area
The physical location in domain depending on backend application product characteristic and change, wherein the area between interior pin area Ln and outer pin area Lo
Domain is existing common bending region.Therefore, in the preferred embodiment of the utility model, the first soldermask layer 121 do not cover between
Non-pinned area Ps between test pin area Lt and interior pin area Ln, however the utility model is not limited.The utility model
Also the embodiment for having the first soldermask layer 121 that all non-pinned area Ps are completely covered.Existing epoxy resin (o- can be used
Cresol Novalac/Phenol/DGEBA) type ink or other suitable ink this step completed with screen printing technology
Suddenly.The thickness of first soldermask layer 121 can be in 3 μm to 15 μm of range.
Step (c) is that shielding forms one first tin layers on the conductive copper layer with first soldermask layer.
It is that shielding forms one first tin layers 131 on conductive copper layer 110 with the first soldermask layer 121 with reference to Fig. 3.By existing
There is electroless plating (i.e. electroless plating) technology to form the first tin layers 131.Such as step (b) is formed by semi-finished product and is soaked in
It washes after one section of predetermined time in the molten tin bath of the tin plating electrolyte of sulfur acid, potassium peroxydisulfate or fluoroboration tin and dries up again, reenter later roasting
Case is heat-treated.In this step, the first tin layers 131 are not covered by the first soldermask layer 121 except being plated on conductive copper layer 110
Outside the surface of lid, tin plating electrolyte can further be made to invade the conductive copper layer 110 under the first edge 121a of the first soldermask layer 121,
Therefore the first edge 121a of the first soldermask layer 121 of formation covers the structure of the first side 131a of the first tin layers 131.First
The thickness of tin layers 131 can in 0.02 μm to 0.16 μm of range, the first tin layers 131 of preferred embodiment with a thickness of 0.10 μm.
Step (d): being that shielding forms one second tin layers in first tin layers with first soldermask layer.
It is that shielding forms the second tin layers 132 in the first tin layers 131 with the first soldermask layer 121 with reference to Fig. 4.For it is preferred that,
Not the step of soldermask layer is not additionally formed between step (c) and step (d).Existing electroless plating can be passed through such as step (c)
(i.e. electroless plating) technology forms the second tin layers 132.Such as step (c) is formed by semi-finished product and is soaked in sulfur acid, over cure
It washes after one section of predetermined time in the molten tin bath of the tin plating electrolyte of sour potassium or fluoroboration tin and dries up again, reenter oven later and carry out hot place
Reason.Step (c) first time tin plating gun-metal layer obtained can generate Cu by being heat-treated high temperature3Sn, this can slow down
The Cu of second of step (d) tin plating generated tin layers6Sn5Generation diffusion rate, and then slow down pure stannum layer detraction rate, mention
Elevated track and chip chamber eutectic bonding acceptance rate, and avoid generating tin palpus.In this step, tin plating electrolyte intrusion the can further be made
Under the first edge 121a of one soldermask layer 121, the first edge 121a for forming the first soldermask layer 121 covers the second tin layers
The structure of 132 second side 132a.The thickness of second tin layers 132 can in 0.12 μm to 0.5 μm of range, preferred embodiment
Second tin layers 132 with a thickness of 0.28 μm.Because step (c) and (d) use electroless plating (i.e. electroless plating) technology, and
It is all shielding with the first soldermask layer 121, therefore the area high toward copper density by the second tin layers 132 in the meeting of the first tin layers of step (d) 131
Domain promotes, so that the interface of the interface I ss and the first tin layers 131 and conductive copper layer 110 of the first tin layers 131 and the second tin layers 132
Isc conformal (conformal).
Step (e) forms that one second soldermask layer partly covers second tin layers and at least partly to cover this first anti-welding
Layer.
With reference to Fig. 5, forms one second soldermask layer 122 and partly cover the second tin layers 132 and at least partly cover first
Soldermask layer 121.For it is preferred that, this step forms the second soldermask layer 122 and is at least covered in the second tin layers of step (d) 132 and first
Soldermask layer 121 is formed by contact surface.In step (d), the first soldermask layer 121 is immersed in molten tin bath, it might therefore weaken first
The contact surface of soldermask layer 121 and the second tin layers 132, thus using the second soldermask layer 122 by this contact surface covering can avoid it is anti-welding
Layer is removed from tin layers.Can be used existing epoxy resin (o-Cresol Novalac/Phenol/DGEBA type) type ink or
Other suitable ink complete this step with screen printing technology.The thickness of second soldermask layer 122 can be in 3 μm to 20 μm of model
It encloses.In this embodiment, the second soldermask layer 122 is to print to the non-pinned area Ps whole district therefore cover all the first soldermask layer 121,
However the utility model is not limited.The utility model also includes that only to partly cover first anti-welding for the second soldermask layer 122
121 (only covering its outer rim) of layer and the embodiment for partly covering the second tin layers 132.
The structure of the soft circuit base plate of the utility model
With reference to Figure 1A and Fig. 5, it is used to carry the soft circuit base plate packet of chip in first embodiment the utility model
Containing the conductive copper layer 110 with Wiring pattern P on insulating substrate 100；First tin layers 131 are located at 110 top of conductive copper layer；The
Two tin layers 132 are located at 131 top of the first tin layers；The covering of first soldermask layer 121 is not covered by the first tin layers 131 and the second tin layers 132
The conductive copper layer 110 of lid, and the first soldermask layer 121 partly covers the second tin layers 132；And second soldermask layer 122 partly cover
The second tin layers of lid 132 and at least partly cover the first soldermask layer 121.
In another embodiment, can refer to Fig. 5, the utility model provides the soft circuit base plate for carrying chip,
In the first soldermask layer 121 have a first edge 121a contact the second tin layers 132.
In another embodiment, can refer to Fig. 5, the utility model provides the soft circuit base plate for carrying chip,
In the first tin layers 131 have first longitudinal direction interface 131a contact conductive copper layer 110, the first soldermask layer 121 have first edge
121a contacts the second tin layers 132, and the lateral distance X of first longitudinal direction interface 131a and first edge 121a is greater than the first tin layers 131
Thickness.
In another embodiment, can refer to Fig. 5, the utility model provides the soft circuit base plate for carrying chip,
In the second tin layers 132 there is second longitudinal direction interface 132a to contact first tin layers 131, the first soldermask layer 121 covers second longitudinal direction
Interface 132a.
In another embodiment, can refer to Fig. 5, the utility model provides the soft circuit base plate for carrying chip,
In the second tin layers 132 have second longitudinal direction interface 132a contact the first tin layers 131, the second soldermask layer 122 have second edge
122a contacts the second tin layers 132, and the lateral distance Y of second longitudinal direction interface 132a and second edge 122a is greater than the second tin layers 132
Thickness.
In another embodiment, can refer to Fig. 5, the utility model provides the soft circuit base plate for carrying chip,
In the conformal interface I sc in the first tin layers 131 and conductive copper layer 110 of the interface I ss of the first tin layers 131 and the second tin layers 132.
Fig. 6 is shown is considered as tin layers 161 for above-mentioned first tin layers 131 and the second tin layers 132 together, by the first soldermask layer 121
And second soldermask layer 122 when being considered as soldermask layer 162 together, the utility model is used to carry the structure of the soft circuit base plate of chip
Feature is comprising a conductive copper layer 110 there is Wiring pattern P to be set on insulating substrate 100；One tin layers 161 are located at conductive copper layer
110 tops, wherein conductive copper layer 110 has the exposed portion 163 not covered by tin layers 161；And one soldermask layer 162 cover
Exposed portion and tin layers 161 are partly covered, wherein tin layers 161 have longitudinal direction interface 161a contact conductive copper layer 110, anti-welding
There is layer 162 an edge 162a to contact tin layers 161, wherein the lateral distance Z of longitudinal direction interface 161a and edge 162a is greater than tin layers
161 thickness.The thickness range of the soldermask layer is from 6 μm to 35 μm.The thickness range of the tin layers is from 0.14 μm to 0.66 μm.This
Outside, the utility model, which also has, only carries out step (c) and the embodiment without step (d), this example tin layers thickness range from
0.1 μm to 0.6 μm.
There are also a second embodiments for the utility model, with first embodiment the difference is that step (a) further includes " before tin plating
So that conductive copper layer has the step of a roughening copper face, remaining step is all identical with the first embodiment for conductive copper layer roughening ".It is conductive
Any appropriate method can be used to complete for layers of copper roughening.For example, can patterned conductive copper layer 110 formed Wiring pattern P it
Afterwards, with chemical solution handles the conductive copper layer (Wiring pattern P) and is formed.In this embodiment, chemical solution may be, for example,
Potassium sulfate (K2S2O8) solution, suitable concentration is 30~40g/L, sulfuric acid or hydrochloric acid solution, and suitable concentration is 20~30g/L.
Conductive copper layer (Wiring pattern P) can be immersed in chemical solution 10~30 seconds at room temperature.With the time of contact of chemical solution
Longer surface roughness can be bigger.Fig. 7 is the tin plating structural schematic diagram with soldermask layer of completion of second embodiment.On roughening copper face
It is tin plating that tin face can also be made to generate the roughening structure for being similar to roughening copper face.As shown, roughened conductive copper layer 110 ' has
It is roughened copper face 701, therefore the first tin layers 131 ' being subsequently formed and the second tin layers 132 ' have similar coarse surface, are such as roughened
Tin face 702 and roughening tin face 703.It has been observed that roughening tin face can provide biggish surface area.When soft circuit base plate is external to it
When his electronic building brick, the roughening tin face in outer pin region can make it become larger with anisotropic conductive film (ACF) bonded area, and then make
Soft circuit base plate with electronic device is even closer is bonded.For it is preferred that, the surface in the roughening tin face 703 of the second tin layers 132 '
Rugosity Rz range are as follows: 0.045 μm~0.5 μm, preferred scope is 0.06 μm~0.35 μm, more preferred range is μm 0.1~
0.3μm.The measurement of surface roughness Rz is will to complete tin plating sample to cut into about 5cm × 5cm size, with non-contacting-type shape
Measure laser microscopes (the model VK-X100 of the Taiwan KEYENCE Ji Ensi) measurement.Be when measurement using laser point light diameter about
1 μm, object lens multiplying power sets 10X, and 1350 μm of field range, 1012 μm of x and object lens multiplying power set 20X, and 675 μm of field range
506 μm of x, with sweep time about 10~20 seconds, line-spacing pitch set 2 μm and measures.
The above descriptions are merely preferred embodiments of the present invention, and the right being not intended to limit the utility model is wanted
Seek range；It is all other without departing from the lower equivalent change or modification completed of the revealed spirit of the utility model, it should be included in
In following scopes of the claims.
[symbol description]
10 soft circuit base plate semi-finished product
100 insulating substrates
101 driving holes
110 conductive copper layers
P Wiring pattern
1B is with reference to figure
Lo outer pin area
The non-pinned area Ps
Pin area in Ln
Lt test pin area
121 first soldermask layers
121a first edge
131 first tin layers
The first side 131a
The interface Iss
The interface Isc
132 second tin layers
122 second soldermask layers
122a second edge
The second side 132a
X lateral distance
Y lateral distance
161 tin layers
The longitudinal direction 161a interface
162 soldermask layers
The edge 162a
163 exposed portion
Z lateral distance
110 ' conductive copper layers
132 ' second tin layers
131 ' first tin layers
701 roughening copper faces
702 roughening tin faces
703 roughening tin faces
Claims (17)
1. it is a kind of for carrying the soft circuit base plate of chip, characterized by comprising:
A conductive copper layer with Wiring pattern is located on an insulating substrate；
One first tin layers are located above the conductive copper layer；
One second tin layers are located above first tin layers；
One first soldermask layer, the conductive copper layer that covering is not covered by first tin layers and second tin layers, and this is first anti-welding
Layer partly covers second tin layers；And
One second soldermask layer partly covers second tin layers and at least partly covers first soldermask layer.
2. soft circuit base plate according to claim 1, which is characterized in that there is first soldermask layer first edge to connect
Touch second tin layers.
3. soft circuit base plate according to claim 1, which is characterized in that first tin layers have a first longitudinal direction interface
Contact the conductive copper layer, which there is a first edge to contact second tin layers, the first longitudinal direction interface and this
The lateral distance at one edge is greater than the thickness of first tin layers.
4. soft circuit base plate according to claim 1, which is characterized in that second tin layers have a second longitudinal direction interface
First tin layers are contacted, which covers the second longitudinal direction interface.
5. soft circuit base plate according to claim 1, which is characterized in that second tin layers have a second longitudinal direction interface
Contact first tin layers, which there is a second edge to contact second tin layers, the second longitudinal direction interface and this
The lateral distance at two edges is greater than the thickness of second tin layers.
6. soft circuit base plate according to claim 1, which is characterized in that the interface of first tin layers and second tin layers
The conformal interface in first tin layers and the conductive copper layer.
7. soft circuit base plate according to claim 1, which is characterized in that the Wiring pattern has a test pin area,
Pin area and an outer pin area in one, first soldermask layer do not cover being somebody's turn to do between the test pin area and the interior pin area
Wiring pattern.
8. soft circuit base plate according to claim 1, which is characterized in that the conductive copper layer has a roughening copper face.
9. soft circuit base plate according to claim 1, which is characterized in that second tin layers have a roughening tin face, should
It is roughened the surface roughness range in tin face are as follows: 0.045 μm~0.5 μm.
10. soft circuit base plate according to claim 1, which is characterized in that second tin layers have a roughening tin face, should
It is roughened the surface roughness range in tin face are as follows: 0.06 μm~0.35 μm.
11. soft circuit base plate according to claim 1, which is characterized in that second tin layers have a roughening tin face, should
It is roughened the surface roughness range in tin face are as follows: 0.1 μm~0.3 μm.
12. it is a kind of for carrying the soft circuit base plate of chip, characterized by comprising:
One conductive copper layer has a Wiring pattern and is set on an insulating substrate；
One tin layers are located above the conductive copper layer, and wherein the conductive copper layer has the exposed portion not covered by the tin layers；
And
One soldermask layer covers the exposed portion and partly covers the tin layers,
Wherein the tin layers have the longitudinal interfacial contact conductive copper layer, which has the EDGE CONTACT tin layers, wherein
The lateral distance at the longitudinal direction interface and the edge is greater than the thickness of the tin layers.
13. soft circuit base plate according to claim 12, which is characterized in that the thickness range of the soldermask layer from 6 μm to
35μm。
14. soft circuit base plate according to claim 12, which is characterized in that the thickness range of the tin layers from 0.1 μm to
0.6μm。
15. soft circuit base plate according to claim 12, which is characterized in that the tin layers have a roughening tin face, this is thick
Change the surface roughness range in tin face are as follows: 0.045 μm~0.5 μm.
16. soft circuit base plate according to claim 12, which is characterized in that the tin layers have a roughening tin face, this is thick
Change the surface roughness range in tin face are as follows: 0.06 μm~0.35 μm.
17. soft circuit base plate according to claim 12, which is characterized in that the tin layers have a roughening tin face, this is thick
Change the surface roughness range in tin face are as follows: 0.1 μm~0.3 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920682560.8U CN209515608U (en) | 2019-05-13 | 2019-05-13 | For carrying the soft circuit base plate of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920682560.8U CN209515608U (en) | 2019-05-13 | 2019-05-13 | For carrying the soft circuit base plate of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209515608U true CN209515608U (en) | 2019-10-18 |
Family
ID=68189152
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201920682560.8U Active CN209515608U (en) | 2019-05-13 | 2019-05-13 | For carrying the soft circuit base plate of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209515608U (en) |
-
2019
- 2019-05-13 CN CN201920682560.8U patent/CN209515608U/en active Active
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