CN210431372U - Narrow pulse peak value sampling hold circuit - Google Patents
Narrow pulse peak value sampling hold circuit Download PDFInfo
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- CN210431372U CN210431372U CN201921418001.2U CN201921418001U CN210431372U CN 210431372 U CN210431372 U CN 210431372U CN 201921418001 U CN201921418001 U CN 201921418001U CN 210431372 U CN210431372 U CN 210431372U
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Abstract
The utility model discloses a narrow pulse peak value sample hold circuit, which comprises a peak value signal sample hold part, a comparator control part, a capacitance voltage compensation part, a following output part and a DSP signal control processing part, wherein the comparator control part, the capacitance voltage compensation part, the following output part and the DSP signal control processing part are respectively connected with the peak value signal sample hold part; the comparator control part comprises a second operational amplifier and a fifth resistor and is used for controlling a second analog switch of the peak signal sampling and holding part to be switched off at the peak value and cutting off a leakage current channel of a sampling capacitor of the peak signal sampling and holding part; the capacitance voltage compensation part comprises a first junction field effect transistor, a third resistor and a first capacitor and is used for compensating the voltage loss of the sampling capacitor caused by the charging of the junction capacitor of the second junction field effect transistor of the peak signal sampling and holding part. The utility model discloses the circuit has the characteristics of high-speed high accuracy, is applicable to the occasion of drawing high-speed narrow pulse peak value.
Description
Technical Field
The utility model belongs to the technical field of the technique of power device junction temperature monitoring and specifically relates to indicate a narrow pulse peak value sample hold circuit.
Background
In the on-line monitoring of the junction temperature of the power device, the method for extracting the junction temperature by using an electrical parameter method is a new method. Wherein the peak induced voltage generated by the parasitic inductance of the source at the moment of device turn-off is related to its junction temperature. The off time of a general device is hundreds of nanoseconds, the high-speed device is even as low as tens of nanoseconds, the rise time of a pulse peak generated in the high-speed device is shorter, and the amplitude is also changed, so that the design of a high-precision nanosecond-level high-speed narrow pulse peak value sampling and holding circuit is one of necessary conditions for realizing junction temperature online monitoring by using the method.
However, the existing peak value sampling and holding circuit has the defects of insufficient bandwidth, slow tracking speed and insufficient precision. In order to meet the speed requirement, most of the adopted sampling capacitors are pF-level small capacitors, after the peak value is reached, the parasitic capacitors of the diodes can cause the leakage of charges, the voltage held by the sampling capacitors can be reduced to a certain degree, and the precision of the sampling peak value is influenced.
SUMMERY OF THE UTILITY MODEL
The utility model aims to overcome prior art's shortcoming and not enough, provide a narrow pulse peak value sample hold circuit, have the characteristics of high-speed high accuracy, be applicable to the occasion of drawing high-speed narrow pulse peak value.
In order to achieve the above object, the present invention provides a technical solution: a narrow pulse peak value sampling hold circuit comprises a peak value signal sampling hold part, a comparator control part, a capacitance voltage compensation part, a following output part and a DSP signal control processing part, wherein the comparator control part, the capacitance voltage compensation part, the following output part and the DSP signal control processing part are respectively connected with the peak value signal sampling hold part; the comparator control part comprises a second operational amplifier and a fifth resistor and is used for controlling a second analog switch of the peak signal sampling and holding part to be turned off at the peak value, cutting off a leakage current channel of a sampling capacitor of the peak signal sampling and holding part and reducing voltage loss, and the capacitor voltage compensation part comprises a first junction field effect transistor, a third resistor and a first capacitor and is used for compensating the voltage loss on the sampling capacitor caused by the charging of a junction capacitor of a second junction field effect transistor of the peak signal sampling and holding part; the non-inverting input end of the second operational amplifier is connected with the inverting input end of the first operational amplifier, one end of a sixth resistor and the grid electrode of the first junction field effect transistor of the peak signal sampling and holding part respectively, the output end of the second operational amplifier is connected with one end of a fifth resistor, and the other end of the fifth resistor is connected with the control end of the second analog switch of the peak signal sampling and holding part; the grid of the first junction type field effect transistor is connected with the inverting input end of the second operational amplifier, the inverting input end of the first operational amplifier and one end of the sixth resistor respectively, the source electrode and the drain electrode of the first junction type field effect transistor are connected with one end of the third resistor respectively, the other end of the third resistor is connected with one end of the first capacitor, and the other end of the first capacitor is connected with one end of the second analog switch of the peak signal sampling and holding part and the output end of the first operational amplifier respectively.
Further, the peak signal sampling and holding part samples the peak value of the narrow pulse input signal Vin, and comprises a first analog switch, a first resistor, a second resistor, a first operational amplifier, a second analog switch, a fourth resistor, a second junction field effect transistor, a sixth resistor, a third analog switch and a second capacitor serving as a sampling capacitor, and the following output part comprises a seventh resistor, a first triode and an eighth resistor; wherein, the connection and disconnection of the first analog switch and the third analog switch are controlled by a DSP signal control processing part through a DSP chip, the narrow pulse input signal Vin is connected with one end of the first analog switch, the other end of the first analog switch is respectively connected with one end of a first resistor, one end of a second resistor and the same-phase input end of a second operational amplifier, the other end of the first resistor is connected with the ground, the other end of the second resistor is connected with the same-phase input end of the first operational amplifier, the reverse-phase input end of the first operational amplifier is respectively connected with the reverse-phase input end of the second operational amplifier, the grid electrode of a first junction field effect tube and one end of a sixth resistor, the output end of the first operational amplifier is respectively connected with one end of the second analog switch and one end of a first capacitor, the other end of the second analog switch is connected with one end of a fourth resistor, and the other end of the fourth resistor is connected with the grid electrode of the second junction field effect tube, the source electrode and the drain electrode of the second junction field effect transistor are respectively connected with a third analog switch, one end of a second capacitor and one end of a seventh resistor, the other end of the second capacitor is connected with the other end of the third analog switch and the ground, and the other end of the sixth resistor is respectively connected with the emitting electrode of the first triode and one end of an eighth resistor; one end of the seventh resistor is connected with a source electrode and a drain electrode of the second junction field effect transistor, one end of the third analog switch and one end of the second capacitor, the other end of the seventh resistor is connected with a base electrode of the first triode, a collector electrode of the first triode is connected with the ground, an emitter of the first triode is connected with one end of the eighth resistor, the other end of the eighth resistor is connected with a sampled output voltage Vout, and the output voltage Vout is sampled and stored through an ADC module of the DSP chip.
Further, the first operational amplifier is a transconductance operational amplifier.
Further, the second operational amplifier is a low-delay high-speed comparator.
Compared with the prior art, the utility model, have following advantage and beneficial effect:
1. the utility model discloses what the circuit adopted is transconductance type operational amplifier, and its bandwidth is high, and the output impedance is big, and output current is big, satisfies the requirement for sampling electric capacity quick charge.
2. The utility model discloses the circuit adopts the junction field effect transistor to replace schottky diode, has low junction electric capacity, and the characteristics of low leakage current reduce the loss of sample hold electric capacity charge.
3. The utility model discloses the circuit adopts low delay high speed comparator control analog switch to turn-off in peak value department, cuts off the electric leakage stream channel of sample holding capacitance, reduces voltage loss.
4. The utility model discloses the circuit adopts the voltage loss of the sampling electric capacity that compensation capacitance compensation junction field effect transistor's junction electric capacity charges and leads to, improves the sampling precision.
Therefore, the utility model discloses the circuit has the characteristics of high-speed high accuracy, is applicable to the occasion of extracting high-speed narrow pulse peak value.
Drawings
FIG. 1 is a schematic diagram of a narrow pulse peak sample and hold circuit; in the figure, Signal input control is a control Signal sent by the DSP to control the first analog switch S1, and is used for controlling the input and disconnection of the input Signal Vin; the hold control is a control signal generated by the second operational amplifier U2 and used for controlling the on-off of the second analog switch S2; the clear signal is a control signal sent by the DSP to control the on/off of the third analog switch S3, and is used to clear or maintain the voltage on the second capacitor C2.
Fig. 2 is a waveform diagram of an input signal Vin, a voltage at an output end of the second operational amplifier U2, and an output signal Vout.
Detailed Description
The present invention will be further described with reference to the following specific embodiments.
As shown in fig. 1, the narrow pulse peak value sample-and-hold circuit provided by the present embodiment includes a peak value signal sample-and-hold section 1, a comparator control section 2, a capacitance voltage compensation section 3, a following output section 4, and a DSP signal control processing section 5, where the comparator control section 2, the capacitance voltage compensation section 3, the following output section 4, and the DSP signal control processing section 5 are respectively connected to the peak value signal sample-and-hold section 1; the peak signal sampling and holding part 1 performs peak sampling on the narrow pulse input signal Vin, and comprises a first analog switch S1, a first resistor R1, a second resistor R2, a first operational amplifier U1, a second analog switch S2, a fourth resistor R4, a second junction field effect transistor J1, a sixth resistor R6, a third analog switch S3 and a second capacitor C2 serving as a sampling capacitor; the following output part comprises a seventh resistor R7, a first triode U3 and an eighth resistor R8 and is used for following output of the voltage of the sampling capacitor and isolating the influence of the output voltage on the front stage; the comparator control part 2 comprises a second operational amplifier U2 and a fifth resistor R5, and is used for controlling a second analog switch S2 to be turned off at the peak value, cutting off a leakage current channel of a sampling capacitor and reducing voltage loss; the capacitance voltage compensation part 3 comprises a first junction field effect transistor J2, a third resistor R3 and a first capacitor C1 and is used for compensating the voltage loss on the sampling capacitor caused by the charging of the junction capacitor of the second junction field effect transistor J1 of the peak signal sampling holding part; the on and off of the first analog switch S1 and the third analog switch S3 are controlled by a DSP signal control processing part through a DSP chip, the first operational amplifier U1 is a transconductance operational amplifier, and the second operational amplifier U2 is a low-delay high-speed comparator; the non-inverting input end of the second operational amplifier U2 is respectively connected with a first analog switch S1, one end of a first resistor R1 and one end of a second resistor R2, the inverting input end of the second operational amplifier U2 is respectively connected with the inverting input end of the first operational amplifier U1, one end of a sixth resistor R6 and the grid of a first junction field-effect tube J2, the output end of the second operational amplifier U2 is connected with one end of a fifth resistor R5, and the other end of the fifth resistor R5 is connected with the control end of a second analog switch S2; the grid of the first junction type field effect transistor J2 is respectively connected with the inverting input end of the second operational amplifier U2, the inverting input end of the first operational amplifier U1 and one end of the sixth resistor R6, the source and the drain of the first junction type field effect transistor J2 are respectively connected with one end of the third resistor R3, the other end of the third resistor R3 is connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is respectively connected with one end of the second analog switch S2 and the output end of the first operational amplifier U1; the narrow pulse input signal Vin is connected with one end of a first analog switch S1, the other end of the first analog switch S1 is connected with one end of a first resistor R1, one end of a second resistor R2 and the non-inverting input end of a second operational amplifier U2, the other end of the first resistor R1 is connected with the ground, the other end of the second resistor R2 is connected with the non-inverting input end of the first operational amplifier U1, the inverting input end of the first operational amplifier U1 is connected with the inverting input end of a second operational amplifier U2, the gate of a first junction field effect transistor J2 and one end of a sixth resistor R6, the output end of the first operational amplifier U1 is connected with one end of a second analog switch S2 and one end of a first capacitor C1, the other end of the second analog switch S2 is connected with one end of a fourth resistor R4, the other end of the fourth resistor R4 is connected with the gate of a second junction field effect transistor J1, the source of the second junction field effect transistor J1 and the third analog switch S3 are connected with the source field effect transistor J3, One end of a second capacitor C2 is connected with one end of a seventh resistor R7, the other end of the second capacitor C2 is connected with the other end of a third analog switch S3 and the ground, and the other end of the sixth resistor R6 is connected with an emitter of the first triode U3 and one end of an eighth resistor R8 respectively; one end of the seventh resistor R7 is connected to the source and the drain of the second junction field effect transistor J1, one end of the third analog switch S3, and one end of the second capacitor C2, the other end of the seventh resistor R7 is connected to the base of the first triode U3, the collector of the first triode U3 is connected to ground, the emitter of the first triode U3 is connected to one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to the sampled output voltage Vout, and the output voltage Vout is sampled and stored by the ADC module of the DSP chip.
As shown in fig. 2, waveforms of the input voltage signal Vin, the output voltage VCOMP of the second operational amplifier U2, and the output voltage Vout are shown, in which before the input signal Vin reaches a first peak, the output voltage VCOMP of the U2 is at a high level, and after reaching the peak, the output voltage VCOMP changes to a low level, and the output voltage Vout is kept at the first peak, and similarly, after the input signal Vin reaches a second peak, the output voltage Vout is kept at the second peak.
The following is the working principle of the narrow pulse peak sample-and-hold circuit of this embodiment, specifically as follows:
the DSP Signal control processing part 5 outputs a control Signal (Signal input control), controls a first analog switch S1 to be opened, when a narrow pulse input Signal Vin is in a rising stage, the voltage of the in-phase end of a second operational amplifier U2 is larger than the voltage of the anti-phase end, outputs a high level, controls a second analog switch S2 to be opened, simultaneously the voltage of the in-phase end of a first operational amplifier U1 is larger than the voltage of the anti-phase end, a transconductance operational amplifier outputs a forward current, a second junction field effect transistor J1 is conducted, a second capacitor C2 is charged, the voltage of the anti-phase end of the first operational amplifier U1 is smaller than the voltage of the output end, the first junction field effect transistor J2 is cut off, and the junction capacitor of the first capacitor C1 and the first junction field effect transistor J2 is reversely charged to store charges; when the narrow pulse input signal Vin is in a falling stage, the input voltage is less than the output voltage, the voltage of the in-phase terminal of the first operational amplifier U1 is less than the voltage of the out-phase terminal, the output current of the transconductance operational amplifier is reversed, the second jfet J1 is turned off, the voltage of the second capacitor C2 is kept at a peak value, at this time, the second capacitor C2 charges the junction capacitor of the second jfet J1, thereby causing the voltage to fall, and the junction capacitor of the first jfet J2 charges the junction capacitor of the second jfet J1 through the compensation loop, thereby compensating the charge reduced by the second capacitor C2 due to the existence of the junction capacitor of the second jfet J1, reducing the voltage drop of the second capacitor C2, further improving the precision of the sampling peak value, at the same time, the voltage of the in-phase terminal of the second operational amplifier U2 is less than the voltage of the out-phase terminal, outputting a low level, the second analog switch S2 is turned off, thereby cutting off the channel of the reverse current of the second, the leakage current of the second capacitor C2 is reduced, the voltage drop is reduced, the precision of a sampling peak value is further improved, at the moment, the voltage on the second capacitor C2 is output by the following output part 4 to be the output voltage Vout, the output voltage Vout is sampled and stored through an ADC module of a DSP chip of the DSP signal control processing part, the sampling of the peak value is completed, after the sampling is completed, the DSP signal control processing part gives a discharge control signal (clear signal), the third analog switch S3 is conducted, the second capacitor C2 discharges, and preparation is made for next peak value sampling and holding.
In summary, compared with the prior art, the transconductance operational amplifier of the present invention has high bandwidth, large output impedance and large output current, and meets the requirement of fast charging the sampling capacitor; the junction field effect transistor is adopted to replace a Schottky diode, so that the Schottky diode has the characteristics of low junction capacitance and low leakage current, the loss of sampling holding capacitance charge is reduced, and errors are reduced; the high-speed comparator is adopted to control the analog switch to be switched off at the peak value, a leakage current channel of the sampling holding capacitor is cut off, and voltage loss is reduced; the voltage loss on the sampling capacitor caused by the junction capacitor charging of the junction field effect transistor is compensated by adopting the compensation loop, and the sampling precision is improved. Therefore, the utility model discloses the circuit has the characteristics of high-speed high accuracy, is applicable to the occasion of drawing high-speed narrow pulse peak value, has practical application and worth promoting.
The above-mentioned embodiments are only preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, so that all the changes made according to the shape and principle of the present invention should be covered within the protection scope of the present invention.
Claims (4)
1. A narrow pulse peak value sampling and holding circuit comprises a peak value signal sampling and holding part (1), a comparator control part (2), a capacitance voltage compensation part (3), a following output part (4) and a DSP signal control processing part (5), wherein the comparator control part (2), the capacitance voltage compensation part (3), the following output part (4) and the DSP signal control processing part (5) are respectively connected with the peak value signal sampling and holding part (1); the method is characterized in that: the comparator control part (2) comprises a second operational amplifier (U2) and a fifth resistor (R5) and is used for controlling a second analog switch (S2) of the peak signal sample-hold part (1) to be turned off at the peak value, cutting off a leakage current channel of a sampling capacitor of the peak signal sample-hold part (1) and reducing voltage loss, and the capacitor voltage compensation part (3) comprises a first junction field effect transistor (J2), a third resistor (R3) and a first capacitor (C1) and is used for compensating the voltage loss on the sampling capacitor caused by junction capacitor charging of a second junction field effect transistor (J1) of the peak signal sample-hold part (1); the non-inverting input end of the second operational amplifier (U2) is respectively connected with the first analog switch (S1), one end of a first resistor (R1) and one end of a second resistor (R2) of the peak signal sampling and holding part (1), the inverting input end of the second operational amplifier (U2) is respectively connected with the inverting input end of the first operational amplifier (U1), one end of a sixth resistor (R6) and the gate of the first junction field-effect tube (J2) of the peak signal sampling and holding part (1), the output end of the second operational amplifier (U2) is connected with one end of a fifth resistor (R5), and the other end of the fifth resistor (R5) is connected with the control end of the second analog switch (S2) of the peak signal sampling and holding part (1); the grid of the first junction type field effect transistor (J2) is connected with the inverting input end of the second operational amplifier (U2), the inverting input end of the first operational amplifier (U1) and one end of the sixth resistor (R6) respectively, the source and the drain of the first junction type field effect transistor (J2) are connected with one end of the third resistor (R3) respectively, the other end of the third resistor (R3) is connected with one end of the first capacitor (C1), and the other end of the first capacitor (C1) is connected with one end of the second analog switch (S2) of the peak signal sampling and holding part (1) and the output end of the first operational amplifier (U1) respectively.
2. The narrow pulse peak sample-and-hold circuit of claim 1, wherein: the peak signal sampling and holding part (1) samples the peak value of a narrow pulse input signal Vin, and comprises a first analog switch (S1), a first resistor (R1), a second resistor (R2), a first operational amplifier (U1), a second analog switch (S2), a fourth resistor (R4), a second junction field effect transistor (J1), a sixth resistor (R6), a third analog switch (S3) and a second capacitor (C2) serving as a sampling capacitor, wherein the following output part (4) comprises a seventh resistor (R7), a first triode (U3) and an eighth resistor (R8); wherein, the first analog switch (S1) and the third analog switch (S3) are controlled by the DSP chip, the narrow pulse input signal Vin is connected with one end of the first analog switch (S1), the other end of the first analog switch (S1) is respectively connected with one end of a first resistor (R1), one end of a second resistor (R2) and the non-inverting input end of a second operational amplifier (U2), the other end of the first resistor (R1) is connected with the ground, the other end of the second resistor (R2) is connected with the non-inverting input end of a first operational amplifier (U1), the inverting input end of the first operational amplifier (U1) is respectively connected with the inverting input end of the second operational amplifier (U2), the grid of a first junction field effect transistor (J2) and one end of a sixth resistor (R6), and the output end of the first operational amplifier (U1) is respectively connected with one end of a second analog switch (S2), One end of a first capacitor (C1) is connected, the other end of the second analog switch (S2) is connected with one end of a fourth resistor (R4), the other end of the fourth resistor (R4) is connected with the gate of a second junction field effect transistor (J1), the source and the drain of the second junction field effect transistor (J1) are respectively connected with one end of a third analog switch (S3), a second capacitor (C2) and one end of a seventh resistor (R7), the other end of the second capacitor (C2) is connected with the other end of a third analog switch (S3) and ground, and the other end of the sixth resistor (R6) is respectively connected with the emitter of a first triode (U3) and one end of an eighth resistor (R8); one end of the seventh resistor (R7) is connected with the source and the drain of the second junction field effect transistor (J1), one end of the third analog switch (S3) and one end of the second capacitor (C2), the other end of the seventh resistor (R7) is connected with the base of the first triode (U3), the collector of the first triode (U3) is connected with the ground, the emitter of the first triode (U3) is connected with one end of the eighth resistor (R8), the other end of the eighth resistor (R8) is connected with the sampled output voltage Vout, and the output voltage Vout is sampled and stored through an ADC module of the DSP chip.
3. The narrow pulse peak sample-and-hold circuit of claim 1 or 2, wherein: the first operational amplifier (U1) is a transconductance operational amplifier.
4. The narrow pulse peak sample-and-hold circuit of claim 1 or 2, wherein: the second op-amp (U2) is a low-delay high-speed comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921418001.2U CN210431372U (en) | 2019-08-29 | 2019-08-29 | Narrow pulse peak value sampling hold circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921418001.2U CN210431372U (en) | 2019-08-29 | 2019-08-29 | Narrow pulse peak value sampling hold circuit |
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| CN210431372U true CN210431372U (en) | 2020-04-28 |
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| CN201921418001.2U Withdrawn - After Issue CN210431372U (en) | 2019-08-29 | 2019-08-29 | Narrow pulse peak value sampling hold circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023274407A1 (en) * | 2021-07-02 | 2023-01-05 | 陈启星 | Switch operational amplifier |
| CN116250810A (en) * | 2023-05-15 | 2023-06-13 | 广东工业大学 | Signal holding circuit for microscopic imaging system and dual-mode microscopic imaging system |
-
2019
- 2019-08-29 CN CN201921418001.2U patent/CN210431372U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023274407A1 (en) * | 2021-07-02 | 2023-01-05 | 陈启星 | Switch operational amplifier |
| CN116250810A (en) * | 2023-05-15 | 2023-06-13 | 广东工业大学 | Signal holding circuit for microscopic imaging system and dual-mode microscopic imaging system |
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