CN103780231A - Circuit structure for achieving peak value sampling and holding - Google Patents
Circuit structure for achieving peak value sampling and holding Download PDFInfo
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- CN103780231A CN103780231A CN201410046085.7A CN201410046085A CN103780231A CN 103780231 A CN103780231 A CN 103780231A CN 201410046085 A CN201410046085 A CN 201410046085A CN 103780231 A CN103780231 A CN 103780231A
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Abstract
The invention relates to a circuit structure for achieving peak value sampling and holding. The circuit structure comprises a peak value sampling module, a peak value sampling buffering output module, a peak value holding module and a peak value holding buffering output module. The peak value sampling module comprises a sampling signal input buffering unit, a first sampling unit, a sampling switch, a signal reset switch and a second sampling unit, the signal reset switch is used for resetting the voltage input into the first comparison end of the sampling signal input buffering unit from the first sampling unit within each period of reset clock pulses, and the reset clock pulses are the same as sampling clock pulses in frequency. By means of the circuit structure for achieving peak value sampling and holding, wire voltage peak value sampling and holding can be accurately achieved, and input signals can be well reproduced; the real-time zero reset of the signal reset switch and a reset module is adopted, so that the peak value voltage can be accurately obtained, charge accumulation on a sampling capacitor can be avoided, and the circuit structure is simple in structure and convenient to use, and has the wide application scope.
Description
Technical field
The present invention relates to switch power technology field, relate in particular to line voltage signal peak value sampling and keep field, specifically refer to a kind of circuit structure that peak value sampling keeps of realizing.
Background technology
In switch power supply system, the size of AC line voltage can affect the reliability of the normal work of Switching Power Supply, also can affect overall performance simultaneously, works and can make switch power supply system life-span and safety be guaranteed under severe AC line voltage.Be illustrated in figure 1 prior art sampling hold circuit, comprise signal buffering input module 100, signal sampling module 101, peak value maintenance module 102, peak value maintenance Buffer output module 103.
Described signal buffering input module 100 carries out voltage follow to line voltage signal, comprises signal input buffer device 111:
The positive termination AC line voltage input of described signal input buffer device 111, negative terminal connects output, and output connects sampled signal switch 112.
Described signal sampling module 101 sample line voltage signals, comprise sampled signal switch 112, sampling capacitance 113:
Described sampled signal switch 112 1 termination signal input buffer devices 111 are exported, one end ground connection;
Described sampling capacitance 113 positive termination sampled signal switch 112 one end and peak hold switch 114 one end, negativing ending grounding.
Described peak value keeps module to keep sampling capacitance 113 crest voltage obtaining of sample, comprises peak hold switch 114, peak value maintenance electric capacity 115:
Described peak hold switch 114 1 termination sampling capacitance 113 anodes and sampled signal switch 112, one termination peak values keep electric capacity 115 anodes and peak value to keep output buffer 116 anodes;
Described peak value keeps the positive termination peak hold switch 114 of electric capacity 115 and peak value to keep output buffer 116 anodes, negativing ending grounding.
Described peak value keeps Buffer output module 103 to keep electric capacity 115 peak signals to carry out voltage follow to peak value, increases the driving force to load simultaneously, comprises peak value and keeps output buffer 116:
Described peak value keeps the positive termination peak value of output buffer 116 to keep electric capacity 115 anodes and peak hold switch, and negative terminal connects output.
Each point waveform when being illustrated in figure 2 prior art sampling hold circuit and working under AC signal input: 110 is AC line voltage input signal; 112 for controlling the clock signal of sampled signal switch 112; 114 for controlling the clock signal of peak hold switch 114, contrary with sampled signal switch 112 clock signals; 117 is AC line voltage peak output signal.
Prior art sampling hold circuit operation principle: in the time that sampled signal switch 112 control signals are significant level, the sampling capacitance 113 input line voltage signal of sampling, in the time that peak hold switch 114 control signals are significant level, sampling capacitance 113 keeps electric capacity 115 to charge to peak value, retention wire voltage peak signal voltage, peak value keeps output buffer 116 to follow peak value and keeps electric capacity 115 Voltage-outputs simultaneously.
The deficiencies in the prior art: in the time that peak hold switch 114 control signals are significant level, sampling capacitance 113 keeps electric capacity 115 to charge to peak value, voltage on sampling capacitance 113 is declining, until sampling capacitance 113 and peak value keep electric capacity 115 voltages to stop declining when consistent, voltage on now peak value maintenance electric capacity has not been effective line voltage peak voltage, can not accurately obtain AC line voltage peak voltage; Known according to Fig. 2 waveform, the prior art AC alternating current crest voltage of can not effectively sampling, the direct current crest voltage of AC alternating current after full-wave rectification of can only sampling.
Summary of the invention
The object of the invention is to overcome the shortcoming of above-mentioned prior art, provide a kind of can realize more accurate line voltage peak sampling and keep, playback input signal, simple in structure, the circuit structure that peak value sampling keeps of realizing with broader applications scope better.
To achieve these goals, the circuit structure of realizing peak value sampling maintenance of the present invention has following formation:
This realizes the circuit structure that peak value sampling keeps, and its main feature is that described circuit structure comprises:
Peak value sampling module, in order to the crest voltage of each time point of sampled input signal;
Peak value sampling Buffer output module, in order to strengthen the load driving force of sampling and outputting voltage of described peak value sampling module;
Peak value keeps module, keeps in order to the sampled peak voltage of the peak value sampling Buffer output module output to described;
Peak value keeps Buffer output module, keeps the load driving force of the output voltage of module in order to strengthen described peak value;
Described peak value sampling module comprises:
Sampled signal input buffer cell, in order to the magnitude of voltage of the output voltage values of relatively described peak value sampling Buffer output module and described sampled input signal and export comparative result;
The first sampling unit, in order to sample to described sampled input signal and relatively to hold first of sampled signal input buffer cell described the input signal input of sampling;
Sampling switch, samples in order to control the first described sampling unit in the time that sampling clock pulse is significant level, and being connected of the first sampling unit described in disconnecting when sampling clock pulse is inactive level and sampled input signal;
First signal reset switch, in order within each cycle of zero clearing clock pulse to the first described sampling unit be input to described sampled signal input buffer cell first relatively the voltage of end carry out zero clearing, described zero clearing clock pulse is identical with sampling clock pulse frequency;
The second sampling unit, in order to sample during lower than the magnitude of voltage of sampled input signal when the magnitude of voltage of described peak value sampling Buffer output module, the second described sampling unit is connected with the output of described sampled signal input buffer cell.
Preferably, described circuit structure also comprises:
Dump block, in order to a upper periodic peaks threshold voltage of described peak value sampling module output is carried out to zero clearing, described dump block is connected between described peak value sampling module and peak value sampling Buffer output module.
More preferably, the described circuit structure of realizing peak value sampling maintenance, it is characterized in that, described dump block is secondary signal reset switch, and described secondary signal reset switch is in order to carry out zero clearing by a upper periodic peaks threshold voltage of described peak value sampling module output.
Preferably, the first described sampling unit and the second sampling unit are sampling capacitance.
Preferably, described sampled signal input buffer cell is the first operational amplifier, the positive input of the first described operational amplifier is connected with the first described sampling unit, and the reverse input end of the second described operational amplifier keeps the output of Buffer output module to be connected with described peak value.
More preferably, it is the second operational amplifier that described peak value keeps Buffer output module, the positive input of the second described operational amplifier is connected with the output of described peak value sampling module, the reverse input end of the second described operational amplifier is connected with the output of the second described operational amplifier, and the output of the second described operational amplifier also connects the input that described peak value keeps module.
Preferably, described peak value keeps module to comprise that peak hold switch and peak value keep electric capacity, described peak hold switch is in order in the time keeping clock pulse to be significant level, control described peak value keep electric capacity charge to identical with the crest voltage of described peak value sampling module output till, and in the time keeping clock pulse to be inactive level, control described peak value and keep electric capacity to maintain current voltage value, described peak value keeps electric capacity to keep the input of Buffer output module to be connected with described peak value.
Preferably, it is the 3rd operational amplifier that described peak value keeps Buffer output module, the positive input of the 3rd described operational amplifier keeps the output of module to be connected with described peak value, and the reverse input end of the 3rd described operational amplifier is connected with the output of the 3rd described operational amplifier.
Adopt the circuit structure that peak value sampling keeps of realizing in this invention, realize more accurate line voltage peak sampling and kept, playback input signal better, real-time zero clearing by signal reset switch and dump block can accurately obtain crest voltage and avoid the charge accumulated on sampling capacitance, simple in structure, application is convenient, has broader applications scope.
Accompanying drawing explanation
Fig. 1 is the structural representation of sampling hold circuit in prior art.
Fig. 2 is each point waveform schematic diagram when sampling hold circuit is worked in prior art.
Fig. 3 is the electrical block diagram that peak value sampling keeps of realizing of the present invention.
Each point waveform schematic diagram when Fig. 4 is the circuit structure work that realizes peak value sampling maintenance of the present invention.
Embodiment
In order more clearly to describe technology contents of the present invention, conduct further description below in conjunction with specific embodiment.
The present invention relates to a kind of peak value sampling retentive control circuit, intention is to solve the deficiencies in the prior art, and a kind of more accurate line voltage peak sampling hold circuit is provided, and concrete enforcement is described in detail according to Fig. 3.
As shown in Figure 3, circuit of the present invention comprises peak value sampling module 200, dump block 201, peak value sampling Buffer output module 202, peak value maintenance module 203, peak value maintenance Buffer output module 204.
Described peak value sampling module 200 each point voltages of sample line voltage signal, comprise sampling switch 211, sampling capacitance 212, sampled signal reset switch 214, sampled signal input buffer 215, sampling diode 216, sampling capacitance 217:
Described sampling switch 211 is by clock control, sampling capacitance 212 sampled input signals when sampling switch 211 is closed, sampled signal input buffer 215 detects applied signal voltage simultaneously, in the time that applied signal voltage is greater than negative terminal voltage, sampling capacitance 217 is sampled, in the time that applied signal voltage is less than negative terminal voltage, sampling capacitance 217 is not sampled, in the clock cycle, once, sampled signal reset switch 214 clock signals are contrary with sampling switch 211 clock signals for 214 zero clearings of sampled signal reset switch;
Described sampling switch 211 1 termination input signals, termination signal input buffer device 215 anodes;
Described sampling capacitance 212 positive termination signal input buffer device 215 anodes, negativing ending grounding;
Described sampled signal reset switch 214 1 termination signal input buffer device 215 anodes, one end ground connection; Positive termination sampling switch 211 outputs of described sampled signal input buffer 215, negative terminal connects peak value sampling output buffer 220 and exports, output termination sampling diode 216 anodes;
Described sampling diode 216 anodes connect sampled signal input buffer 215 and export, and negative electrode connects sampling capacitance 217 anodes;
The positive termination sampling of described sampling capacitance 217 diode 216 negative electrodes, negativing ending grounding.
Described dump block 201 after peak value keeps Buffer output module 204 to complete output on a periodic sampling signal carry out zero clearing, ready for next periodic sampling, comprise sampled signal reset switch 219:
Described sampled signal reset switch 219 1 termination sampling capacitance 217 anodes and peak value sampling signal output buffer 220 anodes, one end ground connection.
Described peak value sampling signal Buffer output module 202 following sampling electric capacity 217 voltages increase the driving force of peak value sampling signal to load simultaneously, comprise peak value sampling signal output buffer 220:
Described peak value sampling signal output buffer 220 carries out voltage follow to peak value sampling signal, positive termination sampled signal reset switch 219 one end and sampling capacitance 217 anodes, negative terminal connects output, and output connects sampled signal input buffer 215 negative terminals and peak hold switch 222 one end.
Described peak value keeps module 203 to keep peak value sampling signal voltage, comprises peak hold switch 222, peak value maintenance electric capacity 223:
Described peak hold switch 222 1 termination peak value sampling signal output buffer 220 output and sampled signal input buffer 215 negative terminals, one end ground connection;
Described peak value keeps electric capacity 223 1 termination peak hold switch 222 one end and peak value to keep output buffer 225 anodes, one end ground connection.
Described peak value keeps Buffer output module 204 to carry out voltage follow to peak value inhibit signal increases the driving force of peak value inhibit signal to load simultaneously, comprises peak value and keeps output buffer 225:
Described peak value keeps the positive termination peak hold switch 222 of output buffer 225 and peak value to keep electric capacity 223 anodes, and negative terminal connects output.
Each point waveform when being illustrated in figure 4 peak sampling hold circuit of the present invention and working under AC input signal: 210 is AC line voltage input signal; 211 control clock signal for sampling switch 211, and more peak value sampling precision is higher for clock signal frequency; 214 for controlling the clock signal of sampled signal reset switch 214, contrary with 211 clock signals, avoids charge accumulation by the zero clearing effect of sampled signal dump block, can accurately obtain crest voltage; 213 is the sampling capacitance 212 AC line voltage input signal obtaining of sampling; 218 is the sampling capacitance 217 AC line voltage peak signal obtaining of sampling; 221 is the voltage follow signal of AC line voltage peak signal; 219 for completing after the output of peak value inhibit signal, controls the clock signal of sampling reset signal switch 219, and each AC line voltage cycle completes once; 222 for controlling the clock signal of peak hold switch 222; The 224 AC line voltage peak signals for the maintenance of peak value maintenance electric capacity; 226 is AC line voltage peak output signal.
Peak sampling hold circuit operation principle of the present invention: in the time that sampling switch 211 control signals are significant level, the sampling capacitance 212 AC line voltage input signal voltage of sampling, the voltage obtaining and peak value sampling signal output buffer 220 output voltages compare, if high, the sampling capacitance 217 AC line voltage input signal voltage of sampling, if low, sampling capacitance 217 is not sampled, and 220 outputs of sampled signal output buffer are all arrived assurance with the crest voltage precision that the closed-loop system that sampled signal input buffer 215 forms can make sampling obtain.In the time that peak hold switch control signal is significant level, sampled signal output buffer 220 keeps electric capacity 223 to charge until consistent with sampling capacitance 217 voltages to sampling, peak value keeps output buffer 225 to keeping the voltage on electric capacity 223 to carry out voltage follow simultaneously, after completing peak value output, sampling capacitance 217 is carried out to zero clearing action, AC line voltage cycle completes a minor peaks and keeps output and sampling capacitance 217 zero clearings to move, for next periodic sampling ready.
For the change (as the conversion of buffer internal structure) of circuit partial structurtes in the present invention, for replacement or the modification of the combination unsubstantiality of the replacement of components and parts (as sampling diode type comprises triode and the metal-oxide-semiconductor of diode form connection), switching tube, within all falling into protection range of the present invention.
Adopt the circuit structure that peak value sampling keeps of realizing in this invention, realize more accurate line voltage peak sampling and kept, playback input signal better, real-time zero clearing by signal reset switch and dump block can accurately obtain crest voltage and avoid the charge accumulated on sampling capacitance, simple in structure, application is convenient, has broader applications scope.
In this specification, the present invention is described with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from the spirit and scope of the present invention.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (8)
1. realize the circuit structure that peak value sampling keeps, it is characterized in that, described circuit structure comprises:
Peak value sampling module, in order to the crest voltage of each time point of sampled input signal;
Peak value sampling Buffer output module, in order to strengthen the load driving force of sampling and outputting voltage of described peak value sampling module;
Peak value keeps module, keeps in order to the sampled peak voltage of the peak value sampling Buffer output module output to described;
Peak value keeps Buffer output module, keeps the load driving force of the output voltage of module in order to strengthen described peak value;
Described peak value sampling module comprises:
Sampled signal input buffer cell, in order to the magnitude of voltage of the output voltage values of relatively described peak value sampling Buffer output module and described sampled input signal and export comparative result;
The first sampling unit, in order to sample to described sampled input signal and relatively to hold first of sampled signal input buffer cell described the input signal input of sampling;
Sampling switch, samples in order to control the first described sampling unit in the time that sampling clock pulse is significant level, and being connected of the first sampling unit described in disconnecting when sampling clock pulse is inactive level and sampled input signal;
First signal reset switch, in order within each cycle of zero clearing clock pulse to the first described sampling unit be input to described sampled signal input buffer cell first relatively the voltage of end carry out zero clearing, described zero clearing clock pulse is identical with sampling clock pulse frequency;
The second sampling unit, in order to sample during lower than the magnitude of voltage of sampled input signal when the magnitude of voltage of described peak value sampling Buffer output module, the second described sampling unit is connected with the output of described sampled signal input buffer cell.
2. the circuit structure of realizing peak value sampling maintenance according to claim 1, is characterized in that, described circuit structure also comprises:
Dump block, in order to a upper periodic peaks threshold voltage of described peak value sampling module output is carried out to zero clearing, described dump block is connected between described peak value sampling module and peak value sampling Buffer output module.
3. the circuit structure of realizing peak value sampling maintenance according to claim 2, it is characterized in that, the described circuit structure of realizing peak value sampling maintenance, it is characterized in that, described dump block is secondary signal reset switch, and described secondary signal reset switch is in order to carry out zero clearing by a upper periodic peaks threshold voltage of described peak value sampling module output.
4. the circuit structure of realizing peak value sampling maintenance according to claim 1, is characterized in that, described the first sampling unit and the second sampling unit are sampling capacitance.
5. the circuit structure of realizing peak value sampling maintenance according to claim 1, it is characterized in that, described sampled signal input buffer cell is the first operational amplifier, the positive input of the first described operational amplifier is connected with the first described sampling unit, and the reverse input end of the second described operational amplifier keeps the output of Buffer output module to be connected with described peak value.
6. the circuit structure of realizing peak value sampling maintenance according to claim 5, it is characterized in that, it is the second operational amplifier that described peak value keeps Buffer output module, the positive input of the second described operational amplifier is connected with the output of described peak value sampling module, the reverse input end of the second described operational amplifier is connected with the output of the second described operational amplifier, and the output of the second described operational amplifier also connects the input that described peak value keeps module.
7. the circuit structure of realizing peak value sampling maintenance according to claim 1, it is characterized in that, described peak value keeps module to comprise that peak hold switch and peak value keep electric capacity, described peak hold switch is in order in the time keeping clock pulse to be significant level, control described peak value keep electric capacity charge to identical with the crest voltage of described peak value sampling module output till, and in the time keeping clock pulse to be inactive level, controlling described peak value keeps electric capacity to maintain current voltage value, described peak value keeps electric capacity to keep the input of Buffer output module to be connected with described peak value.
8. the circuit structure of realizing peak value sampling maintenance according to claim 1, it is characterized in that, it is the 3rd operational amplifier that described peak value keeps Buffer output module, the positive input of the 3rd described operational amplifier keeps the output of module to be connected with described peak value, and the reverse input end of the 3rd described operational amplifier is connected with the output of the 3rd described operational amplifier.
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| CN201410046085.7A CN103780231B (en) | 2014-02-10 | 2014-02-10 | Realize the circuit structure that peak value sampling is kept |
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| CN201410046085.7A CN103780231B (en) | 2014-02-10 | 2014-02-10 | Realize the circuit structure that peak value sampling is kept |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702095A (en) * | 2015-03-31 | 2015-06-10 | 杭州士兰微电子股份有限公司 | Switching power supply controller and switching power supply comprising switching power supply controller |
| CN105222900A (en) * | 2015-09-15 | 2016-01-06 | 工业和信息化部电子第五研究所 | Infrared focal plane array sensing circuit |
| CN107121587A (en) * | 2017-06-26 | 2017-09-01 | 佛山科学技术学院 | Peak value and excessively peak moment tracing detection circuit |
| WO2020000993A1 (en) * | 2018-06-24 | 2020-01-02 | 陈启星 | Power switch-type sampling and holding device |
| CN110806503A (en) * | 2018-08-04 | 2020-02-18 | 张坚 | Novel peak value detection circuit |
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| CN101615432A (en) * | 2009-07-29 | 2009-12-30 | 杭州士兰微电子股份有限公司 | Peak sampling hold circuit, peak sampling hold method and application |
| CN102364848A (en) * | 2011-02-01 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Primary side-controlled constant current switch power supply controller and primary side-controlled constant current switch power supply control method |
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| JPS5425660A (en) * | 1977-07-29 | 1979-02-26 | Toshiba Corp | Peak value detection circuit |
| US4992674A (en) * | 1988-05-24 | 1991-02-12 | Dallas Semiconductor Corporation | Controlled slew peak detector |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702095A (en) * | 2015-03-31 | 2015-06-10 | 杭州士兰微电子股份有限公司 | Switching power supply controller and switching power supply comprising switching power supply controller |
| CN105222900A (en) * | 2015-09-15 | 2016-01-06 | 工业和信息化部电子第五研究所 | Infrared focal plane array sensing circuit |
| CN105222900B (en) * | 2015-09-15 | 2018-09-28 | 工业和信息化部电子第五研究所 | Infrared focal plane array reading circuit |
| CN107121587A (en) * | 2017-06-26 | 2017-09-01 | 佛山科学技术学院 | Peak value and excessively peak moment tracing detection circuit |
| CN107121587B (en) * | 2017-06-26 | 2023-02-28 | 佛山科学技术学院 | Peak value and over-peak time tracking detection circuit |
| WO2020000993A1 (en) * | 2018-06-24 | 2020-01-02 | 陈启星 | Power switch-type sampling and holding device |
| CN110806503A (en) * | 2018-08-04 | 2020-02-18 | 张坚 | Novel peak value detection circuit |
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