CN110806503A

CN110806503A - Novel peak value detection circuit

Info

Publication number: CN110806503A
Application number: CN201810880948.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Individual
Current assignee: Shenzhen Yuntong Technology Co ltd
Priority date: 2018-08-04
Filing date: 2018-08-04
Publication date: 2020-02-18

Abstract

In the field of integrated circuits, the peak detection circuit is available because the peak value of the input signal is changing, and needs to be refreshed once to ensure that the output is the current peak value of the input signal. However, during the refresh period, the output signal is affected by the refresh signal, and the output signal is not the peak value of the current signal. Aiming at the problems of the traditional peak value detection circuit, the invention provides a novel peak value detection circuit which can enable the output of the circuit to be the peak value of an input signal all the time without being influenced by a refreshing signal.

Description

Novel peak value detection circuit

Technical Field

This patent designs a neotype peak detection circuit, and its output signal does not receive the influence of refresh signal among the traditional peak detection circuit.

Background

In the existing peak detection circuit, because the peak value of the input signal is changing, a refresh is needed to ensure that the output is the current peak value of the input signal at any time. However, during the period of refresh, the output signal is affected by the refresh signal, and at this time, the output signal is not the peak value of the current signal, and there is a problem of signal distortion and even detection error.

Disclosure of Invention

Purpose and bright spot of the invention:

aiming at the problems of the traditional peak value detection circuit, the invention provides a novel peak value detection circuit which can enable the output of the circuit to be the peak value of an input signal all the time without being influenced by a refreshing signal.

Description of technical solutions (product classes) (emphasis):

the scheme is based on the original peak detection circuit, and a sampling hold circuit and a logic control circuit are added.

The peak detection circuit is a traditional peak detection circuit, and the circuit mainly comprises peak detection and refreshing.

The sample-and-hold circuit is provided as long as it samples and holds the peak value detected by the peak detection circuit.

The logic control circuit is logic that controls the peak detection circuit and the sample-and-hold circuit.

The working principle is as follows:

conventional peak detection circuits as shown in fig. 1, the input signal vin (t) is kept stored on C1 after passing through OP1 and D1, and output as V _ peak. N1 is an NMOS, and the refresh signal V _ refresh directly controls the NMOS. At refresh, V _ fresh is high and the charge on C1 is drained to 0 by N1, so the value of V _ peak is also 0, rather than the peak value of vin (t) of the input signal. This is a disadvantage of the conventional peak detection circuit. As shown in FIG. 2 below;

on the basis, the invention adds a sample hold circuit and a logic control circuit, as shown in the following figure 3; the control logic and sample and hold circuit will sample out the peak and hold it before the refresh circuit is operated, and the resulting peak voltage is as shown in figure 4 below

Description of the technical solutions (methods) (emphasis)

Conventional peak detection circuits as shown in fig. 1, the input signal vin (t) is kept stored on C1 after passing through OP1 and D1, and output as V _ peak. N1 is an NMOS, and the refresh signal V _ refresh directly controls the NMOS. In many applications, the peak value of vin (t) is not constant and varies from cycle to cycle, as shown in fig. 5. A refresh circuit is thus required, which refreshes the peak voltage held at C1 once after a certain time interval, the sample-and-hold circuit, which is shown in dashed lines in fig. 6, mainly comprises OP2, SW1 and C2. S1 is controlled by control signal V _ sample. The negative terminal and the output terminal of the OP2 are connected to form a buffer with unity gain. When V _ sample is high, S1 is closed and the output of capacitor C2 and OP2 are connected directly. The value of V _ peak _ draft is sampled onto the capacitor C2, V _ peak = V _ peak _ draft when V _ sample is low, S2 is turned off and the value of V _ peak is held on the capacitor C2, which remains unchanged regardless of whether V _ peak _ draft changes. The function of the logic control circuit is to generate two output signals V _ Fresh and V _ sample according to the input signal Fresh, as shown in fig. 7, the two generated logic control signals are as shown in fig. 8, the pulse of the V _ sample signal must first be equal to the V _ Fresh signal, and a certain dead time must exist between the V _ sample signal and the V _ Fresh signal. This is to ensure that the V _ peak _ draft must be sample-and-hold prior to a refresh.

Technical effect of this patent

The output of the conventional peak detection circuit is shown in fig. 9, and the output of the present embodiment is shown in fig. 4

Attached drawings (emphasis)

FIG. 1 shows a schematic view of a

FIG. 3

FIG. 6

Drawings

FIG. 1 is a conventional peak detection circuit diagram

FIG. 2 is an output diagram of a conventional peak detection circuit

FIG. 3 is a sample and hold circuit and logic control circuit diagram incorporating the present invention

FIG. 4 is a graph of the output of the peak detection circuit of the present invention

FIG. 5 is a graph of the peak value of vin (t)

FIG. 6 is a sample and hold circuit diagram

FIG. 7 is a graph of the output signals V-fresh and V-sample

FIG. 8 is a sample-and-hold diagram of V-peak-draft that must be sampled before a refresh

Fig. 9 is a graph comparing outputs of the conventional peak detection circuit.

Claims

1. A novel peak value detection circuit is characterized in that a sampling hold circuit and a logic control circuit are added in a traditional peak value detection circuit, the logic control circuit and the sampling hold circuit can sample and hold a peak value before a refreshing circuit works, wherein the sampling hold circuit is mainly formed by connecting an OP2 operational amplifier and a switch S1 in series and connecting a capacitor C2 in parallel, and controls S2 to refresh and hold signals through a Vsample signal of the logic control circuit; the logic control circuit generates two output signals V _ Fresh and V _ sample according to an input signal Freeh, wherein the pulse of the V _ sample signal must be firstly equal to the V _ Fresh signal, and a certain dead time must be reserved between the V _ sample signal and the V _ Fresh signal, so that the V _ peak _ draft must be sampled and held before refreshing, and the circuit characteristic that the output of the V _ peak _ draft is always the peak value of the input signal and is not influenced by the refreshing signal is realized.