CN103780231B - Realize the circuit structure that peak value sampling is kept - Google Patents
Realize the circuit structure that peak value sampling is kept Download PDFInfo
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- CN103780231B CN103780231B CN201410046085.7A CN201410046085A CN103780231B CN 103780231 B CN103780231 B CN 103780231B CN 201410046085 A CN201410046085 A CN 201410046085A CN 103780231 B CN103780231 B CN 103780231B
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Abstract
The circuit structure that peak value sampling is kept is realized the present invention relates to a kind of, including peak value sampling module, peak value sampling Buffer output module, peak value hold module and peak holding Buffer output module, described peak value sampling module includes：Sampled signal input buffer cell, the first sampling unit, sampling switch, signal reset switch and the second sampling unit, the first voltage for comparing end that signal reset switch is used to be input to the first sampling unit within each cycle for resetting clock pulses sampled signal input buffer cell is zeroed out, and resets clock pulses identical with sample clock pulse frequency.The circuit structure that peak value sampling is kept is realized using this kind, more accurate line voltage peak value sampling and holding can be realized, preferably reproduce input signal, crest voltage can accurately be obtained by the real-time clearing of signal reset switch and dump block and charge accumulated on sampling capacitance is avoided, it is simple in construction, using convenient, with broader applications scope.
Description
Technical field
The present invention relates to switch power technology field, more particularly to line voltage signal peak sampling holding field, it is specifically
Refer to a kind of circuit structure for realizing peak value sampling holding.
Background technology
In switch power supply system, the size of AC line voltages can influence the reliability of Switching Power Supply normal work, while
Overall performance can be influenceed, being worked under severe AC line voltages can make switch power supply system life-span and safety not to be guaranteed.
It is prior art sampling hold circuit as shown in Figure 1, includes signal buffering input module 100, signal sampling module 101, peak value
Keep module 102, peak holding Buffer output module 103.
The signal buffering input module 100 carries out voltage follow to line voltage signal, includes signal input buffer device
111：
The signal input buffer device 111 just termination AC line voltages input, negative terminal connects output, and output connects sampled signal switch
112。
The sampling of the signal sampling module 101 line voltage signal, includes sampled signal switch 112, sampling capacitance 113：
The sampled signal switch 112 1 terminates signal input buffer device 111 and exported, one end ground connection；
The sampling capacitance 113 just termination sampled signal switchs 112 one end and the one end of peak hold switch 114, and negative terminal connects
Ground.
The crest voltage that the peak value hold module is obtained to the sampling of sampling capacitance 113 is kept, and includes peak holding
Switch 114, peak holding electric capacity 115：
The termination anode of sampling capacitance 113 of peak hold switch 114 1 and sampled signal switch 112, a termination peak value
The anode of holding capacitor 115 and the anode of peak holding output buffer 116；
The peak holding electric capacity 115 just termination peak hold switch 114 and the anode of peak holding output buffer 116,
Negativing ending grounding.
The peak holding Buffer output module 103 carries out voltage follow to the peak signal of peak holding electric capacity 115, simultaneously
Increase the driving force to load, include peak holding output buffer 116：
The peak holding the output buffer 116 just anode of termination peak holding electric capacity 115 and peak hold switch, negative terminal
Connect output.
It is illustrated in figure 2 each point waveform when prior art sampling hold circuit works under the input of AC signals：110 be AC
Line voltage input signal；112 switch 112 clock signal for control sampled signal；114 be control peak hold switch 114
Clock signal, switchs 112 clock signals opposite with sampled signal；117 be AC line voltage peak output signals.
Prior art sampling hold circuit operation principle：When it is significant level that sampled signal, which switchs 112 control signals, adopt
The sampling input line voltage signal of sample electric capacity 113, when the control signal of peak hold switch 114 is significant level, sampling capacitance 113
Peak holding electric capacity 115 is charged, line voltage peak signal voltage is kept, while peak holding output buffer 116 follows peak
It is worth the voltage output of holding capacitor 115.
The deficiencies in the prior art：When the control signal of peak hold switch 114 is significant level, sampling capacitance 113 is to peak
Value holding capacitor 115 charges, and the voltage on sampling capacitance 113 is declining, until sampling capacitance 113 and peak holding electric capacity 115
Stop declining when voltage is consistent, now the voltage on peak holding electric capacity has not been effective line voltage crest voltage, it is impossible to
It is accurately obtained AC line voltage crest voltages；It can be seen from Fig. 2 waveforms, prior art can not effectively sample AC alternating currents peak value electricity
Pressure, can only sample direct current crest voltage of the AC alternating currents after full-wave rectification.
The content of the invention
The purpose of the present invention is that the shortcoming for overcoming above-mentioned prior art can realize more accurate line there is provided one kind
Voltage peak sample and keep, preferably reproduce input signal, it is simple in construction, realize that peak value is adopted with broader applications scope
The circuit structure that sample is kept.
To achieve these goals, the circuit structure for realizing peak value sampling holding of the invention has following composition：
This realizes the circuit structure that peak value sampling is kept, and it is mainly characterized by, and described circuit structure includes：
Peak value sampling module, the crest voltage to the Each point in time of sampled input signal；
Peak value sampling Buffer output module, drives to strengthen the load of sampling and outputting voltage of described peak value sampling module
Kinetic force；
Peak value hold module, is protected to the sampled peak voltage to described peak value sampling Buffer output module output
Hold；
Peak holding Buffer output module, the load driving energy of the output voltage to strengthen described peak value hold module
Power；
Described peak value sampling module includes：
Sampled signal input buffer cell, to the peak value sampling Buffer output module described in comparison output voltage values and
The magnitude of voltage of described sampled input signal simultaneously exports comparative result；
First sampling unit, to be sampled to described sampled input signal and the input signal of sampling is inputted into institute
The first of the sampled signal input buffer cell stated compares end；
Sampling switch, is adopted to the first sampling unit described in the control when sample clock pulse is significant level
Sample, and the connection of the first sampling unit and sampled input signal when sample clock pulse is inactive level described in disconnection；
First signal reset switch, to defeated to described first sampling unit within each cycle for resetting clock pulses
The first voltage for comparing end entered to described sampled signal input buffer cell is zeroed out, described clearing clock pulses with
Sample clock pulse frequency is identical；
Second sampling unit, is less than sampled input signal to the magnitude of voltage when described peak value sampling Buffer output module
Magnitude of voltage when sampled, the second described sampling unit is connected with the output end of described sampled signal input buffer cell
Connect.
It is preferred that described circuit structure also includes：
Dump block, it is described a upper cycle peak voltage for described peak value sampling module output to be zeroed out
Dump block be connected between described peak value sampling module and peak value sampling Buffer output module.
More preferably, it is described to realize the circuit structure that peak value sampling is kept, it is characterised in that described dump block is the
Binary signal reset switch, described secondary signal reset switch is to by a upper periodic peaks for described peak value sampling module output
Threshold voltage is zeroed out.
It is preferred that described the first sampling unit and the second sampling unit is sampling capacitance.
It is preferred that described sampled signal input buffer cell is the first operational amplifier, the first described operation amplifier
The positive input of device is connected with the first described sampling unit, the reverse input end of described the second operational amplifier and institute
The output end for the peak holding Buffer output module stated is connected.
More preferably, described peak holding Buffer output module is the second operational amplifier, the second described operation amplifier
The positive input of device is connected with the output end of described peak value sampling module, described the second operational amplifier it is reverse defeated
Enter end with the output end of the second described operational amplifier to be connected, the output end of the second described operational amplifier is also connected with institute
The input for the peak value hold module stated.
It is preferred that described peak value hold module includes peak hold switch and peak holding electric capacity, described peak value is protected
Switch is held to when it is significant level to keep clock pulses, the described peak holding electric capacity of control charged to it is described
Untill the crest voltage of peak value sampling module output is identical, and the described peak value of control when it is inactive level to keep clock pulses
Holding capacitor maintains current voltage value, described peak holding electric capacity and the input of described peak holding Buffer output module
It is connected.
It is preferred that described peak holding Buffer output module is the 3rd operational amplifier, the 3rd described operation amplifier
The positive input of device is connected with the output end of described peak value hold module, described the 3rd operational amplifier it is reverse defeated
Enter end with the output end of the 3rd described operational amplifier to be connected.
The circuit structure that peak value sampling is kept of realizing in the invention is employed, more accurate line voltage peak value is realized
Sampling and holding, preferably reproduce input signal, can be accurate by the real-time clearing of signal reset switch and dump block
To crest voltage and charge accumulated on sampling capacitance is avoided, it is simple in construction, using convenient, with broader applications scope.
Brief description of the drawings
Fig. 1 is the structural representation of sampling hold circuit in the prior art.
Each point waveform diagram when Fig. 2 works for sampling hold circuit in the prior art.
Fig. 3 is the electrical block diagram that peak value sampling is kept of realizing of the invention.
Each point waveform diagram when Fig. 4 works for the circuit structure for realizing peak value sampling holding of the present invention.
Embodiment
In order to more clearly describe the technology contents of the present invention, carried out with reference to specific embodiment further
Description.
Control circuit is kept the present invention relates to a kind of peak value sampling, it is intended that be that there is provided one for solution the deficiencies in the prior art
More accurate line voltage peak sampling hold circuit is planted, specific implementation is described in detail according to Fig. 3.
As shown in figure 3, circuit of the present invention includes peak value sampling module 200, dump block 201, peak value sampling Buffer output
Module 202, peak value hold module 203, peak holding Buffer output module 204.
Each voltage of the sampling line voltage signal of peak value sampling module 200, includes sampling switch 211, sampling capacitance
212nd, sampled signal reset switch 214, sampled signal input buffer 215, sampling diode 216, sampling capacitance 217：
The sampling switch 211 is by clock control, the sampled input signal of sampling capacitance 212 when sampling switch 211 is closed, together
When sampled signal input buffer 215 detect applied signal voltage, when applied signal voltage is more than negative terminal voltage, sampling capacitance
217 are sampled, and when applied signal voltage is less than negative terminal voltage, sampling capacitance 217 is without sampling, in a clock cycle
Sampled signal reset switch 214 is reset once, the clock signal of sampled signal reset switch 214 and the clock signal of sampling switch 211
Conversely；
The sampling switch 211 1 terminates input signal, the anode of a termination signal input buffer device 215；
The sampling capacitance 212 just anode of termination signal input buffer device 215, negativing ending grounding；
The anode of the termination signal input buffer of sampled signal reset switch 214 1 device 215, one end ground connection；The sampling
The just termination output end of sampling switch 211 of signal input buffer device 215, negative terminal connects peak value sampling output buffer 220 and exported, exports
The termination sampling anode of diode 216；
The sampling anode of diode 216 connects sampled signal input buffer 215 and exported, and negative electrode is connecing sampling capacitance 217 just
End；
The sampling capacitance 217 just the termination sampling negative electrode of diode 216, negativing ending grounding.
The dump block 201 is after peak holding Buffer output module 204 completes output to upper periodic sampling signal
It is zeroed out, is that next periodic sampling is ready, includes sampled signal reset switch 219：
The termination anode of sampling capacitance 217 of sampled signal reset switch 219 1 and peak value sampling signal output buffer
220 anodes, one end ground connection.
The voltage of 202 following sampling electric capacity of the peak value sampling signal Buffer output module 217, while increasing peak value sampling letter
Number to the driving force of load, peak value sampling signal output buffer 220 is included：
The peak value sampling signal output buffer 220 carries out voltage follow, positive termination sampling letter to peak value sampling signal
Number one end of reset switch 219 and the anode of sampling capacitance 217, negative terminal connect output, and output connects the negative terminal of sampled signal input buffer 215
With the one end of peak hold switch 222.
The peak value hold module 203 is kept to peak value sampling signal voltage, includes peak hold switch 222, peak
It is worth holding capacitor 223：
The termination peak value sampling of peak hold switch 222 1 signal output buffer 220 is exported and sampled signal input
The negative terminal of buffer 215, one end ground connection；
Described termination one end of peak hold switch 222 of peak holding electric capacity 223 1 and peak holding output buffer 225 are just
End, one end ground connection.
The peak holding Buffer output module 204 carries out voltage follow to peak hold signal increases peak holding simultaneously
Signal includes peak holding output buffer 225 to the driving force of load：
The peak holding output buffer 225 just termination peak hold switch 222 and the anode of peak holding electric capacity 223,
Negative terminal connects output.
It is illustrated in figure 4 each point waveform when peak sampling hold circuit of the present invention works under AC input signal：210 are
AC line voltage input signals；211 be that sampling switch 211 controls clock signal, and clock signal frequency more peak value sampling precision is more
It is high；214 be the clock signal of control sampled signal reset switch 214, with 211 clock signals on the contrary, being reset by sampled signal
The clearing effect of module avoids charge accumulation, can accurately obtain crest voltage；213 be the AC that the sampling of sampling capacitance 212 is obtained
Line voltage input signal；218 be the AC line voltage peak signals that the sampling of sampling capacitance 217 is obtained；221 be that AC line voltages peak value is believed
Number voltage follow signal；219 is complete after peak hold signal output, the clock letter of control sampling reset signal switch 219
Number, each AC line voltages cycle completes once；222 be the clock signal of control peak hold switch 222；224 be peak holding
The AC line voltage peak signals that electric capacity is kept；226 be AC line voltage peak output signals.
The peak sampling hold circuit operation principle of the present invention：When the control signal of sampling switch 211 is significant level, adopt
The sampling AC line voltage applied signal voltages of sample electric capacity 212, obtained voltage exports electricity with peak value sampling signal output buffer 220
Pressure is compared, if high, the sampling AC line voltage applied signal voltages of sampling capacitance 217, if low, sampling capacitance 217 does not enter
Row sampling, the closed-loop system that the output of sampled signal output buffer 220 is constituted with sampled signal input buffer 215 can make sampling
Obtained crest voltage precision all arrives guarantee.When peak hold switch control signal is significant level, sampled signal output is slow
Rush 220 pairs of sampling holding capacitors 223 of device to charge untill consistent with the voltage of sampling capacitance 217, while peak holding output is slow
Rush device 225 and voltage follow is carried out to the voltage in holding capacitor 223, sampling capacitance 217 is zeroed out after completing peak value output
Action, an AC line voltage cycle completes a peak holding output and the clearing of sampling capacitance 217 action, is next periodic sampling
It is ready.
For the change of circuit partial structurtes in the present invention（Such as the conversion of buffer internal structure）, replacing for component
Change（Diode type of such as sampling includes the triode and metal-oxide-semiconductor of diode connection）, switching tube combination unsubstantiality
Replace or change, each fall within the scope of the present invention.
The circuit structure that peak value sampling is kept of realizing in the invention is employed, more accurate line voltage peak value is realized
Sampling and holding, preferably reproduce input signal, can be accurate by the real-time clearing of signal reset switch and dump block
To crest voltage and charge accumulated on sampling capacitance is avoided, it is simple in construction, using convenient, with broader applications scope.
In this description, the present invention is described with reference to its specific embodiment.But it is clear that can still make
Various modifications and alterations are without departing from the spirit and scope of the present invention.Therefore, specification and drawings are considered as illustrative
And it is nonrestrictive.
Claims (6)
1. a kind of realize the circuit structure that peak value sampling is kept, it is characterised in that described circuit structure includes：
Peak value sampling module, the crest voltage to the Each point in time of sampled input signal；
Peak value sampling Buffer output module, the load driving energy of the sampling and outputting voltage to strengthen described peak value sampling module
Power；
Peak value hold module, keeps to the sampled peak voltage to described peak value sampling Buffer output module output；
Peak holding Buffer output module, the load driving force of the output voltage to strengthen described peak value hold module；
Described peak value sampling module includes：
Sampled signal input buffer cell, to the output voltage values of the peak value sampling Buffer output module described in comparison and described
Sampled input signal magnitude of voltage and export comparative result；
First sampling unit, to be sampled and inputted the input signal of sampling described to described sampled input signal
The first of sampled signal input buffer cell compares end；
Sampling switch, is sampled to the first sampling unit described in the control when sample clock pulse is significant level, and
The connection of described the first sampling unit and sampled input signal is disconnected when sample clock pulse is inactive level；
First signal reset switch, to be input within each cycle for resetting clock pulses to the first described sampling unit
First voltage for comparing end of described sampled signal input buffer cell is zeroed out, described clearing clock pulses and sampling
Clock pulse frequency is identical；
The first signal reset switch one terminates sampled signal input buffer cell anode, one end ground connection；The sampled signal
Input buffer cell is just terminating sampling switch output end, and negative terminal connects the output of peak value sampling Buffer output module, output termination sampling
Diode anode；
The sampling diode anode connects the output of sampled signal input buffer cell, and negative electrode connects the first sampling unit anode；
Second sampling unit, the electricity to be less than sampled input signal when the magnitude of voltage of described peak value sampling Buffer output module
Sampled during pressure value, the second described sampling unit is connected with the output end of described sampled signal input buffer cell；
Dump block, a upper cycle peak voltage for described peak value sampling module output to be zeroed out, described is clear
Zero module is connected between described peak value sampling module and peak value sampling Buffer output module；
When the sampling switch control signal is significant level, sampling capacitance sampling AC line voltage applied signal voltages are obtained
Voltage is compared with peak value sampling Buffer output module output voltage, if high, sampling capacitance sampling AC line voltage input letters
Number voltage, if low, sampling capacitance is without sampling, and peak value sampling Buffer output module and peak value sampling module composition are closed
The crest voltage precision that loop system obtains sampling is guaranteed；
Described peak value hold module includes peak hold switch and peak holding electric capacity, and described peak hold switch is to work as
When keeping clock pulses for significant level, the described peak holding electric capacity of control is charged to and described peak value sampling module
Untill the crest voltage of output is identical, and the described peak holding electric capacity of control is maintained when it is inactive level to keep clock pulses
Current voltage value, described peak holding electric capacity is connected with the input of described peak holding Buffer output module.
2. according to claim 1 realize the circuit structure that peak value sampling is kept, it is characterised in that described realizes peak value
The circuit structure that sampling is kept, it is characterised in that described dump block is secondary signal reset switch, described secondary signal
Reset switch is a upper cycle peak voltage for described peak value sampling module output to be zeroed out.
3. according to claim 1 realize the circuit structure that peak value sampling is kept, it is characterised in that the first described sampling
Unit and the second sampling unit are sampling capacitance.
4. according to claim 1 realize the circuit structure that peak value sampling is kept, it is characterised in that described sampled signal
Input buffer cell is the first operational amplifier, and the positive input of the first described operational amplifier is sampled with described first
Unit is connected, and the reverse input end of the second operational amplifier is connected with the output end of described peak holding Buffer output module
Connect.
5. according to claim 4 realize the circuit structure that peak value sampling is kept, it is characterised in that described peak holding
Buffer output module is the second operational amplifier, the positive input of described the second operational amplifier and described peak value sampling
The output end of module is connected, and the reverse input end of described the second operational amplifier is defeated with the second described operational amplifier
Go out end to be connected, the output end of the second described operational amplifier is also connected with the input of described peak value hold module.
6. according to claim 1 realize the circuit structure that peak value sampling is kept, it is characterised in that described peak holding
Buffer output module is the 3rd operational amplifier, the positive input of described the 3rd operational amplifier and described peak holding
The output end of module is connected, and the reverse input end of described the 3rd operational amplifier is defeated with the 3rd described operational amplifier
Go out end to be connected.
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| CN201410046085.7A CN103780231B (en) | 2014-02-10 | 2014-02-10 | Realize the circuit structure that peak value sampling is kept |
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| CN201410046085.7A CN103780231B (en) | 2014-02-10 | 2014-02-10 | Realize the circuit structure that peak value sampling is kept |
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| CN103780231B true CN103780231B (en) | 2017-10-20 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702095B (en) * | 2015-03-31 | 2017-05-24 | 杭州士兰微电子股份有限公司 | Switching power supply controller and switching power supply comprising switching power supply controller |
| CN105222900B (en) * | 2015-09-15 | 2018-09-28 | 工业和信息化部电子第五研究所 | Infrared focal plane array reading circuit |
| CN107121587B (en) * | 2017-06-26 | 2023-02-28 | 佛山科学技术学院 | Peak value and over-peak time tracking detection circuit |
| CN110635770A (en) * | 2018-06-24 | 2019-12-31 | 陈启星 | Sampling holder for controlling on-off of input amplifier signal loop by power switch |
| CN110806503A (en) * | 2018-08-04 | 2020-02-18 | 张坚 | Novel peak value detection circuit |
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|---|---|---|---|---|
| US4992674A (en) * | 1988-05-24 | 1991-02-12 | Dallas Semiconductor Corporation | Controlled slew peak detector |
| CN101615432A (en) * | 2009-07-29 | 2009-12-30 | 杭州士兰微电子股份有限公司 | Peak sampling hold circuit, peak sampling hold method and application |
| CN102364848A (en) * | 2011-02-01 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Primary side-controlled constant current switch power supply controller and primary side-controlled constant current switch power supply control method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5425660A (en) * | 1977-07-29 | 1979-02-26 | Toshiba Corp | Peak value detection circuit |
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2014
- 2014-02-10 CN CN201410046085.7A patent/CN103780231B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4992674A (en) * | 1988-05-24 | 1991-02-12 | Dallas Semiconductor Corporation | Controlled slew peak detector |
| CN101615432A (en) * | 2009-07-29 | 2009-12-30 | 杭州士兰微电子股份有限公司 | Peak sampling hold circuit, peak sampling hold method and application |
| CN102364848A (en) * | 2011-02-01 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Primary side-controlled constant current switch power supply controller and primary side-controlled constant current switch power supply control method |
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