CN203554419U - Random pulse triggering peak sampling and keeping circuit - Google Patents
Random pulse triggering peak sampling and keeping circuit Download PDFInfo
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- CN203554419U CN203554419U CN201320742598.2U CN201320742598U CN203554419U CN 203554419 U CN203554419 U CN 203554419U CN 201320742598 U CN201320742598 U CN 201320742598U CN 203554419 U CN203554419 U CN 203554419U
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Abstract
The utility model discloses a random pulse triggering peak sampling and keeping circuit, which comprises a pulse triggering unit and a peak keeping unit. Through the pulse triggering unit and the peak keeping unit, output signals of the pulse triggering unit are used for controlling a switch SPST on the peak keeping unit, such that the peak keeping unit can be triggered timely. According to the random pulse triggering peak sampling and keeping circuit, the purposes that sampling and discharging are timely and next-time adoption is facilitated.
Description
Technical field
The utility model relates to electricity field, particularly, relates to a kind of random pulses and triggers peak sampling hold circuit.
Background technology
At present, sampling hold circuit extensively uses in sample circuit, but existing sampling hold circuit exists the current discharge that peak holding circuit partly stores to have delay, and the peak holding circuit making can not be in time for peak value maintenance be next time ready.
Utility model content
The purpose of this utility model is, for the problems referred to above, proposes a kind of random pulses and triggers peak sampling hold circuit, to realize the sampling hold circuit advantage of discharging in time.
For achieving the above object, the technical solution adopted in the utility model is:
Random pulses trigger a peak sampling hold circuit, comprise pulse-triggered unit and peak value holding unit,
Described pulse-triggered unit comprises transport and placing device A1, transport and placing device A2, field effect transistor Q1, field effect transistor Q2 and switch S PST, series diode D1 and resistance R 1 successively between the inverting input of the inverting input of described transport and placing device A1 and transport and placing device A2, the anode of described diode D1 is connected with the inverting input of transport and placing device A1, the negative electrode of this diode D1 is connected with resistance R 1, the two ends shunt capacitance C3 of described diode D1, the two ends shunt capacitance C4 of described resistance R 1, described tandem tap SPST and the diode D2 successively put between the output of device A1 and the source electrode of field effect transistor Q1, the anode of described diode D2 is connected with switch S PST, the negative electrode of diode D2 is connected with the source electrode of field effect transistor Q1, and the anode of diode D2 is connected with the grid of field effect transistor Q1, series resistance R2 between the in-phase input end of described field effect transistor Q1 drain electrode and transport and placing device A2, the source electrode of this field effect transistor Q1 and capacitor C 1 series connection ground connection, the drain electrode of this field effect transistor Q1 and capacitor C 2 series connection ground connection, and the drain electrode of this field effect transistor Q1 is connected with the drain electrode of field effect transistor Q2, the source ground of field effect transistor Q2,
Described pulse-triggered unit comprises differential circuit and comparison circuit, described differential circuit comprises capacitor C 5 and transport and placing device A3, the inverting input series resistance R3 of this transport and placing device A3 and capacitor C 5, and series resistance R6 between the inverting input of this transport and placing device A3 and transport and placing device A3 output, the in-phase input end of this transport and placing device A3 and resistance R 4 series connection ground connection, described comparison circuit comprises transport and placing device A4 and resistance R 5, the inverting input of this transport and placing device A4 is connected with the output of described transport and placing device A3, the output of this transport and placing device A4 is connected with resistance R 5, one end of described resistance R 5 and transition twin zener dioder series connection ground connection, described resistance R 5 is connected with above-mentioned switch S PST with the node between transition twin zener dioder.
Further, described transport and placing device A1 and transport and placing device A2 adopt LF356 operational amplifier, and described transport and placing device A3 adopts LM338 operational amplifier, and described transport and placing device A4 adopts LM339A operational amplifier.
Further, the capacitance size of described capacitor C 3 and capacitor C 4 is 560PF.
Further, the capacitance size of described capacitor C 5 is 50nF.
Further, the grid of field effect transistor Q2 connects single-chip microcomputer.
The technical solution of the utility model has following beneficial effect:
The utility model, by pulse-triggered unit and peak value holding unit, is used the output signal of pulse-triggered unit to control the switch S PST on peak value holding unit, and peak value holding unit is triggered timely.Sampling and electric discharge are timely, the convenient object next time adopting.
Accompanying drawing explanation
Fig. 1 is the peak value holding unit electrical circuit diagram described in the utility model embodiment;
Fig. 2 is the pulse-triggered unit electrical circuit diagram described in the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing, preferred embodiment of the present utility model is described, should be appreciated that preferred embodiment described herein is only for description and interpretation the utility model, and be not used in restriction the utility model.
As shown in Figure 1 and Figure 2, a kind of random pulses trigger peak sampling hold circuit, comprise pulse-triggered unit and peak value holding unit,
Pulse-triggered unit comprises transport and placing device A1, transport and placing device A2, field effect transistor Q1, field effect transistor Q2 and switch S PST, series diode D1 and resistance R 1 successively between the inverting input of the inverting input of transport and placing device A1 and transport and placing device A2, the anode of diode D1 is connected with the inverting input of transport and placing device A1, the negative electrode of this diode D1 is connected with resistance R 1, the two ends shunt capacitance C3 of diode D1, the two ends shunt capacitance C4 of resistance R 1, put between the output of device A1 and the source electrode of field effect transistor Q1 tandem tap SPST and diode D2 successively, the anode of diode D2 is connected with switch S PST, the negative electrode of diode D2 is connected with the source electrode of field effect transistor Q1, and the anode of diode D2 is connected with the grid of field effect transistor Q1, series resistance R2 between the in-phase input end of field effect transistor Q1 drain electrode and transport and placing device A2, the source electrode of this field effect transistor Q1 and capacitor C 1 series connection ground connection, the drain electrode of this field effect transistor Q1 and capacitor C 2 series connection ground connection, and the drain electrode of this field effect transistor Q1 is connected with the drain electrode of field effect transistor Q2, the source ground of field effect transistor Q2,
Pulse-triggered unit comprises differential circuit and comparison circuit, differential circuit comprises capacitor C 5 and transport and placing device A3, the inverting input series resistance R3 of this transport and placing device A3 and capacitor C 5, and series resistance R6 between the inverting input of this transport and placing device A3 and transport and placing device A3 output, the in-phase input end of this transport and placing device A3 and resistance R 4 series connection ground connection, comparison circuit comprises transport and placing device A4 and resistance R 5, the inverting input of this transport and placing device A4 is connected with the output of transport and placing device A3, the output of this transport and placing device A4 is connected with resistance R 5, one end of resistance R 5 and transition twin zener dioder series connection ground connection, resistance R 5 is connected with above-mentioned switch S PST with the node between transition twin zener dioder.
Wherein, transport and placing device A1 and transport and placing device A2 adopt LF356 operational amplifier, and transport and placing device A3 adopts LM338 operational amplifier, and transport and placing device A4 adopts LM339A operational amplifier.The capacitance size of capacitor C 3 and capacitor C 4 is 560PF.The capacitance size of capacitor C 5 is 50nF.The grid of field effect transistor Q2 connects single-chip microcomputer.
LF356 operational amplifier is to have the operational amplifier that field effect transistor is made input stage.Transport and placing device A1 is to be mainly storage capacitance C1, and capacitor C 2 provides charging current, and transport and placing device A2 is placed in total feedback loop, and this is conducive to tracking accuracy.By single-chip processor i/o mouth P1.5, send high level and make field effect transistor Q2 conducting, thereby storage capacitance is discharged, substantially can make the voltage in storage capacitance be put into zero, so just for lower secondary tracking, get ready.The course of work of circuit is as follows:
When the drain electrode turn-on condition of field effect transistor Q1 meets, field effect transistor Q1 conducting.Transport and placing device A1 is by diode D2, and field effect transistor Q1, to capacitor C 1, C2 charging, makes output tracking input.When diode D2 meets cut-off condition, the output of transport and placing device A1 is negative voltage, the grid of field effect transistor Q1 is also negative voltage, and source electrode is because the electric discharge of capacitor C 1 is slow, so be positive voltage, thereby field effect transistor Q1 cut-off, at this moment the leakage current passage between storage capacitance C2 and the output of transport and placing device A2 is cut off by diode D2 and field effect transistor Q1.Fig. 2 circuit consists of differential circuit and comparison circuit.When signal is prepared to rise, comparator output high level, analog switch SPST conducting, peak holding circuit conducting, storage capacitance charging.When signal is when starting to decline after peaking, comparator output low level, analog switch SPST disconnects, and peak holding circuit storage capacitance keeps peak impulse voltage; The low level of comparator triggers singlechip interruption simultaneously, starts A/D conversion.After A/D EOC, single-chip microcomputer P1.5 mouth sends high level and controls field effect transistor Q2 conducting, and storage capacitance C1, C2 in peak holding circuit are discharged.
Finally it should be noted that: the foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, although the utility model is had been described in detail with reference to previous embodiment, for a person skilled in the art, its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement.All within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection range of the present utility model.
Claims (5)
1. random pulses trigger a peak sampling hold circuit, it is characterized in that, comprise pulse-triggered unit and peak value holding unit,
Described pulse-triggered unit comprises transport and placing device A1, transport and placing device A2, field effect transistor Q1, field effect transistor Q2 and switch S PST, series diode D1 and resistance R 1 successively between the inverting input of the inverting input of described transport and placing device A1 and transport and placing device A2, the anode of described diode D1 is connected with the inverting input of transport and placing device A1, the negative electrode of this diode D1 is connected with resistance R 1, the two ends shunt capacitance C3 of described diode D1, the two ends shunt capacitance C4 of described resistance R 1, described tandem tap SPST and the diode D2 successively put between the output of device A1 and the source electrode of field effect transistor Q1, the anode of described diode D2 is connected with switch S PST, the negative electrode of diode D2 is connected with the source electrode of field effect transistor Q1, and the anode of diode D2 is connected with the grid of field effect transistor Q1, series resistance R2 between the in-phase input end of described field effect transistor Q1 drain electrode and transport and placing device A2, the source electrode of this field effect transistor Q1 and capacitor C 1 series connection ground connection, the drain electrode of this field effect transistor Q1 and capacitor C 2 series connection ground connection, and the drain electrode of this field effect transistor Q1 is connected with the drain electrode of field effect transistor Q2, the source ground of field effect transistor Q2,
Described pulse-triggered unit comprises differential circuit and comparison circuit, described differential circuit comprises capacitor C 5 and transport and placing device A3, the inverting input series resistance R3 of this transport and placing device A3 and capacitor C 5, and series resistance R6 between the inverting input of this transport and placing device A3 and transport and placing device A3 output, the in-phase input end of this transport and placing device A3 and resistance R 4 series connection ground connection, described comparison circuit comprises transport and placing device A4 and resistance R 5, the inverting input of this transport and placing device A4 is connected with the output of described transport and placing device A3, the output of this transport and placing device A4 is connected with resistance R 5, one end of described resistance R 5 and transition twin zener dioder series connection ground connection, described resistance R 5 is connected with above-mentioned switch S PST with the node between transition twin zener dioder.
2. random pulses according to claim 1 trigger peak sampling hold circuit, it is characterized in that, described transport and placing device A1 and transport and placing device A2 adopt LF356 operational amplifier, and described transport and placing device A3 adopts LM338 operational amplifier, and described transport and placing device A4 adopts LM339A operational amplifier.
3. random pulses according to claim 1 and 2 trigger peak sampling hold circuit, it is characterized in that, the capacitance size of described capacitor C 3 and capacitor C 4 is 560PF.
4. random pulses according to claim 1 and 2 trigger peak sampling hold circuit, it is characterized in that, the capacitance size of described capacitor C 5 is 50nF.
5. random pulses according to claim 1 and 2 trigger peak sampling hold circuit, it is characterized in that, the grid of field effect transistor Q2 connects single-chip microcomputer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320742598.2U CN203554419U (en) | 2013-11-22 | 2013-11-22 | Random pulse triggering peak sampling and keeping circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320742598.2U CN203554419U (en) | 2013-11-22 | 2013-11-22 | Random pulse triggering peak sampling and keeping circuit |
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| CN203554419U true CN203554419U (en) | 2014-04-16 |
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| CN201320742598.2U Expired - Fee Related CN203554419U (en) | 2013-11-22 | 2013-11-22 | Random pulse triggering peak sampling and keeping circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105547577A (en) * | 2016-02-03 | 2016-05-04 | 河南柴油机重工有限责任公司 | Signal sampling protection method used for voltage transmitter and protection circuit |
| CN106888006A (en) * | 2017-03-17 | 2017-06-23 | 华自科技股份有限公司 | Signal peak detection means |
| CN107707260A (en) * | 2017-11-27 | 2018-02-16 | 中山路得斯空调有限公司 | A kind of instantaneous sampling holding circuit for low speed ADC |
| CN107942127A (en) * | 2017-11-17 | 2018-04-20 | 亿嘉和科技股份有限公司 | Peak-detector circuit |
| CN107968654A (en) * | 2017-12-29 | 2018-04-27 | 浙江九州量子信息技术股份有限公司 | A kind of narrow pulse peak using compensation network |
| CN108459195A (en) * | 2018-03-26 | 2018-08-28 | 昆山龙腾光电有限公司 | Peak detector |
-
2013
- 2013-11-22 CN CN201320742598.2U patent/CN203554419U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105547577A (en) * | 2016-02-03 | 2016-05-04 | 河南柴油机重工有限责任公司 | Signal sampling protection method used for voltage transmitter and protection circuit |
| CN105547577B (en) * | 2016-02-03 | 2018-12-07 | 河南柴油机重工有限责任公司 | A kind of signal sampling guard method and protection circuit for pressure transmitter |
| CN106888006A (en) * | 2017-03-17 | 2017-06-23 | 华自科技股份有限公司 | Signal peak detection means |
| CN106888006B (en) * | 2017-03-17 | 2020-11-03 | 华自科技股份有限公司 | Signal peak value detection device |
| CN107942127A (en) * | 2017-11-17 | 2018-04-20 | 亿嘉和科技股份有限公司 | Peak-detector circuit |
| CN107707260A (en) * | 2017-11-27 | 2018-02-16 | 中山路得斯空调有限公司 | A kind of instantaneous sampling holding circuit for low speed ADC |
| CN107968654A (en) * | 2017-12-29 | 2018-04-27 | 浙江九州量子信息技术股份有限公司 | A kind of narrow pulse peak using compensation network |
| CN107968654B (en) * | 2017-12-29 | 2023-11-24 | 浙江九州量子信息技术股份有限公司 | Narrow pulse peak value holding circuit adopting compensation network |
| CN108459195A (en) * | 2018-03-26 | 2018-08-28 | 昆山龙腾光电有限公司 | Peak detector |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C53 | Correction of patent for invention or patent application | ||
| CB03 | Change of inventor or designer information |
Inventor after: Li Shanshan Inventor after: Feng Haidong Inventor after: Liu Jiangang Inventor after: Fang Yulong Inventor before: Li Shanshan |
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| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: LI SHANSHAN TO: LI SHANSHAN FENG HAIDONG LIU JIANGANG FANG YULONG |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140416 Termination date: 20161122 |
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| CF01 | Termination of patent right due to non-payment of annual fee |