WO2023274407A1 - Switch operational amplifier - Google Patents

Switch operational amplifier Download PDF

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WO2023274407A1
WO2023274407A1 PCT/CN2022/103359 CN2022103359W WO2023274407A1 WO 2023274407 A1 WO2023274407 A1 WO 2023274407A1 CN 2022103359 W CN2022103359 W CN 2022103359W WO 2023274407 A1 WO2023274407 A1 WO 2023274407A1
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control
zero
switch
loss
output
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PCT/CN2022/103359
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French (fr)
Chinese (zh)
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陈启星
罗启宇
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陈启星
罗启宇
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Publication of WO2023274407A1 publication Critical patent/WO2023274407A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

Definitions

  • the present invention is a switch operational amplifier, which belongs to the field of electronic circuits.
  • the current op amp is a basic op amp, which consists of three stages: input stage + intermediate stage + output stage. There are methods such as controlling the power supply of the op amp to control the on and off of the op amp, and there is no way to directly control the on and off of the output stage triode. A method and device for realizing on-off control of an operational amplifier.
  • ⁇ Triodes include bipolar triodes and field effect transistors. This article takes the bipolar triode circuit as an example to describe, and its principle is also applicable to field effect tube circuits;
  • the subscript of the base potential follows the subscript of the triode, for example, the base potential of the output transistor T c2 is marked as V c2 ;
  • the switching op amp includes a switching follower. After connecting the op amp in the switching op amp to form a follower, the switching op amp becomes a switching follower, also known as a follower switch, which is a zero-loss analog switch. Specially named "zero loss switch";
  • ⁇ Low level is represented by "0", and high level is represented by "1".
  • V ⁇ E INT(U ⁇ Z / ⁇ V)* ⁇ V, that is, based on the quantization unit ⁇ V
  • V ⁇ E is an analog quantity
  • ⁇ ⁇ , ⁇ , ⁇ , ..., m respectively represent the first level, the second level, the third level, ..., the last level, and the wildcard is ⁇ ;
  • the first subscript of ⁇ e ) is the level subscript, ⁇ , ⁇ , ⁇ , ..., m represent the first level, the second level, the third level, ..., the last level respectively, and the second subscript is the order subscript , indicating the 0th order, the 1st order, the 2nd order...
  • the invention is a switching operational amplifier, based on which a zero-loss switch, a zero-loss multi-channel switch, a zero-loss sample holder, and a high-fidelity ADC/DAC are constructed;
  • the full text of the integrated operational amplifier is referred to as the operational amplifier.
  • the traditional operational amplifier is called the basic operational amplifier in this article.
  • the basic operational amplifier includes three stages: input stage + intermediate stage + output stage.
  • the switching operational amplifier is based on the basic operational amplifier Add a control stage to control the on-off of the output stage;
  • the output stage includes an NPN output transistor and a PNP output transistor
  • the control stage is composed of control pipe pairs
  • the control transistor includes a bipolar transistor or a field effect transistor, the base of the bipolar transistor or the grid of the field effect transistor is the pan-base of the control transistor, and the emitter of the bipolar transistor Or the source of the field effect tube is the flood emitter of the control tube, the collector of the bipolar triode or the drain of the field effect tube is the flood collector of the control tube, and the flood emitter
  • the channel between the pan-collector and the pan-collector is the main channel of the control tube;
  • a control tube pair includes a first control tube and an identical second control tube, the ubiquitous bases of the two control tubes are connected and controlled by the same control signal I; the main channel of the first control tube Connected between the power supply +V CC and the base of the PNP output transistor, the main channel of the second control tube is connected between the power supply -V CC and the base of the NPN output transistor;
  • the first control tube makes the base of the PNP output transistor communicate with the power supply +V CC , so that the PNP output The transistor is cut off;
  • the second control tube connects the base of the NPN output transistor to the power supply -V CC , so that the NPN output transistor is cut off; at this time, the switching amplifier is in an OFF state;
  • control signal I makes the main channel of the first control tube and the second control tube cut off, the first control tube and the second control tube are equivalent to non-existence; state, that is, the switching op amp is in the ON state;
  • ⁇ , ⁇ , ⁇ , ..., m respectively represent the first level, the second level, the third level, ..., the last level, and the wildcard is ⁇ ;
  • V ⁇ e , R ⁇ e , I ⁇ e , PS ⁇ e , S ⁇ e are level subscripts, ⁇ , ⁇ , ⁇ , ..., m, respectively represent the first level, the second level, the third level, ..., the last level, the second level
  • the subscript is the order subscript, indicating the 0th order, the 1st order, the 2nd order...
  • the wildcard of the order subscript is e; the subscript ⁇ e is called the ⁇ th order and the eth order; the order of various chain devices is defaulted
  • a switching operational amplifier according to the basic technical feature, further characterized in that the pair of control tubes includes a pair of NPN control tubes and a pair of PNP control tubes,
  • the NPN control tube pair includes a first NPN control tube and a second NPN control tube
  • the flood collector of the first NPN control transistor is connected to the power supply +V CC , the flood emitter of the first NPN control transistor is connected to the base of the PNP output transistor, and the flood emitter of the second NPN control transistor is connected to Power supply-V CC , the pan-collector of the second NPN control transistor is connected to the base of the NPN output transistor;
  • the base of the PNP output transistor will be connected to the power supply +V CC by the first NPN control transistor and cut off; the two output transistors are cut off, and at this time, the switch The op amp is in the off state; this is the high-level turn-off switch op amp of the control signal, referred to as the high-off and low-pass op amp, and -I is the high-off and low-pass control terminal;
  • the PNP control tube pair includes a first PNP control tube and a second PNP control tube;
  • the flood emitter of the first PNP control tube is connected to the power supply +V CC , the pan collector of the first PNP control tube is connected to the base of the PNP output transistor, and the pan collector of the second PNP control tube is connected to Power supply-V CC , the flood emitter of the second PNP control transistor is connected to the base of the NPN output transistor;
  • the switch op amp is in an off state; this is the low level of the control signal to turn off the switch op amp, referred to as the low-cut high-pass op amp, and +I is the low-cut high-pass control terminal;
  • the base of the NPN output transistor will be connected to the power supply -V CC and cut off, and the base of the PNP output transistor will be turned off. connected to the power supply +V CC and cut off; at this time, the switching amplifier is in the off state.
  • both the NPN control tube pair and the PNP control tube pair exist, it is a dual-control op amp, with -I, +I control terminals; only when the NPN control tube pair is a high-break low-pass op amp, with a -I control terminal; only The timing of the PNP control tube is a low-cut high-pass op amp with a +I control terminal.
  • Technical feature 3 a zero-loss switch including the switching amplifier described in technical feature 2, characterized in that,
  • the output end of the switch op amp is connected with the inverting input end to form a zero-loss switch, the non-inverting input end of the switch op amp is used as the input end of the zero loss switch, and the control end of the switch op amp is used as the zero loss switch.
  • Technical feature 4 a bidirectional zero-loss switch comprising the zero-loss switch described in technical feature 3, further characterized in that,
  • the two zero-loss switches are connected in parallel in the forward direction and the reverse direction, and the corresponding control terminals of the two are connected, -I is connected to -I, and +I is connected to +I to form a bidirectional zero-loss switch.
  • the feedback-type sample-and-hold device includes an input buffer op amp, an output buffer op amp, a sampling switch, a holding capacitor, and a switch op amp feedback type sampling
  • the retainer is characterized by,
  • the input buffer op-amp of the original feedback type sample-and-hold device is replaced with the switch op-amp, and the control terminal of the switch op-amp is connected with a clock signal to replace the original sampling switch.
  • the series-type sample-and-hold device includes an input voltage follower, an output voltage follower, a sampling switch, and a holding capacitor.
  • the zero-loss switch series sampling The retainer is characterized by,
  • the input voltage follower of the original serial sample-and-hold device is replaced by the zero-loss switch, and the control terminal of the zero-loss switch is connected with a clock signal to replace the original sampling switch.
  • a q-bit zero-loss multi-channel switch including a q-bit decoder and a plurality of zero-loss switches; 2 q output terminals of the q-bit decoder are connected to the control terminals of the zero-loss switches, including For one-to-one connection, one-to-many connection, and many-to-one connection, the input end of the zero-loss switch is used as the input end of the zero-loss multi-way switch.
  • Technical feature 8 a bidirectional zero-loss multi-channel switch including the bidirectional zero-loss switch described in technical feature 4, characterized in that,
  • a q-bit bidirectional zero-loss multi-channel switch includes a q-bit decoder and a plurality of bidirectional zero-loss switches; 2 q output terminals of the q-bit decoder are connected to the control terminals of the bidirectional zero-loss switch
  • the connection includes a one-to-one connection, a one-to-many connection, and a many-to-one connection, and the input end of the zero-loss switch is used as the input end of the zero-loss multi-way switch.
  • the ⁇ -th sub-level SADC is a q ⁇ bit SADC ⁇ , including a q ⁇ bit parallel ADCB ⁇ , a bridge potential V ⁇ E extraction module, and an intermediate module,
  • the intermediate module includes a sample-and-hold T/H, a summer ⁇ ⁇ , an amplifier AM ⁇ ;
  • the ⁇ -level analog signal voltage U ⁇ y is connected to the sample holder T/H and processed to become a stable signal voltage U ⁇ Z .
  • U ⁇ Z is divided into two branches, one of which is sent to the minuend terminal of the summer ⁇ ⁇ , and the other is sent to the comparison
  • the chain acts as the non-inverting input signal of each comparator, and compares it with the reference potential connected to the inverting input of each comparator;
  • the q ⁇ -bit parallel ADCB ⁇ includes a q ⁇ -bit reference resistor chain (R ⁇ 0 , R ⁇ 1 , R ⁇ 2 , ..., R ⁇ (Q ⁇ -1) ), a q ⁇ -bit comparator chain (C ⁇ 0 , C ⁇ 1 , C ⁇ 2 ,..., C ⁇ (Q ⁇ -1) , where C ⁇ 0 can be omitted), a q ⁇ bit encoder, each resistance of the reference potential chain is equal to form Q ⁇ reference potential points with equal intervals ⁇ V ( V ⁇ 0 , V ⁇ 1 , V ⁇ 2 , ..., V ⁇ (Q ⁇ -1) );
  • the lower part of the dual-control zero-loss switch PS ⁇ e is the low-break high-pass terminal +I ⁇ e
  • the upper part is the high-break low-pass terminal -I ⁇ e
  • -I ⁇ 0 of PS ⁇ 0 is connected to +I ⁇ 1 of PS ⁇ 1 and - I ⁇ 1 is connected to +I ⁇ 2 of PS ⁇ 2
  • -I ⁇ 2 of PS ⁇ 2 is connected to +I ⁇ 3 of PS ⁇ 3 , ..., and so on, (PS ⁇ 0 , PS ⁇ 1 , PS ⁇ 2 , ..., PS ⁇ (Q ⁇ -1) )
  • each connection point is marked with a low-break high-pass end, forming a control terminal chain (+I ⁇ 1 , +I ⁇ 2 , ..., +I ⁇ (Q ⁇ - 1 ) ), and connect +I ⁇ 0 of PS ⁇ 0 to 1, and -I ⁇ (Q ⁇ -1) of PS ⁇
  • the output control word of the comparator chain (I ⁇ 1 , I ⁇ 2 ,..., I ⁇ (Q ⁇ -1) ) has two output directions, one output direction is the encoder, and the q ⁇ bit of the ⁇ th stage ADCB ⁇ is obtained through the encoder digital signal to realize the AD conversion of the ⁇ th stage; the other output direction is to be connected as a control word to the control terminal of the double-controlled zero-loss switch corresponding to the subscript (+I ⁇ 1 , +I ⁇ 2 ,..., +I ⁇ (Q ⁇ - 1) ), each output end of the double-controlled zero-loss switch is connected to the common output port BUS ⁇ and then connected to the subtrahend end of the summator ⁇ ⁇ ;
  • the comparator output value corresponding to the subscript of the bridge potential V ⁇ E and below the reference potential point is equal to 1, and the comparator output value of the subscript corresponding to the reference potential point greater than the bridge potential V ⁇ E value is equal to 0, that is, with the V ⁇ E demarcation point,
  • the output value of the comparator below V ⁇ E is a string of 1s, and the output value of the comparator above V ⁇ E is a string of 0s; only PS ⁇ E is at the critical point where a string of 1s becomes a string of 0s, and the dual-control zero-loss switch
  • the extraction module of the bridge potential V ⁇ E includes a q ⁇ bit zero-loss multiplex switch; the q ⁇ bit zero-loss multiplex switch includes a q ⁇ bit decoder, a zero-loss switch chain (S ⁇ 0 , S ⁇ 1 , S ⁇ 2 ,..., S ⁇ (Q ⁇ -1) ), each zero-loss switch output terminal is connected to the common output terminal BUS ⁇ ;
  • each zero-loss switch of the zero-loss switch chain The input terminals of each zero-loss switch of the zero-loss switch chain, the inverting input terminals of each comparator of the comparator chain, and each reference potential point of the reference resistance chain, each terminal or point of the three is according to the subscript Corresponding relationship to connect;
  • An n-bit DAC is composed of m sub-level SDACs and a proportional summation op amp.
  • ( ⁇ level, ⁇ level, ⁇ level, ..., level m) weight calculator (AW ⁇ , AW ⁇ , AW ⁇ , ..., AW m ), the magnifications of the weight calculator are (AW ⁇ , AW ⁇ , AW ⁇ , ..., AW m ), with AW ⁇ as the benchmark, let
  • the number of digits of the ⁇ th sub-stage SDAC ⁇ is q ⁇
  • SDAC ⁇ includes a q ⁇ bit multiplexer and a q ⁇ bit reference resistor chain; the resistances of the reference potential chain are equal, a total of 2 q ⁇ equidistant reference potential points (V ⁇ 0 , V ⁇ 1 , V ⁇ 2 ,..., V ⁇ (Q ⁇ -1) );
  • the multi-way switch consists of a q ⁇ bit decoder and a q ⁇ bit zero-loss switch chain (S ⁇ 0 . _ _ Level common output terminal BUS ⁇ ;
  • the SDAC ⁇ at all levels (BUS ⁇ , BUS ⁇ , BUS ⁇ , ..., BUS ⁇ ) are respectively sent to the weight calculators (AW ⁇ , AW ⁇ , AW ⁇ , ..., AW m ) corresponding to the subscripts, each weight calculator Converge to the summer ⁇ ⁇ for summing to realize DA conversion
  • the decoder When SDAC ⁇ receives a digital signal, the decoder will uniquely select a zero-loss switch among the 2 q ⁇ zero-loss switches, and the zero-loss switch will take out the connected reference potential, and the reference potential It is a bridge between digital signal and analog signal, named as bridge potential V ⁇ E , the bridge potential V ⁇ E is taken out and then sent to the common output terminal to realize DA conversion of the sub-stage SDAC ⁇ ;
  • the bridge potentials obtained are respectively (V ⁇ E , V ⁇ E , V ⁇ E , ..., V ⁇ E ), and the weights of the bridge potentials at each level are Differently, the total output voltage V out of the DA conversion is obtained after the weighted calculation of the bridge potentials at all levels is added; the weighted calculation and the added circuit can use proportional summation op amps;
  • the single control word switch op amp is named (SA); the double (Pair) control word switch op amp is named (PA); the single control word switch is named (AS); The high-pass switch is named (HS); the high-break low-pass switch is named (LS); the double control word switch is named (PS);
  • Figure 2.1 Block diagram of a single control word switching op amp with output stage and control stage details; 10 - input stage; 11 - intermediate stage; 12 - output stage; 13 - single control control stage; SA - switching op amp; u bN - Inverting input signal; u bP - non-inverting input signal; u b0 - output signal; T b1 - NPN output tube; T b2 - PNP output tube; V b1 -T b1 base potential; V b2 -T b2 base Potential; R b1 -T b1 bias resistor; R b2 -T b2 bias resistor; D b1 -T b1 bias diode; D b2 -T b2 bias diode; T b3 - the first PNP control tube; T b4 - The second PNP control tube; I + - low off high pass;
  • Figure 2.4 Schematic diagram of a single control word switching op amp connected into a zero-loss switch; SA-switching op amp; U bP -input signal; U b0 -output signal; I + -low-off high-pass;
  • FIG. 3.1 Block diagram of single control word switching op amp with output stage and control stage details; 10 - input stage; 11 - intermediate stage; 12 - output stage; 14 - dual control control stage; PA - dual control switching op amp; u cN - inverting input signal; u cP - non-inverting input signal; u c0 - output signal; T c1 - NPN output tube; T c2 - PNP output tube; V c1 -T c1 base potential; V c2 -T c2 Base potential; R c1 - T c1 bias resistor; R c2 - T c2 bias resistor; D c1 - T c1 bias diode; D c2 - T c2 bias diode; T c3 and T c4 - first and second Two PNP control tubes (for op amp low-off high-pass tubes); T c5 and T c6 - the first and second NPN
  • Figure 4.1 -feedback sample-and-hold device; SA 1 -switching op amp; V in -input terminal; A 1 -output amplifier; C 1 -sampling capacitor; CLK-clock pulse; V out -output signal;
  • Figure 4.2 Series Sample and Holder; Series Sample and Holder ( Figure 4.2), AS 2 - Zero Loss Switch; V in - Input Terminal,; A 2 - Output Amplifier; C 2 - Sampling Capacitor; CLK - Clock Pulse ; V out - output signal;
  • FIG. 5.1 - ⁇ th stage SDAC (sub-stage DAC); dashed box SDAC ⁇ - ⁇ th stage SDAC; dotted box MS ⁇ - ⁇ th stage zero-loss multiplex switch; dashed box LSC ⁇ - ⁇ th stage low switch chain; dashed line Frame RC ⁇ - reference resistance chain of ⁇ th stage; YM ⁇ - ⁇ th stage decoder; (d ⁇ 2 d ⁇ 1 d ⁇ 0 ) - digital input signal; (I ⁇ 7 ⁇ I ⁇ 0 ) - output of ⁇ th stage decoder control word; (LS ⁇ 7 ⁇ LS ⁇ 0 )-low switch, forming a low switch chain; BUS ⁇ -the common end of the ⁇ -level switch chain or multi-way switch; d ⁇ 2 d ⁇ 1 d ⁇ 0 -input signal; (R ⁇ 7 ⁇ R ⁇ 0 )-the reference resistance chain of the ⁇ th stage;
  • Figure 5.2 The ⁇ th stage bidirectional multiplexer; the symbols are the same as those in Figure 5.1, with a set of (IO ⁇ 7 ⁇ IO ⁇ 0 ) ⁇ th stage input and output ports added;
  • Figure 6 bridge potential DAC; the symbols are the same as those in Figure 5.1, and the symbols added are: AW ⁇ - the weight operator of the ⁇ stage; ⁇ - summator; V ⁇ - summation voltage;
  • FIG. 7.1 block diagram of the ⁇ th stage MS type m*3bit bridge potential ADC; the symbols that have not appeared before are: SADC1 ⁇ - the ⁇ th stage MS type m*3bit bridge potential ADC; ADM ⁇ - the ⁇ th stage parallel ADC; ( C ⁇ 7 ⁇ C ⁇ 0 )-the comparator chain of the ⁇ th stage; ENC ⁇ —the ⁇ th stage encoder; U ⁇ y —the input analog signal of the ⁇ th stage; U ⁇ (y+1) —the output analog signal of the ⁇ th stage; U ⁇ z - analog signal after sampling and holding; V ⁇ E - bridge potential; U ⁇ X - mantissa voltage after extracting bridge potential;
  • Figure 7.2 block diagram of the ⁇ th stage PSC type m*3bit bridge potential ADC; the symbols that have not appeared before are: SADC2 ⁇ - the ⁇ th stage PSC type m*3bit bridge potential ADC; PSC ⁇ - the ⁇ th stage off/on chain; (PS ⁇ 7 ⁇ PS ⁇ 0 )-the ⁇ th stage is off/on;
  • the control stage is composed of a pair of control tubes or multiple pairs of control tubes.
  • a pair of output tubes are NPN/PNP transistors
  • a pair of control tubes are two NPN tubes or two PNP tubes.
  • a pair of NPN control tubes is named Named as "NPN controller”
  • the on-off of the output tube is the on-off of the switching amplifier; therefore, the control word signal determines the switching op-amp in The working state is still in the high-impedance state; the op amp with the added control stage is referred to as "switching op amp".
  • Example 2 Zero-loss switch constructed from a switching op amp
  • zero-loss switching is an application of switching op amps, and all switching op amps described in this article include zero-loss switching;
  • the author has invented a zero-loss switch before, which is to place the control tube on the power path of the op amp, and control the ON/OFF of the op amp by controlling the power on and off of the op amp. It has two major disadvantages: the first is The control tube will occupy the voltage of the op amp, which will reduce the operating voltage of the op amp and affect the performance of the op amp. The zero-loss switch overcomes these two defects.
  • the zero-loss switch mentioned in this article does not refer to the zero-loss switch invented before, but the zero-loss switch invented this time;
  • Embodiment 3 A single control word switch operational amplifier SA
  • the control stage can be composed of a pair of control tubes, named single word control stage, the corresponding op amp is named single control word switch op amp, and the corresponding zero loss switch is named "single control zero loss switch"; the control stage can also be composed of Multiple pairs of control tubes are connected to form a logic circuit of "AND, OR, NOT" to form a complex control level controlled by multiple control words, which is named multi-word control level, and the corresponding operational amplifier is named multi-control word switching op amp;
  • the complex control relationship can also be composed of a single control word switch op amp plus an external logic circuit;
  • Single control word switching op amp includes "low-off high-pass switching op amp” and "high-off low-pass switching op amp";
  • the NPN control tube is removed, which is Figure 2.1, there is only a pair of PNP control tubes T b3 and T b4 , named "PNP controller"; the emitter and collector of the control tube T b4 are respectively connected to the NPN output tube T
  • the base of b1 is connected to -V CC
  • the collector and emitter of another control transistor T b3 are respectively connected to the base of PNP output transistor T b2 and +V CC
  • the control tube T b3 connects the base of the PNP output transistor T b2 to +V CC , and turns off the PNP output transistor.
  • low-off high-pass switching op amp when the op amp is connected as a follower, the low-off high-pass switching op amp becomes a "low-off high-pass zero-loss switch", so the low-off high-pass switching op amp Including "low-break high-pass zero-loss switch”; low-break high-pass zero-loss switch is referred to as “high switch (HS, that is, High Switch)";
  • Embodiment 4 Double control word switching op amp PA
  • the double-pass word switch op amp includes a double-pass word zero-loss switch, and the op-amp in the double-pass word switch op amp is connected as a voltage follower ( Figure 3.4), and the double-pass word switch op amp becomes a double-pass word zero Loss switch, referred to as double-pass word switch PS (meaning: a pair of S in the Pair control word), its symbol diagram is ( Figure 3.5 and 7.3); because "double-pass word switch" is used frequently in this paper, so the double-pass word switch The word switch is specially named "off/on", “off/on” is the reverse of the word "switch";
  • Embodiment 5 A zero-loss switching sample-and-hold device constructed of zero-loss switches, referred to as a zero-loss sample-and-hold device
  • sample-and-hold devices There are many types of sample-and-hold devices, and the mainstream ones are feedback-type sample-and-hold devices and series-type sample-and-hold devices;
  • the control word signal is named "ON signal”, as long as the control word signal that makes the switch op amp OFF is named "OFF signal”;
  • the switching operational amplifier SA 1 acts as a sampling switch and input amplifier
  • the non-inverting input terminal of the switching operational amplifier SA 1 serves as the signal input terminal V in
  • its inverting input terminal is connected to the output of the output amplifier A 1
  • the terminals are connected to form a large closed-loop circuit.
  • the sampling capacitor C1 is connected between the inverting terminal of A1 and the output terminal, which can improve the charging and discharging speed.
  • the clock pulse is connected to the control word of the switching op amp. When the clock pulse When the "ON signal" of CLK arrives, the switch op amp SA 1 is turned on, and the sampling capacitor C 1 samples the input signal V in . When the clock pulse CLK "OFF signal” arrives, the switch op amp is turned off, and the sampling capacitor C 1 Hold the sampled signal, the output signal V out of the output amplifier A 1 is equal to the hold signal of C 1 ;
  • the zero-loss switch AS 2 acts as a sampling switch, its input terminal is V in , the output amplifier A 2 is connected as a voltage follower, and the sampling capacitor C 2 is connected between the output terminal of AS 2 and the ground
  • the clock pulse is connected to the control word of AS 2 , when the "ON signal” of the clock pulse CLK arrives, AS 2 conducts, and the sampling capacitor C 2 samples the input signal V in , when the clock pulse CLK "OFF signal"
  • AS 2 is turned off, the sampling capacitor C 2 holds the sampled signal, and the output signal V out of the output amplifier A 2 is equal to the holding signal of C 2 ;
  • the zero-loss multi-channel switch, the bridge potential DAC and the bridge potential ADC are named as the common name "total device", and the total device is composed of multi-level "sub-level devices";
  • a total device of m level by 3bit is virtualized, which is composed of m sub-level devices.
  • the number system is parentheses plus subscript, so that the binary subscript is "2", and the octal subscript is "8".
  • the default analog signal adopts octal, that is, the analog signal without subscript defaults to octal number, such as 5 by default is (5) 8 ;
  • the digital signal is coded according to the natural code
  • Embodiment 6 A zero-loss multi-way switch constructed of a zero-loss switch, referred to as a multiway switch MS (Multiway-Switch)
  • MS Multiway-Switch
  • the circuit; the decoder selects a zero-loss switch in the switch chain according to the control signal.
  • Embodiment 7 On the basis of the zero-loss multi-way switch, the zero-loss switch is connected in parallel in the opposite direction to form a bidirectional channel multi-way switch;
  • Figure 5.2 is a two-way channel multi-way switch.
  • the multi-way switch in Figure 5.1 is a one-way channel multi-way switch. The signal can only be transmitted from right to left.
  • each low switch LS ⁇ e is connected in parallel with a reverse direction
  • the low switch of LS ⁇ e becomes a bidirectional channel multi-way switch MS ⁇ ;
  • Figure 5.2 is a 3-bit bidirectional channel multi-way switch. This method of connecting each low switch LS ⁇ e in parallel with a low switch in the opposite direction is applicable to q bit Bi-directional channel multiplexer;
  • Embodiment 8 a bridge potential DAC constructed on the basis of a multi-way switch; the bridge potential DAC is composed of m SDAC ⁇ ;
  • SDAC ⁇ consists of three modules: decoder YM ⁇ , low switch chain LSC ⁇ (LS Chain) and resistance chain RC ⁇ (R Chain); among them, decoder YM ⁇ , low switch chain LSC ⁇ constitute a multi-way switch MS ⁇ ;
  • a bridge potential DAC with m*3bit resolution can be composed of m SDAC ⁇ ( Figure 6).
  • the bridge potential DAC includes SDAC ⁇ , SDAC ⁇ , SDAC ⁇ ,..., SDAC m sub-levels.
  • the total output signal V ⁇ is the total output signal V ⁇ after the potential of each weight bridge is summed by the summer ⁇ ;
  • the same principle can be constructed into an m-level bridge potential DAC with different bits for each level.
  • the resolution of the bridge potential DAC is equal to the sum of the resolutions of each SDAC
  • Embodiment 9 The MS type bridge potential ADC that combines multi-way switch MS and parallel type ADC to form;
  • Step1 Receive the analog signal U ⁇ y transmitted from the upper SADC ⁇ -1 , stabilize it into an analog signal U ⁇ z after passing through the sample holder T/H , and enter the (parallel ADC) ADM ⁇ for AD conversion;
  • V ⁇ E is the bridge potential
  • the mantissa voltage U ⁇ X is the fractional part of the sampling signal U ⁇ Z , U ⁇ X ⁇ V; the mantissa voltage U ⁇ X , the sampling signal U ⁇ Z and the bridge potential V ⁇ E
  • U ⁇ X U ⁇ Z -V ⁇ E
  • Step2 ADM ⁇ converts V ⁇ E into a digital signal D (q-1) ... D 0 , D (q-1) ... D 0 is divided into two paths, one is used as an AD conversion value, and the other is passed to a multi-way switch MS ⁇ , as the input signal of the road switch MS ⁇ input terminal d (q-1) ...d 0 , the bridge potential V ⁇ E is taken out;
  • m q bit SADCs constitute a m*q bit bridge potential ADC
  • Example 10 A PSC-type bridge potential ADC constructed by combining an off/on-chain PSC with a parallel ADC;
  • Step1 Receive the analog signal U ⁇ y transmitted from the upper SADC ⁇ -1 , stabilize it into an analog signal U ⁇ z after passing through the sample holder T/H , and enter the (parallel ADC) ADM ⁇ for AD conversion;
  • V ⁇ E is the bridge potential
  • the mantissa voltage U ⁇ X is the fractional part of the sampling signal U ⁇ Z , U ⁇ X ⁇ V; the mantissa voltage U ⁇ X , the sampling signal U ⁇ Z and the bridge potential V ⁇ E
  • U ⁇ X U ⁇ Z -V ⁇ E
  • Step2 The comparator chain in ADM ⁇ converts V ⁇ E into a control word (I ⁇ (Q-1) ⁇ I ⁇ 0 ), it should be noted that this control word is different from the control word of the decoder , the control word group of the decoder, only the selected control word is equal to 0, and in Figure 7.2, because the non-inverting input terminal of the comparator is connected to U ⁇ Z and the inverting input terminal is connected to the reference potential, the control word output by the comparator
  • m 3bit SADCs constitute an m*3bit bridge potential ADC.

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Abstract

A switch operational amplifier, a zero-loss switch, a bidirectional zero-loss switch, a feedback sample-and-hold, a series sample-and-hold, a zero-loss multiway switch, a bidirectional zero-loss multiway switch, a bridge-potential ADC, and a bridge-potential DAC. In the switch operational amplifier, a control stage is added to a basic operational amplifier to control the on/off of an output stage; the basic operational amplifier comprises an input stage, an intermediate stage, and an output stage; the output stage comprises an NPN output triode and a PNP output triode; the control stage consists of a control tube pair; the control stage is a pair of identical control tubes having bases connected to each other; emitters and collectors of the control tubes are used to connect the base of the NPN output triode of the output stage to power supply -VCC and connect the base of the PNP output triode of the output stage to power supply +VCC; when the bases of the control tubes are at a high potential, the control tubes are turned on, so that both output stage triodes are turned off, and the operational amplifier is thus turned off; and when the bases of the control tubes are at a low potential, the two control tubes are turned off, in which case the control tubes are not functioned, such that the operational amplifier is in a basic operational amplifier state.

Description

一种开关运放a switch op amp
技术领域：本发明是一种开关运放，属于电子电路领域。Technical field: the present invention is a switch operational amplifier, which belongs to the field of electronic circuits.
技术背景：technical background:
目前的运放为基本运放，包含三个级：输入级+中间级+输出级，有通过控制运放工作电源以控制运放通断等方法，还没有通过直接控制输出级三极管通断来实现控制运放通断的方法和器件。The current op amp is a basic op amp, which consists of three stages: input stage + intermediate stage + output stage. There are methods such as controlling the power supply of the op amp to control the on and off of the op amp, and there is no way to directly control the on and off of the output stage triode. A method and device for realizing on-off control of an operational amplifier.
为简便起见，先进行一些约定：For the sake of simplicity, some conventions are made first:
●三极管包括双极型三极管和场效应管，本文以双极型三极管电路为例进行描述，其原理也适用于场效应管电路；●Triodes include bipolar triodes and field effect transistors. This article takes the bipolar triode circuit as an example to describe, and its principle is also applicable to field effect tube circuits;
●三极管三个极的电位中，重点关注基极电位，所以将基极电位的下标随三极管的下标，如输出管T c2的基极电位标记为V c2； Among the potentials of the three poles of the triode, focus on the base potential, so the subscript of the base potential follows the subscript of the triode, for example, the base potential of the output transistor T c2 is marked as V c2 ;
●开关运放包括开关式跟随器，将开关运放中的运放连接成跟随器后，开关运放就成了开关式跟随器，又称为跟随开关，这是一种零损耗模拟开关，特命名为“零损开关”；The switching op amp includes a switching follower. After connecting the op amp in the switching op amp to form a follower, the switching op amp becomes a switching follower, also known as a follower switch, which is a zero-loss analog switch. Specially named "zero loss switch";
●“通”＝“ON”，“断”＝“OFF”，根据文章通顺性用词，某器件“通”表示该器件通电，对输出管或开关运放而言是表示它处于正常工作的放大状态，对控制管而言是表示它处于饱和导通状态；某器件“断”表示该器件断电，无论是输出管、开关运放还是控制管，都是表示它处于截止状态或称高阻态；● "On" = "ON", "Off" = "OFF", according to the wording of the article, "on" means that the device is powered on, and it means that it is in normal operation for the output tube or switching amplifier. The amplified state, for the control tube, means that it is in a saturated conduction state; if a device is "off", it means that the device is powered off, whether it is an output tube, a switching amplifier or a control tube, it means that it is in a cut-off state or called high resistance state;
●控制字为“I”，约定I＝0为低电平，I＝1为高电平；●The control word is "I", and it is agreed that I=0 is low level, and I=1 is high level;
●低电平用“0”表示，高电平用“1”表示。对于某个控制字I，当I＝0(低电平)时使开关运放ON，那么这个控制字I就命名为“高断低通”，标记为“I -”；反过来，当I＝1(高电平)时使开关运放ON，那么这个控制字I命名为“低断高通”，标记为“I +”；“高断低通”或“低断高通”都是针对运放而言，对于控制管而言刚好相反。 ●Low level is represented by "0", and high level is represented by "1". For a certain control word I, when I=0 (low level), the switch op amp is turned ON, so this control word I is named "high-off low - pass" and marked as "I-"; conversely, when I = 1 (high level) to make the switch operational amplifier ON, then this control word I is named "low-off high-pass" and marked as "I + ";"high-offlow-pass" or "low-off high-pass" are all for For the release, the opposite is true for the control tube.
●某个瞬间，在小于模拟信号U λZ的基准电位中，必定有一个是最接近于U λZ的电位，记为V λE，该基准电位V λE就定义为ADCB λ此瞬间的桥电位，即V λE＜U λZ＜V λ(E+1)，采用取整运算可以得到桥电位V λE，V λE＝INT(U λZ/ΔV)*ΔV，即，基于量化单位ΔV，V λE是模拟量U λZ的整数部分，那么尾数电压U λX就是模拟量U λZ的小数部分，U λX＜ΔV，尾数电压U λX＝模拟电压U λZ-桥电位V λE ●At a certain moment, among the reference potentials that are smaller than the analog signal U λZ , there must be one that is closest to U λZ , denoted as V λE , and the reference potential V λE is defined as the bridge potential of ADCB λ at this moment, that is V λE <U λZ <V λ(E+1) , the bridge potential V λE can be obtained by rounding operation, V λE = INT(U λZ /ΔV)*ΔV, that is, based on the quantization unit ΔV, V λE is an analog quantity The integer part of U λZ, then the mantissa voltage U λX is the fractional part of the analog U λZ , U λX <ΔV, the mantissa voltage U λX = analog voltage U λZ - bridge potential V λE
●α、β、γ、…、m，分别表示第1级、第2级、第3级、…、第末级，其通配符为λ；(V λe、R λe、I λe、PS λe、S λe)的第一下标为级下标，α、β、γ、…、m，分别表示第1级、第2级、第3级、…、第末级，第二下标为阶下标，表示器件链的第0阶、第1阶、第2阶…；其阶 下标通配符为e；称下标 λe为第λ级第e阶；默认各种链器件的阶从小到大的排列方向为从下往上，λ、e、q λ为包括零在内的正整数；qα、qβ、qγ、…分别为第α、β、γ、…级的位数；令Q λ＝2 qλ。 ● α, β, γ, ..., m, respectively represent the first level, the second level, the third level, ..., the last level, and the wildcard is λ; (V λe , R λe , I λe , PS λe , S The first subscript of λe ) is the level subscript, α, β, γ, ..., m represent the first level, the second level, the third level, ..., the last level respectively, and the second subscript is the order subscript , indicating the 0th order, the 1st order, the 2nd order... of the device chain; the subscript wildcard of its order is e; the subscript λe is called the λth order and the eth order; the order of various chain devices is arranged from small to large by default The direction is from bottom to top, λ, e, q λ are positive integers including zero; qα, qβ, qγ, ... are the digits of the α, β, γ, ... levels respectively; let Q λ =2 qλ .
发明内容：Invention content:
本发明是一种开关运放，基于开关运放构造出零损开关、零损多路开关、零损采样保持器、高保真的ADC/DAC；The invention is a switching operational amplifier, based on which a zero-loss switch, a zero-loss multi-channel switch, a zero-loss sample holder, and a high-fidelity ADC/DAC are constructed;
基本技术特征：一种开关运放，其特征在于，Basic technical features: a switching op amp, characterized in that,
集成运算放大器全文简称运放，传统的运放在本文中称为基本运放，基本运放包含三个级：输入级+中间级+输出级，所述开关运放是在基本运放的基础上增加一个控制级以用于控制输出级的通断；The full text of the integrated operational amplifier is referred to as the operational amplifier. The traditional operational amplifier is called the basic operational amplifier in this article. The basic operational amplifier includes three stages: input stage + intermediate stage + output stage. The switching operational amplifier is based on the basic operational amplifier Add a control stage to control the on-off of the output stage;
所述输出级包括NPN输出三极管、PNP输出三极管；The output stage includes an NPN output transistor and a PNP output transistor;
所述控制级由控制管对构成；The control stage is composed of control pipe pairs;
所述控制管包括双极型三极管或场效应管，所述双极型三极管的基极或所述场效应管的栅极为所述控制管的泛基极，所述双极型三极管的发射极或所述场效应管的源极为所述控制管的泛射极，所述双极型三极管的集电极或所述场效应管的漏极为所述控制管的泛集电极，所述泛射极和所述泛集电极之间的通道为所述控制管的主流通道；泛基极的控制信号I＝0表示低电平，I＝1表示高电平；The control transistor includes a bipolar transistor or a field effect transistor, the base of the bipolar transistor or the grid of the field effect transistor is the pan-base of the control transistor, and the emitter of the bipolar transistor Or the source of the field effect tube is the flood emitter of the control tube, the collector of the bipolar triode or the drain of the field effect tube is the flood collector of the control tube, and the flood emitter The channel between the pan-collector and the pan-collector is the main channel of the control tube; the control signal I=0 of the pan-base means a low level, and I=1 means a high level;
一个控制管对包括一个第一控制管和一个相同的第二控制管，所述两个控制管的泛基极相连接并受控于同一个控制信号I；所述第一控制管的主流通道连接于电源+V CC与所述PNP输出三极管的基极之间，所述第二控制管的主流通道连接于电源-V CC与所述NPN输出三极管的基极之间； A control tube pair includes a first control tube and an identical second control tube, the ubiquitous bases of the two control tubes are connected and controlled by the same control signal I; the main channel of the first control tube Connected between the power supply +V CC and the base of the PNP output transistor, the main channel of the second control tube is connected between the power supply -V CC and the base of the NPN output transistor;
当控制信号I使得所述第一控制管和第二控制管的主流通道导通时，所述第一控制管使得所述PNP输出三极管的基极与电源+V CC连通，使所述PNP输出三极管截止；所述第二控制管使得所述NPN输出三极管的基极与电源-V CC连通，使所述NPN输出三极管截止；这时，开关运放处于OFF状态； When the control signal I makes the main channels of the first control tube and the second control tube conduct, the first control tube makes the base of the PNP output transistor communicate with the power supply +V CC , so that the PNP output The transistor is cut off; the second control tube connects the base of the NPN output transistor to the power supply -V CC , so that the NPN output transistor is cut off; at this time, the switching amplifier is in an OFF state;
当控制信号I使得所述第一控制管和第二控制管的主流通道截止时，所述第一控制管和第二控制管相当于不存在；这时，所述开关运放处于基本运放状态，即开关运放处于ON状态；When the control signal I makes the main channel of the first control tube and the second control tube cut off, the first control tube and the second control tube are equivalent to non-existence; state, that is, the switching op amp is in the ON state;
全文名词和符号定义：α、β、γ、…、m，分别表示第1级、第2级、第3级、…、第末级，其通配符为λ；(V λe、R λe、I λe、PS λe、S λe)的第一下标为级下标，α、β、γ、…、m，分别表示第1级、第2级、第3级、…、第末级，第二下标为阶下标，表示器件链的第0阶、第1阶、第2阶…；其阶下标通配符为e；称下标 λe为第λ级第e阶；默认各种链器件的阶从小到大的排列方向为从下往上， λ、e、q λ为包括零在内的正整数；qα、qβ、qγ、…分别为第α、β、γ、…级的位数；Q λ＝2 qλ；V λE＝INT(U λZ/ΔV)*ΔV； Definitions of terms and symbols in the full text: α, β, γ, ..., m, respectively represent the first level, the second level, the third level, ..., the last level, and the wildcard is λ; (V λe , R λe , I λe , PS λe , S λe ) are level subscripts, α, β, γ, ..., m, respectively represent the first level, the second level, the third level, ..., the last level, the second level The subscript is the order subscript, indicating the 0th order, the 1st order, the 2nd order... of the device chain; the wildcard of the order subscript is e; the subscript λe is called the λth order and the eth order; the order of various chain devices is defaulted The arrangement direction from small to large is from bottom to top, λ, e, q λ are positive integers including zero; λ = 2 qλ ; V λE = INT(U λZ /ΔV)*ΔV;
技术特征2：根据基本技术特征所述的一种开关运放，其进一步特征在于，所述控制管对包括NPN控制管对和PNP控制管对，Technical feature 2: A switching operational amplifier according to the basic technical feature, further characterized in that the pair of control tubes includes a pair of NPN control tubes and a pair of PNP control tubes,
所述NPN控制管对包括第一NPN控制管、第二NPN控制管，The NPN control tube pair includes a first NPN control tube and a second NPN control tube,
所述第一NPN控制管的泛集电极连接电源+V CC，所述第一NPN控制管的泛射极连接所述PNP输出三极管的基极，所述第二NPN控制管的泛射极连接电源-V CC，所述第二NPN控制管的泛集电极连接所述NPN输出三极管的基极； The flood collector of the first NPN control transistor is connected to the power supply +V CC , the flood emitter of the first NPN control transistor is connected to the base of the PNP output transistor, and the flood emitter of the second NPN control transistor is connected to Power supply-V CC , the pan-collector of the second NPN control transistor is connected to the base of the NPN output transistor;
所述第一NPN控制管的泛基极、第二NPN控制管的泛基极同时连接于控制信号I+，当控制信号I+＝0时，所述第一NPN控制管、第二NPN控制管截止，相当于所述两个控制管这时候不存在；当控制信号I+＝1时，所述第一NPN控制管、第二NPN控制管导通，所述NPN输出三极管的基极就会被第二NPN控制管连接到电源-V CC而截止，所述PNP输出三极管的基极就会被第一NPN控制管连接到电源+V CC而截止；两个输出管截止，这时，所述开关运放处于关断状态；这是控制信号高电平关断开关运放，简称高断低通式运放，-I为高断低通控制端； The ubiquitous base of the first NPN control transistor and the ubiquitous base of the second NPN control transistor are connected to the control signal I+ at the same time, and when the control signal I+=0, the first NPN control transistor and the second NPN control transistor are cut off , which is equivalent to the fact that the two control transistors do not exist at this time; when the control signal I+=1, the first NPN control transistor and the second NPN control transistor are turned on, and the base of the NPN output transistor will be turned on by the second NPN control transistor. When the two NPN control transistors are connected to the power supply -V CC and cut off, the base of the PNP output transistor will be connected to the power supply +V CC by the first NPN control transistor and cut off; the two output transistors are cut off, and at this time, the switch The op amp is in the off state; this is the high-level turn-off switch op amp of the control signal, referred to as the high-off and low-pass op amp, and -I is the high-off and low-pass control terminal;
所述PNP控制管对包括第一PNP控制管、第二PNP控制管；The PNP control tube pair includes a first PNP control tube and a second PNP control tube;
所述第一PNP控制管的泛射极连接电源+V CC，所述第一PNP控制管的泛集电极连接所述PNP输出三极管的基极，所述第二PNP控制管的泛集电极连接电源-V CC，所述第二PNP控制管的泛射极连接所述NPN输出三极管的基极； The flood emitter of the first PNP control tube is connected to the power supply +V CC , the pan collector of the first PNP control tube is connected to the base of the PNP output transistor, and the pan collector of the second PNP control tube is connected to Power supply-V CC , the flood emitter of the second PNP control transistor is connected to the base of the NPN output transistor;
所述第一PNP控制管的泛基极、第二PNP控制管的泛基极同时连接于控制信号I-，当控制信号I-＝1时，所述第一PNP控制管、第二PNP控制管截止，相当于所述两个控制管这时候不存在；当控制信号I-＝0时，所述第一PNP控制管、第二PNP控制管导通；所述NPN输出三极管的基极就会被第二PNP控制管连接到电源-V CC而截止，所述PNP输出三极管的基极就会被第一PNP控制管连接到电源+V CC而截止；两个输出管截止，这时，所述开关运放处于关断状态；这是控制信号低电平关断开关运放，简称低断高通式运放，+I为低断高通控制端； The ubiquitous base of the first PNP control transistor and the ubiquitous base of the second PNP control transistor are simultaneously connected to the control signal I-, when the control signal I-=1, the first PNP control transistor and the second PNP control transistor The tube is cut off, which means that the two control tubes do not exist at this time; when the control signal I-=0, the first PNP control tube and the second PNP control tube are turned on; the base of the NPN output transistor is on It will be cut off by the second PNP control transistor connected to the power supply -V CC , and the base of the PNP output transistor will be cut off by the first PNP control transistor connected to the power supply +V CC ; the two output transistors are cut off, at this time, The switch op amp is in an off state; this is the low level of the control signal to turn off the switch op amp, referred to as the low-cut high-pass op amp, and +I is the low-cut high-pass control terminal;
NPN控制管对和PNP控制管对中，只要有一对控制管导通，所述NPN输出三极管的基极就会被连接到电源-V CC而截止，所述PNP输出三极管的基极就会被连接到电源+V CC而截止；这时，所述开关运放处于关断状态。 In the pair of NPN control transistors and the pair of PNP control transistors, as long as one pair of control transistors is turned on, the base of the NPN output transistor will be connected to the power supply -V CC and cut off, and the base of the PNP output transistor will be turned off. connected to the power supply +V CC and cut off; at this time, the switching amplifier is in the off state.
当全部控制管都截止时，相当于控制级在电路中不存在，这时，所述运放处于基本运放状态；When all the control tubes are cut off, it means that the control stage does not exist in the circuit, and at this moment, the operational amplifier is in the basic operational amplifier state;
NPN控制管对和PNP控制管对都存在时为双控式运放，具有-I、+I控制端；只有NPN控制管对时 为高断低通式运放，具有-I控制端；只有PNP控制管对时为低断高通式运放，具有+I控制端。When both the NPN control tube pair and the PNP control tube pair exist, it is a dual-control op amp, with -I, +I control terminals; only when the NPN control tube pair is a high-break low-pass op amp, with a -I control terminal; only The timing of the PNP control tube is a low-cut high-pass op amp with a +I control terminal.
技术特征3：一种包括技术特征2所述开关运放的零损开关，其特征在于，Technical feature 3: a zero-loss switch including the switching amplifier described in technical feature 2, characterized in that,
所述开关运放的输出端与反相输入端连接就构成了零损开关，所述开关运放的同相输入端作为所述零损开关的输入端，所述开关运放的控制端作为所述零损开关的控制端；The output end of the switch op amp is connected with the inverting input end to form a zero-loss switch, the non-inverting input end of the switch op amp is used as the input end of the zero loss switch, and the control end of the switch op amp is used as the zero loss switch. The control terminal of the zero loss switch;
只有NPN控制管对时为高断低通式零损开关，具有-I控制端，其导通条件为-I＝0；；只有PNP控制管对时为低断高通式零损开关，具有+I控制端，其导通条件为+I＝1；NPN控制管对和PNP控制管对都存在时为双控零损开关，具有-I、+I控制端，其导通条件为+I＝1且-I＝0；Only the NPN control tube is a high-break low-pass type zero-loss switch with a -I control terminal, and its conduction condition is -I=0; only the PNP control tube is a low-break high-pass type zero-loss switch with + I control terminal, its conduction condition is +I=1; when both NPN control tube pair and PNP control tube pair exist, it is a dual-control zero-loss switch, with -I, +I control terminals, and its conduction condition is +I= 1 and -I=0;
技术特征4：一种包括技术特征3所述的零损开关的双向零损开关，其进一步特征在于，Technical feature 4: a bidirectional zero-loss switch comprising the zero-loss switch described in technical feature 3, further characterized in that,
将两个所述零损开关进行正方向和反方向并联，并且将两者对应的控制端相连接，-I连接-I、+I连接+I，构成双向零损开关。The two zero-loss switches are connected in parallel in the forward direction and the reverse direction, and the corresponding control terminals of the two are connected, -I is connected to -I, and +I is connected to +I to form a bidirectional zero-loss switch.
技术特征5：一种包括技术特征2所述开关运放的反馈型采样保持器，反馈型采样保持器包括输入缓冲运放、输出缓冲运放、采样开关、保持电容，开关运放反馈型采样保持器的特征在于，Technical feature 5: A feedback-type sample-and-hold device including a switching op amp described in technical feature 2. The feedback-type sample-and-hold device includes an input buffer op amp, an output buffer op amp, a sampling switch, a holding capacitor, and a switch op amp feedback type sampling The retainer is characterized by,
将原有反馈型采样保持器的输入缓冲运放用所述开关运放进行置换，所述开关运放的控制端连接时钟信号，取代原有的采样开关。The input buffer op-amp of the original feedback type sample-and-hold device is replaced with the switch op-amp, and the control terminal of the switch op-amp is connected with a clock signal to replace the original sampling switch.
技术特征6：一种包括技术特征3所述零损开关的串联型采样保持器，串联型采样保持器包括输入电压跟随器、输出电压跟随器、采样开关、保持电容，零损开关串联型采样保持器的特征在于，Technical feature 6: A series sample-and-hold device including the zero-loss switch described in technical feature 3. The series-type sample-and-hold device includes an input voltage follower, an output voltage follower, a sampling switch, and a holding capacitor. The zero-loss switch series sampling The retainer is characterized by,
将原有串联型采样保持器的输入电压跟随器用所述零损开关进行置换，所述零损开关的控制端连接时钟信号，取代原有的采样开关。The input voltage follower of the original serial sample-and-hold device is replaced by the zero-loss switch, and the control terminal of the zero-loss switch is connected with a clock signal to replace the original sampling switch.
技术特征7：一种包括技术特征3所述零损开关的零损多路开关，其特征在于，Technical feature 7: a zero-loss multiplex switch including the zero-loss switch described in technical feature 3, characterized in that,
一个q位的零损多路开关，包括一个q位译码器和多个零损开关；所述q位译码器的2 q个输出端与所述零损开关的控制端进行连接，包括一对一的连接、一对多的连接、多对一的连接，所述零损开关的输入端作为所述零损多路开关的输入端。 A q-bit zero-loss multi-channel switch, including a q-bit decoder and a plurality of zero-loss switches; 2 q output terminals of the q-bit decoder are connected to the control terminals of the zero-loss switches, including For one-to-one connection, one-to-many connection, and many-to-one connection, the input end of the zero-loss switch is used as the input end of the zero-loss multi-way switch.
技术特征8：一种包括技术特征4所述双向零损开关的双向零损多路开关，其特征在于，Technical feature 8: a bidirectional zero-loss multi-channel switch including the bidirectional zero-loss switch described in technical feature 4, characterized in that,
一个q位的双向零损多路开关，包括一个q位译码器和多个双向零损开关；所述q位译码器的2 q个输出端与所述双向零损开关的控制端进行连接，包括一对一的连接、一对多的连接、多对一的连接，所述零损开关的输入端作为所述零损多路开关的输入端。 A q-bit bidirectional zero-loss multi-channel switch includes a q-bit decoder and a plurality of bidirectional zero-loss switches; 2 q output terminals of the q-bit decoder are connected to the control terminals of the bidirectional zero-loss switch The connection includes a one-to-one connection, a one-to-many connection, and a many-to-one connection, and the input end of the zero-loss switch is used as the input end of the zero-loss multi-way switch.
技术特征9：一种包括技术特征3所述零损开关的桥电位ADC，其特征在于，Technical feature 9: a bridge potential ADC including the zero-loss switch described in technical feature 3, characterized in that,
一个n位零损开关桥电位ADC包括m个子级SADC，m个子级(SADC α、SADC β、SADC γ、…、SADC m)的位数分别为(q α、q β、q γ、…、q m)，其中，m为末级，n＝q α+q β+q γ+…+q m； An n -bit zero-loss switching bridge potential ADC includes m sub - stages SADC . q m ), wherein, m is the final stage, n=q α +q β +q γ +…+q m ;
所述第λ级子级SADC是一个q λ位SADC λ，包括一个q λ位并行式ADCB λ、一个桥电位V λE的提取模块、一个中间模块， The λ-th sub-level SADC is a q λ bit SADC λ , including a q λ bit parallel ADCB λ , a bridge potential V λE extraction module, and an intermediate module,
所述中间模块包括采样保持器T/H、求和器∑ λ、放大器AM λ； The intermediate module includes a sample-and-hold T/H, a summer Σ λ , an amplifier AM λ ;
第λ级模拟信号电压U λy连接采样保持器T/H处理后成为稳定信号电压U λZ，U λZ分支两路，一路送入求和器∑ λ的被减数端，一路送入所述比较器链充当各个比较器的同相输入端信号，与各个接在比较器反相输入端的基准电位进行比较； The λ-level analog signal voltage U λy is connected to the sample holder T/H and processed to become a stable signal voltage U λZ . U λZ is divided into two branches, one of which is sent to the minuend terminal of the summer ∑ λ , and the other is sent to the comparison The chain acts as the non-inverting input signal of each comparator, and compares it with the reference potential connected to the inverting input of each comparator;
所述q λ位并行式ADCB λ包括一个q λ位基准电阻链(R λ0、R λ1、R λ2、…、R λ(Qλ-1))、一个q λ位比较器链(C λ0、C λ1、C λ2、…、C λ(Qλ-1)，其中C λ0可以省略)、一个q λ位编码器，所述基准电位链各电阻相等，形成Q λ个等间距ΔV的基准电位点(V λ0、V λ1、V λ2、…、V λ(Qλ-1))； The q λ -bit parallel ADCB λ includes a q λ -bit reference resistor chain (R λ0 , R λ1 , R λ2 , ..., R λ(Qλ-1) ), a q λ -bit comparator chain (C λ0 , C λ1 , C λ2 ,..., C λ(Qλ-1) , where C λ0 can be omitted), a q λ bit encoder, each resistance of the reference potential chain is equal to form Q λ reference potential points with equal intervals ΔV ( V λ0 , V λ1 , V λ2 , ..., V λ(Qλ-1) );
所述桥电位V λE的提取模块包括一个由Q λ个双控零损开关(PS λ0、PS λ1、PS λ2、…、PS λ(Qλ-1))组成的q λ位双控零损开关链，所述桥电位V λE的数学表达式为：V λE＝INT(U λZ/ΔV)*ΔV The extraction module of the bridge potential V λE includes a q λ -bit dual-control zero-loss switch composed of Q λ double-control zero-loss switches (PS λ0 , PS λ1 , PS λ2 , ..., PS λ(Qλ-1) ) chain, the mathematical expression of the bridge potential V λE is: V λE =INT(U λZ /ΔV)*ΔV
所述比较器链各个比较器的反相输入端、所述双控零损开关链的各个双控零损开关的输入端、所述基准电阻链的各个基准电位点，三者的各个端或点按照下标的对应关系进行连接；The inverting input terminals of each comparator of the comparator chain, the input terminals of each dual-control zero-loss switch of the dual-control zero-loss switch chain, each reference potential point of the reference resistance chain, each terminal of the three or The points are connected according to the corresponding relationship of subscripts;
所述双控零损开关PS λe的下方为低断高通端+I λe，上方为高断低通端-I λe，由PS λ0的-I λ0连接PS λ1的+I λ1、PS λ1的-I λ1连接PS λ2的+I λ2、PS λ2的-I λ2连接PS λ3的+I λ3、…、以此类推，(PS λ0、PS λ1、PS λ2、…、PS λ(Qλ-1))形成Q-1个连接点，每个连接点用低断高通端标出，形成双控零损开关PS λe的控制端链(+I λ1、+I λ2、…、+I λ(Qλ-1))，并且将PS λ0的+I λ0固定接1，PS λ(Qλ-1)的-I λ(Qλ-1)固定接0； The lower part of the dual-control zero-loss switch PS λe is the low-break high-pass terminal +I λe , and the upper part is the high-break low-pass terminal -I λe , and -I λ0 of PS λ0 is connected to +I λ1 of PS λ1 and - I λ1 is connected to +I λ2 of PS λ2 , -I λ2 of PS λ2 is connected to +I λ3 of PS λ3 , ..., and so on, (PS λ0 , PS λ1 , PS λ2 , ..., PS λ(Qλ-1) ) Form Q-1 connection points, and each connection point is marked with a low-break high-pass end, forming a control terminal chain (+I λ1 , +I λ2 , ..., +I λ(Qλ- 1 ) ), and connect +I λ0 of PS λ0 to 1, and -I λ(Qλ-1) of PS λ(Qλ-1) to 0;
比较器链的输出端控制字(I λ1、I λ2、…、I λ(Qλ-1))有两个输出方向，一个输出方向是编码器，通过编码器得到第λ级ADCB λ的 qλ位数字信号，实现第λ级的AD转换；另一个输出方向是作为控制字连接到对应下标的所述双控零损开关控制端(+I λ1、+I λ2、…、+I λ(Qλ-1))，所述双控零损开关的各个输出端都连接到公共输出端BUS λ进而连接到求和器∑ λ的减数端； The output control word of the comparator chain (I λ1 , I λ2 ,..., I λ(Qλ-1) ) has two output directions, one output direction is the encoder, and the qλ bit of the λth stage ADCB λ is obtained through the encoder digital signal to realize the AD conversion of the λth stage; the other output direction is to be connected as a control word to the control terminal of the double-controlled zero-loss switch corresponding to the subscript (+I λ1 , +I λ2 ,..., +I λ(Qλ- 1) ), each output end of the double-controlled zero-loss switch is connected to the common output port BUS λ and then connected to the subtrahend end of the summator Σ λ ;
当所述q λ位并行式ADCB λ得到模拟信号电压U λZ时，U λZ值必处于两个基准电位之间，其中，将下面这个基准电位定义为桥电位V λE，桥电位V λE是不大于并最接近于U λZ的基准电位，其数学表达式为：V λE＝INT(U λZ/ΔV)*ΔV； When the q λ -bit parallel ADCB λ obtains the analog signal voltage U λZ , the value of U λZ must be between two reference potentials, wherein, the following reference potential is defined as the bridge potential V λE , and the bridge potential V λE is not The reference potential that is greater than and closest to U λZ , its mathematical expression is: V λE = INT(U λZ /ΔV)*ΔV;
桥电位V λE及以下的基准电位点所对应下标的比较器输出值等于1，大于桥电位V λE值的基准电位点所对应下标的比较器输出值等于0，即，以V λE分界点，V λE及下面的比较器输出值是一串1，V λE上面的比较器输出值是一串0；只有PS λE处于一串1变成一串0的临界点，所述双控零损开关PS λe的导通条件为：低断高通端+I λe＝1且高断低通端-I λe＝0；即，只有PS λE满足+I λE＝1且-I λE＝0的导通条件，其它的双控零损开关，要么上下控制字全1，要么上下控制字全0，不满足导通条件；PS λE导通将桥 电位V λE取出并送入公共输出端BUS λ，进而送入求和器∑ λ减数端，求和器∑ λ进行U λZ-V λE运算后得到一个小于ΔV的值，命名为尾数电压U λX，然后通过放大器AM λ放大2 qλ倍，将U λX扩大到(-V REF～V REF)的电压范围，变成下一级SADC λ+1的输入信号U (λ+1)y； The comparator output value corresponding to the subscript of the bridge potential V λE and below the reference potential point is equal to 1, and the comparator output value of the subscript corresponding to the reference potential point greater than the bridge potential V λE value is equal to 0, that is, with the V λE demarcation point, The output value of the comparator below V λE is a string of 1s, and the output value of the comparator above V λE is a string of 0s; only PS λE is at the critical point where a string of 1s becomes a string of 0s, and the dual-control zero-loss switch The conduction condition of PS λe is: low-off high-pass terminal +I λe =1 and high-off low-pass terminal -I λe =0; that is, only PS λE satisfies the conduction conditions of +I λE =1 and -I λE =0 , other dual-control zero-loss switches, either the upper and lower control words are all 1, or the upper and lower control words are all 0, which does not meet the conduction condition; PS λE conduction takes out the bridge potential V λE and sends it to the common output terminal BUS λ Enter the summator ∑ λ subtrahend end, and the summator ∑ λ performs U λZ -V λE operation to obtain a value less than ΔV, which is named as the mantissa voltage U λX , and then amplified by 2 qλ times through the amplifier AM λ to convert U λX Expand to the voltage range of (-V REF ~V REF ), and become the input signal U (λ+1)y of the next stage SADC λ+1 ;
这样，从α级开始，一级接一级往后转换，最后得到一个n位的数字信号。In this way, starting from the alpha level, one level after another is converted backwards, and finally an n-bit digital signal is obtained.
技术特征10：一种包括技术特征9所述零损开关的桥电位ADC，其特征在于，Technical feature 10: a bridge potential ADC including the zero-loss switch described in technical feature 9, characterized in that,
所述桥电位V λE的提取模块包括一个q λ位零损多路开关；所述q λ位零损多路开关包括一个q λ位译码器、一个零损开关链(S λ0、S λ1、S λ2、…、S λ(Qλ-1))，其各个零损开关输出端连接到公共输出端BUS λ； The extraction module of the bridge potential V λE includes a q λ bit zero-loss multiplex switch; the q λ bit zero-loss multiplex switch includes a q λ bit decoder, a zero-loss switch chain (S λ0 , S λ1 , S λ2 ,..., S λ(Qλ-1) ), each zero-loss switch output terminal is connected to the common output terminal BUS λ ;
所述零损开关链的各个零损开关的输入端、所述比较器链各个比较器的反相输入端、所述基准电阻链的各个基准电位点，三者的各个端或点按照下标的对应关系进行连接；The input terminals of each zero-loss switch of the zero-loss switch chain, the inverting input terminals of each comparator of the comparator chain, and each reference potential point of the reference resistance chain, each terminal or point of the three is according to the subscript Corresponding relationship to connect;
技术特征11：一种包括技术特征7所述零损多路开关的桥电位式DAC，其特征在于，Technical feature 11: a bridge potential DAC including the zero-loss multi-way switch described in technical feature 7, characterized in that,
一个n位DAC由m个子级SDAC和一个比例求和运放构成，m个子级SDAC(α级、β级、γ级、…、m级)的位数分别为(q α、q β、q γ、…、q m)，其中，m为末级，n＝q α+q β+q γ+…+q m；所述比例求和运放中，(α级、β级、γ级、…、m级)的权计算器(AW α、AW β、AW γ、…、AW m)，权计算器放大倍数分别为(AW α、AW β、AW γ、…、AW m)，以AW α为基准，令 An n-bit DAC is composed of m sub-level SDACs and a proportional summation op amp. The number of bits of m sub-level SDACs (α level, β level, γ level, ..., m level) are (q α , q β , q γ ,...,q m ), wherein, m is the final stage, n=q α +q β +q γ +...+q m ; in the proportional summation operational amplifier, (α level, β level, γ level, ..., level m) weight calculator (AW α , AW β , AW γ , ..., AW m ), the magnifications of the weight calculator are (AW α , AW β , AW γ , ..., AW m ), with AW α as the benchmark, let
AW β/AW α＝1/2 qα、AW γ/AW α＝1/2 qα+qβ、…、AW m/AW α＝1/2 qα+qβ+…+q(m-1) AW β /AW α =1/2 qα , AW γ /AW α =1/2 qα+qβ ,…, AW m /AW α =1/2 qα+qβ+…+q(m-1)
所述第λ子级SDAC λ，其位数为q λ，SDAC λ包含一个q λ位多路开关和一个q λ位基准电阻链；所述基准电位链各电阻相等，共2 qλ个等间距的基准电位点(V λ0、V λ1、V λ2、…、V λ(Qλ-1))；所述多路开关由一个q λ位译码器和一个q λ位零损开关链(S λ0、S λ1、S λ2、…、S λ(Qλ-1))构成，各个零损开关的输入端按顺序对应下标连接到所述基准电位点，所有零损开关的输出端连接到第λ级公共输出端BUS λ； The number of digits of the λth sub-stage SDAC λ is q λ , and SDAC λ includes a q λ bit multiplexer and a q λ bit reference resistor chain; the resistances of the reference potential chain are equal, a total of 2 qλ equidistant reference potential points (V λ0 , V λ1 , V λ2 ,..., V λ(Qλ-1) ); the multi-way switch consists of a q λ bit decoder and a q λ bit zero-loss switch chain (S λ0 . _ _ Level common output terminal BUS λ ;
各级SDAC λ的(BUS α、BUS β、BUS γ、……、BUS λ)分别送入对应下标的权计算器(AW α、AW β、AW γ、…、AW m)，各个权计算器汇聚到求和器∑ λ进行求和，实现DA转换 The SDAC λ at all levels (BUS α , BUS β , BUS γ , ..., BUS λ ) are respectively sent to the weight calculators (AW α , AW β , AW γ , ..., AW m ) corresponding to the subscripts, each weight calculator Converge to the summer ∑ λ for summing to realize DA conversion
当SDAC λ接收到一个数字信号时，所述译码器会在所述2 qλ个零损开关中唯一的选通一个零损开关，该零损开关将所连接的基准电位取出，该基准电位是数字信号和模拟信号的桥梁，命名为桥电位V λE，桥电位V λE被取出后送入所述公共输出端，实现该子级SDAC λ的DA转换； When SDAC λ receives a digital signal, the decoder will uniquely select a zero-loss switch among the 2 qλ zero-loss switches, and the zero-loss switch will take out the connected reference potential, and the reference potential It is a bridge between digital signal and analog signal, named as bridge potential V λE , the bridge potential V λE is taken out and then sent to the common output terminal to realize DA conversion of the sub-stage SDAC λ ;
用这种方法，获得(α级、β级、γ级、…、m级)的桥电位分别为(V αE、V βE、V γE、……、V λE)，各级桥电位的权是不同的，在对各级桥电位进行权运算后相加，就得到了DA转换的总输出电压V out；权计算以及相加的电路可以采用比例求和运放； In this way, the bridge potentials obtained (α-level, β-level, γ-level, ..., m-level) are respectively (V αE , V βE , V γE , ..., V λE ), and the weights of the bridge potentials at each level are Differently, the total output voltage V out of the DA conversion is obtained after the weighted calculation of the bridge potentials at all levels is added; the weighted calculation and the added circuit can use proportional summation op amps;
V out＝V αE+AW β*V βE+AW γ*V γE+...+AW m*V λm＝V αE+V βE/2 qα+V γE/2 qα+qβ+...+V λm/2 qα+qβ+…+q(m-1)； V out ＝V αE +AW β *V βE +AW γ *V γE +...+AW m *V λm ＝V αE +V βE /2 qα +V γE /2 qα+qβ +...+V λm /2 qα+qβ+…+q(m-1) ;
附图说明Description of drawings
采用业内公知的符号和符号图标记对象，没有特别需要时不逐个说明，包括：电阻(R)、电位(V)、信号电压(u)、二极管(D)、三极管(T)、运放(A)、开关(S)、控制字(I)；Use well-known symbols and symbol diagrams in the industry to mark objects, and do not explain one by one if there is no special need, including: resistance (R), potential (V), signal voltage (u), diode (D), transistor (T), operational amplifier ( A), switch (S), control word (I);
沿用以上命名规则，本文增加的符号有：单控制字开关运放命名为(SA)；双(Pair)控制字开关运放命名为(PA)；单控制字开关命名为(AS)；低断高通式开关命名为(HS)；高断低通式开关命名为(LS)；双控制字开关命名为(PS)；Following the above naming rules, the symbols added in this article are: the single control word switch op amp is named (SA); the double (Pair) control word switch op amp is named (PA); the single control word switch is named (AS); The high-pass switch is named (HS); the high-break low-pass switch is named (LS); the double control word switch is named (PS);
前面已经说明过的符号没有特别需要时不再说明；The symbols that have been explained above will not be explained if there is no special need;
所有符号可以带下标，下标不改变符号性质；All symbols can be subscripted, and the subscript does not change the nature of the symbol;
I λe、LS λe、V λe等符号，下标λ和e是通配符，表示第λ级的第e阶的对象； I λe , LS λe , V λe and other symbols, the subscripts λ and e are wildcards, which represent the objects of the e-th order of the λth level;
图1.1——有输出级细节的运放框图；10-输入级；11-中间级；12-输出级；A a-运放；u aN-反相输入端信号；u aP-同相输入端信号；u a0-输出信号；+V CC-电源正极；-V CC；-电源负极；T a1-NPN输出管；T a2-PNP输出管；V a1-T a1基极电位；V a2-T a2基极电位；R a1-T a1偏置电阻；R a2-T a2偏置电阻；D a1-T a1偏置二极管；D a2-T a2偏置二极管； Figure 1.1 - Op amp block diagram with output stage details; 10 - input stage; 11 - intermediate stage; 12 - output stage; A a - op amp; u aN - inverting input signal; u aP - noninverting input signal ;u a0 - output signal; +V CC - positive pole of power supply; -V CC ; - negative pole of power supply; T a1 -NPN output tube; T a2 -PNP output tube; V a1 -T a1 base potential; V a2 -T a2 Base potential; R a1 -T a1 bias resistor; R a2 -T a2 bias resistor; D a1 -T a1 bias diode; D a2 -T a2 bias diode;
图1.2——运放框图；Figure 1.2 - block diagram of the op amp;
图1.3——运放符号图；Figure 1.3 - op amp symbol diagram;
图2.1-有输出级和控制级细节的单控制字开关运放框图；10-输入级；11-中间级；12-输出级；13-单控控制级；SA-开关运放；u bN-反相输入端信号；u bP-同相输入端信号；u b0-输出信号；T b1-NPN输出管；T b2-PNP输出管；V b1-T b1基极电位；V b2-T b2基极电位；R b1-T b1偏置电阻；R b2-T b2偏置电阻；D b1-T b1偏置二极管；D b2-T b2偏置二极管；T b3-第一PNP控制管；T b4-第二PNP控制管；I +-低断高通； Figure 2.1 - Block diagram of a single control word switching op amp with output stage and control stage details; 10 - input stage; 11 - intermediate stage; 12 - output stage; 13 - single control control stage; SA - switching op amp; u bN - Inverting input signal; u bP - non-inverting input signal; u b0 - output signal; T b1 - NPN output tube; T b2 - PNP output tube; V b1 -T b1 base potential; V b2 -T b2 base Potential; R b1 -T b1 bias resistor; R b2 -T b2 bias resistor; D b1 -T b1 bias diode; D b2 -T b2 bias diode; T b3 - the first PNP control tube; T b4 - The second PNP control tube; I + - low off high pass;
图2.2-单控制字开关运放框图；SA-开关运放；I +-低断高通； Figure 2.2-Block diagram of single control word switching op amp; SA-switching op amp; I + -low off and high pass;
图2.3-单控制字开关运放符号图；SA-开关运放；I +-低断高通； Figure 2.3-Single control word switching op amp symbol diagram; SA-switching op amp; I + -low off high pass;
图2.4-单控制字开关运放连接成零损开关示意图；SA-开关运放；U bP-输入信号；U b0-输出信号；I +-低断高通； Figure 2.4 - Schematic diagram of a single control word switching op amp connected into a zero-loss switch; SA-switching op amp; U bP -input signal; U b0 -output signal; I + -low-off high-pass;
图2.5-单控零损开关符号图；AS-单控零损开关；I-控制字；Figure 2.5-Symbol diagram of single-control zero-loss switch; AS-single-control zero-loss switch; I-control word;
图2.6-低断高通零损开关符号图；HS-低断高通零损开关；I +-低断高通； Figure 2.6 - Symbol diagram of low-break high-pass zero-loss switch; HS-low-break high-pass zero-loss switch; I + - low-break high-pass;
图2.7-高断低通零损开关符号图；LS-高断低通零损开关；I --高断低通； Figure 2.7-High-break low-pass zero-loss switch symbol diagram; LS-high-break low-pass zero-loss switch; I - - high-break low-pass;
图2.8-双向零损开关符号图；Figure 2.8 - Bidirectional zero-loss switch symbol diagram;
图3.1-有输出级和控制级细节的单控制字开关运放框图；10-输入级；11-中间级；12-输出级；14-双控控制级；PA-双控开关运放；u cN-反相输入端信号；u cP-同相输入端信号；u c0-输 出信号；T c1-NPN输出管；T c2-PNP输出管；V c1-T c1基极电位；V c2-T c2基极电位；R c1-T c1偏置电阻；R c2-T c2偏置电阻；D c1-T c1偏置二极管；D c2-T c2偏置二极管；T c3和T c4-第一和第二PNP控制管(针对运放低断高通管)；T c5和T c6-第一和第二NPN控制管；I +-低断高通；I --高断低通； Figure 3.1 - Block diagram of single control word switching op amp with output stage and control stage details; 10 - input stage; 11 - intermediate stage; 12 - output stage; 14 - dual control control stage; PA - dual control switching op amp; u cN - inverting input signal; u cP - non-inverting input signal; u c0 - output signal; T c1 - NPN output tube; T c2 - PNP output tube; V c1 -T c1 base potential; V c2 -T c2 Base potential; R c1 - T c1 bias resistor; R c2 - T c2 bias resistor; D c1 - T c1 bias diode; D c2 - T c2 bias diode; T c3 and T c4 - first and second Two PNP control tubes (for op amp low-off high-pass tubes); T c5 and T c6 - the first and second NPN control tubes; I + - low-off high-pass; I - - high-off low-pass;
图3.2-双控制字开关运放框图；PA-双控开关运放；I +-低断高通；I --高断低通； Figure 3.2-Block diagram of dual control word switch op amp; PA-dual control switch op amp; I + - low off and high pass; I - - high off and low pass;
图3.3-双控制字开关运放符号图；PA-双控开关运放；I +-低断高通；I --高断低通； Figure 3.3-Symbol diagram of dual control word switching op amp; PA-dual control switching op amp; I + - low off and high pass; I - - high off and low pass;
图3.4-双控制字开关运放连接成零损开关示意图；PA-双控开关运放；I +-低断高通；I --高断低通；U cP-输入信号；U c0-输出信号； Figure 3.4-Schematic diagram of double control word switch op amp connected into a zero loss switch; PA-dual control switch op amp; I + - low-off high-pass; I - - high-off low-pass; U cP - input signal; U c0 - output signal ;
图3.5-双控零损开关符号图；PS-双控零损开关；I +-低断高通；I --高断低通； Figure 3.5-Symbol diagram of dual-control zero-loss switch; PS-double-control zero-loss switch; I + - low-off high-pass; I - - high-off low-pass;
图4.1-反馈型采样保持器；SA 1-开关运放；V in-输入端；A 1-输出放大器；C 1-采样电容；CLK-时钟脉冲；V out-输出信号； Figure 4.1-feedback sample-and-hold device; SA 1 -switching op amp; V in -input terminal; A 1 -output amplifier; C 1 -sampling capacitor; CLK-clock pulse; V out -output signal;
图4.2-串联型采样保持器；串联型采样保持器(图4.2)，AS 2-零损开关；V in-输入端，；A 2-输出放大器；C 2-采样电容；；CLK-时钟脉冲；V out-输出信号； Figure 4.2 - Series Sample and Holder; Series Sample and Holder (Figure 4.2), AS 2 - Zero Loss Switch; V in - Input Terminal,; A 2 - Output Amplifier; C 2 - Sampling Capacitor; CLK - Clock Pulse ; V out - output signal;
图4.3-采样保持器符号图；Figure 4.3 - Sample and hold symbol diagram;
图5.1-第λ级SDAC(子级DAC)；虚线框SDAC λ-第λ级SDAC；虚线框MS λ-第λ级零损多路开关；虚线框LSC λ-第λ级低开关链；虚线框RC λ-第λ级基准电阻链；YM λ-第λ级译码器；(d λ2d λ1d λ 0)-数字输入信号；(I λ7～I λ0)-第λ级译码器输出的控制字；(LS λ7～LS λ0)-低开关，组成低开关链；BUS λ-第λ级开关链或多路开关的公共端；d α2d α1d α0-输入信号；(R λ7～R λ0)-第λ级基准电阻链；(V λ7～V λ0)-第λ级基准电压链；V λE～第λ级桥电位； Figure 5.1 - λth stage SDAC (sub-stage DAC); dashed box SDAC λ - λth stage SDAC; dotted box MS λ - λth stage zero-loss multiplex switch; dashed box LSC λ - λth stage low switch chain; dashed line Frame RC λ - reference resistance chain of λth stage; YM λ - λth stage decoder; (d λ2 d λ1 d λ 0 ) - digital input signal; (I λ7 ~ I λ0 ) - output of λth stage decoder control word; (LS λ7 ～LS λ0 )-low switch, forming a low switch chain; BUS λ -the common end of the λ-level switch chain or multi-way switch; d α2 d α1 d α0 -input signal; (R λ7 ～ R λ0 )-the reference resistance chain of the λth stage; (V λ7 ～V λ0 )-the reference voltage chain of the λth stage; V λE ～the bridge potential of the λth stage;
图5.2-第λ级双向多路开关；符号与图5.1符号相同，增加了一组(IO λ7～IO λ0)第λ级输入输出端； Figure 5.2 - The λth stage bidirectional multiplexer; the symbols are the same as those in Figure 5.1, with a set of (IO λ7 ~IO λ0 ) λth stage input and output ports added;
图6-桥电位DAC；符号与图5.1符号相同，增加的符号有：AW λ-第λ级的权重运算器；∑-求和器；V Σ-求和电压； Figure 6 - bridge potential DAC; the symbols are the same as those in Figure 5.1, and the symbols added are: AW λ - the weight operator of the λ stage; Σ - summator; V Σ - summation voltage;
图6.1-权重运算器的结构之一，电路的结构是不胜枚举的；该结构采用反向比例运放是一个很好的选择，AW λ-权重运算器的符号及放大倍数；U out-输出信号；U in-输入信号；R F-反馈电阻；R X-反相输入端电阻；AW λ＝U out/U in＝-R F/R X＝-1/2 (λ-1)q，根据需要确定电阻值； Figure 6.1 - One of the structures of the weight operator, the structure of the circuit is too numerous to enumerate; it is a good choice to use an inverse proportional op amp in this structure, AW λ - the symbol and magnification of the weight operator; U out - Output signal; U in - input signal; R F - feedback resistance; R X - inverting input resistance; AW λ ＝U out /U in ＝-R F /R X ＝-1/2 (λ-1)q , determine the resistance value as needed;
图6.2-权重运算器符号图；符号同上；Figure 6.2 - Symbol diagram of the weight operator; the symbols are the same as above;
图7.1-第λ级MS式m*3bit桥电位ADC框图；前面没出现过的符号有：SADC1 λ-第λ级MS式m*3bit桥电位ADC；ADM λ-第λ级并行式ADC；(C λ7～C λ0)-第λ级比较器链；ENC λ-第λ级编码器；U λy-第λ级输入模拟信号；U λ(y+1)-第λ级输出模拟信号；U λz-采样保持后的模拟信号；V λE-桥电位；U λX-提取桥电位后的尾数电压； Figure 7.1 - block diagram of the λth stage MS type m*3bit bridge potential ADC; the symbols that have not appeared before are: SADC1 λ - the λth stage MS type m*3bit bridge potential ADC; ADM λ - the λth stage parallel ADC; ( C λ7 ～C λ0 )-the comparator chain of the λth stage; ENC λ —the λth stage encoder; U λy —the input analog signal of the λth stage; U λ(y+1) —the output analog signal of the λth stage; U λz - analog signal after sampling and holding; V λE - bridge potential; U λX - mantissa voltage after extracting bridge potential;
图7.2-第λ级PSC式m*3bit桥电位ADC框图；前面没出现过的符号有：SADC2 λ-第λ级PSC式m*3bit桥电位ADC；PSC λ-第λ级关/开链；(PS λ7～PS λ0)-第λ级关/开； Figure 7.2 - block diagram of the λth stage PSC type m*3bit bridge potential ADC; the symbols that have not appeared before are: SADC2 λ - the λth stage PSC type m*3bit bridge potential ADC; PSC λ - the λth stage off/on chain; (PS λ7 ～PS λ0 )-the λth stage is off/on;
图7.3-PSC式m*3bit桥电位ADC的PS；这里单独画出是注意低断高通在下面，高断低通在上面；Figure 7.3-PS of the PSC-type m*3bit bridge potential ADC; the separate drawing here is to note that the low-off high-pass is below, and the high-off low-pass is on the top;
实施例Example
实施例1：开关运放Example 1: Switching op amp
在三个级基础上增加一个控制级，采用控制字信号I＝0/1(即0或1)对控制级进行控制，进而控制输出管的通断，构成一种可以关断的运放，命名为“开关运放”；控制级中包含一对或多对三极管，控制级的三极管自身被控制字0/1控制通断(通断也写成ON/OFF)，它又控制输出管的通断，所以这些三极管命名为“控制管”；Add a control stage on the basis of the three stages, use the control word signal I=0/1 (that is, 0 or 1) to control the control stage, and then control the on-off of the output tube to form an operational amplifier that can be turned off. It is named "switching op amp"; the control stage contains one or more pairs of triodes, and the triodes of the control stage themselves are controlled by the control word 0/1 (on/off is also written as ON/OFF), and it controls the on-off of the output tube. off, so these triodes are named "control tubes";
控制级由一对控制管或多对控制管构成，注意到一对输出管是NPN/PNP三极管各一个，而一对控制管是两个NPN管或两个PNP管，一对NPN控制管命名为“NPN控制器”，一对PNP控制管命名为“PNP控制器”；一对控制管中，一个控制管的集电极与射极连接在NPN输出管的基极与-V CC之间，另一个控制管的集电极与射极连接在PNP输出管的基极与+V CC之间，一对控制管的基极电位被同一个控制字所控制，通过控制字信号I＝0/1决定了控制管的通断，进而，控制管的通断决定了输出管的通断，很明显，输出管的通断就是开关运放的通断；所以，控制字信号决定了开关运放处于工作态还是高阻态；增加了控制级的运放简称“开关运放”。 The control stage is composed of a pair of control tubes or multiple pairs of control tubes. Note that a pair of output tubes are NPN/PNP transistors, and a pair of control tubes are two NPN tubes or two PNP tubes. A pair of NPN control tubes is named Named as "NPN controller", a pair of PNP control tubes is named "PNP controller"; in a pair of control tubes, the collector and emitter of one control tube are connected between the base of the NPN output tube and -V CC , The collector and emitter of the other control tube are connected between the base of the PNP output tube and +V CC , the base potential of a pair of control tubes is controlled by the same control word, through the control word signal I=0/1 It determines the on-off of the control tube, and then, the on-off of the control tube determines the on-off of the output tube. Obviously, the on-off of the output tube is the on-off of the switching amplifier; therefore, the control word signal determines the switching op-amp in The working state is still in the high-impedance state; the op amp with the added control stage is referred to as "switching op amp".
实施例2：由开关运放构造的零损开关Example 2: Zero-loss switch constructed from a switching op amp
将运放的输出端与反相输入端连通，使得反相输入端的电位＝输出电位，因为同相输入端与反相输入端之间为“虚短”，所以，同相输入端的电位＝反相输入端的电位＝输出电位，即，输出电位＝同相输入端的输入电位，形成电压跟随，运放就连接成了电压跟随器，简称跟随器；约定全文运放包括跟随器；Connect the output terminal of the op amp to the inverting input terminal, so that the potential of the inverting input terminal = output potential, because there is a "virtual short" between the non-inverting input terminal and the inverting input terminal, so the potential of the non-inverting input terminal = inverting input The potential of the terminal = the output potential, that is, the output potential = the input potential of the non-inverting input terminal, forming a voltage follower, and the op amp is connected as a voltage follower, referred to as the follower; it is agreed that the full text of the op amp includes the follower;
将开关运放中的运放连接成跟随器，开关运放就成了开关式跟随器，因为从工程上说，跟随器的信号损失可以忽略，所以开关式跟随器是一种零损耗模拟开关，特别命名为“零损开关”；零损开关是开关运放的一种应用，本文所述的所有开关运放都包含零损开关；Connect the op amp in the switching op amp into a follower, and the switching op amp becomes a switching follower. From an engineering point of view, the signal loss of the follower can be ignored, so the switching follower is a zero-loss analog switch. , specially named "zero-loss switching"; zero-loss switching is an application of switching op amps, and all switching op amps described in this article include zero-loss switching;
笔者此前发明过一种零损开关，这是将控制管置于运放的电源通路上，通过控制运放的电源通断来控制运放的ON/OFF，它有两大缺点：第一是控制管要挤占运放的电压，使运放的工作电压降低，影响运放性能；第二是运放在断电和通电的过程中，耗费时间较长，难以实现高频响应；本文提出的零损开关克服了这两个缺陷，本文所述的零损开关不是指以前发明的零损开关，而是这次发明的零损开关；The author has invented a zero-loss switch before, which is to place the control tube on the power path of the op amp, and control the ON/OFF of the op amp by controlling the power on and off of the op amp. It has two major disadvantages: the first is The control tube will occupy the voltage of the op amp, which will reduce the operating voltage of the op amp and affect the performance of the op amp. The zero-loss switch overcomes these two defects. The zero-loss switch mentioned in this article does not refer to the zero-loss switch invented before, but the zero-loss switch invented this time;
实施例3：一种单控制字开关运放SAEmbodiment 3: A single control word switch operational amplifier SA
控制级可以由一对控制管构成，命名为单字控制级，对应的运放命名为单控制字开关运放，对应的零损开关命名为“单控零损开关”；控制级也可以是由多对控制管连接成“与、或、非”的逻辑电路，形成由多个控制字进行控制的复杂控制级，命名为多字控制级，对应的运放命名为多控制字开关运放；复杂的控制关系还可以由单控制字开关运放加外置式逻辑电路构成；The control stage can be composed of a pair of control tubes, named single word control stage, the corresponding op amp is named single control word switch op amp, and the corresponding zero loss switch is named "single control zero loss switch"; the control stage can also be composed of Multiple pairs of control tubes are connected to form a logic circuit of "AND, OR, NOT" to form a complex control level controlled by multiple control words, which is named multi-word control level, and the corresponding operational amplifier is named multi-control word switching op amp; The complex control relationship can also be composed of a single control word switch op amp plus an external logic circuit;
单控制字开关运放包括“低断高通式开关运放”和“高断低通式开关运放”；Single control word switching op amp includes "low-off high-pass switching op amp" and "high-off low-pass switching op amp";
图3.1中，去掉NPN控制管，就是图2.1，只有一对PNP控制管T b3和T b4，命名为“PNP控制器”；控制管T b4的射极与集电极分别连接于NPN输出管T b1的基极与-V CC，另一个控制管T b3的集电极与射极分别连接于PNP输出管T b2的基极与+V CC，这对控制管的基极电位被同一个控制字I +所控制；当控制字I +＝0时，这对控制管ON，控制管T b4将NPN输出管T b1的基极与-V CC之间接通，使该NPN输出管OFF；控制管T b3将PNP输出管T b2的基极与+V CC之间接通，使该PNP输出管OFF，其结果是使两个输出管都处于截止态，即，使运放的输出通路处于高阻态，实现了运放OFF的操作，所以，I +＝0就是关断运放的信号；当控制字I +＝1时这对控制管OFF，控制管对两个输出管不施加影响，使运放处于正常工作态，实现了运放ON的操作，所以，I +＝1(高电平)就是开通运放的信号；因为I +＝高电平时使运放为通态，所以将I的下标设置为“+”，I +命名为“低断高通”，必然的，低断高通I +＝低电平时使运放OFF；综合起来就是：当低断高通I +＝1(高电平)时，两个PNP控制管OFF，使被它们所控制的开关运放处于运算放大状态，将这种开关运放称为“控制字高电平时使运放处于ON态的开关运放”，简称为“低断高通式开关运放”；将运放连接成跟随器，低断高通式开关运放就成了“低断高通式零损开关”，所以低断高通式开关运放包括了“低断高通式零损开关”；低断高通式零损开关简称“高开关(HS，即，High Switch)”； In Figure 3.1, the NPN control tube is removed, which is Figure 2.1, there is only a pair of PNP control tubes T b3 and T b4 , named "PNP controller"; the emitter and collector of the control tube T b4 are respectively connected to the NPN output tube T The base of b1 is connected to -V CC , the collector and emitter of another control transistor T b3 are respectively connected to the base of PNP output transistor T b2 and +V CC , the base potential of the pair of control transistors is controlled by the same control word Controlled by I + ; when the control word I + = 0, this pair of control tubes is ON, and the control tube T b4 connects the base of the NPN output tube T b1 to -V CC , making the NPN output tube OFF; the control tube T b3 connects the base of the PNP output transistor T b2 to +V CC , and turns off the PNP output transistor. As a result, both output transistors are in a cut-off state, that is, the output path of the operational amplifier is in a high-impedance state. state, realizes the operation of the operational amplifier OFF, so, I + = 0 is the signal to turn off the operational amplifier; when the control word I + = 1, this pair of control tubes is OFF, and the control tube does not exert influence on the two output tubes, so that The operational amplifier is in the normal working state, and the operation of the operational amplifier ON has been realized, so I + = 1 (high level) is the signal to turn on the operational amplifier; because I + = high level, the operational amplifier is in the on-state, so the I The subscript of is set to "+", and I + is named "low-off high-pass", and necessarily, the op-amp is OFF when low-off high-pass I + = low level; in combination, it is: when low-off high-pass I + = 1 (high level), the two PNP control tubes are OFF, so that the switching amplifiers controlled by them are in the state of operational amplification. ", referred to as "low-off high-pass switching op amp"; when the op amp is connected as a follower, the low-off high-pass switching op amp becomes a "low-off high-pass zero-loss switch", so the low-off high-pass switching op amp Including "low-break high-pass zero-loss switch"; low-break high-pass zero-loss switch is referred to as "high switch (HS, that is, High Switch)";
同理，图3.1中，如果只有一对NPN控制管T c5和T c6，命名为“NPN控制器”；控制管T b6的集电极与射极分别连接于NPN输出管T c1的基极与-V CC，另一个控制管T c5的射极与集电极分别连接于PNP输出管T c2的基极与+V CC之间，这对控制管的基极电位被同一个控制字I -所控制；当控制字I -＝1时，这对控制管ON，控制管T c6将NPN输出管T c1的基极与-V CC之间接通，使该NPN输出管OFF；控制管T c5将PNP输出管T c2的基极与+V CC之间接通，使该PNP输出管OFF，其结果是使两个输出管都处于截止态，即，使运放的输出通路处于高阻态，实现了运放OFF的操作，所以，I -＝1就是关断运放的信号；当控制字I -＝0时，这对控制管OFF，控制管对两个输出管不施加影响，使运放处于正常工作态，实现了运放ON的操作，所以，I -＝0(低电平)就是开通运放的信号；因为I -＝低电平时使运放为通态，所以将I的下标设置为“-”，I -命名为“高断低通”；必然的，高断低通I -＝高电平时使运放OFF；综合起来就是： 当高断低通I -＝0(低电平)时，两个NPN控制管OFF，使被它们所控制的开关运放处于运算放大状态，将这种开关运放称为“控制字低电平时使运放处于ON态的开关运放”，简称为“高断低通式开关运放”；高断低通式开关运放包括了高断低通式零损开关，高断低通式零损开关简称“低开关(LS，即Low Switch)”； Similarly, in Figure 3.1, if there is only one pair of NPN control transistors T c5 and T c6 , it is named "NPN controller"; the collector and emitter of the control transistor T b6 are respectively connected to the base and the base of the NPN output transistor T c1 -V CC , the emitter and collector of another control transistor T c5 are respectively connected between the base of the PNP output transistor T c2 and +V CC , the base potential of the pair of control transistors is determined by the same control word I - control; when the control word I - = 1, the pair of control tubes is ON, and the control tube T c6 connects the base of the NPN output tube T c1 to -V CC to make the NPN output tube OFF; the control tube T c5 will The base of the PNP output transistor Tc2 is connected to +V CC , so that the PNP output transistor is OFF, and the result is that both output transistors are in a cut-off state, that is, the output path of the operational amplifier is in a high-impedance state, realizing Therefore, I - = 1 is the signal to turn off the op amp; when the control word I - = 0, the control tube is OFF, and the control tube has no influence on the two output tubes, so that the op amp In the normal working state, the operation of the operational amplifier ON has been realized, so I - = 0 (low level) is the signal to turn on the operational amplifier; because I - = low level, the operational amplifier is in the on-state, so the lower level of I The standard is set to "-", and I - is named "high-break low-pass"; necessarily, when high-break low-pass I - = high level, the op amp is OFF; in summary: when high-break low-pass I - = 0 ( Low level), the two NPN control tubes are OFF, so that the switching op amp controlled by them is in the state of operational amplification, and this kind of switching op amp is called "the switching op "High-break low-pass switching op amp" for short; high-break low-pass switching op amp includes high-break low-pass zero-loss switches, and high-break low-pass zero-loss switches are referred to as "low switches (LS, i.e. Low Switch)”;
实施例4：双控制字开关运放PAEmbodiment 4: Double control word switching op amp PA
如果开关运放同时包含PNP控制器和NPN控制器，则构成“双控制字开关运放”或称“双通字开关运放”(图3.1)，符号为PA(意思是：一对Pair控制字的运放A)双控制字开关运放，双控制字I +/I -有4种状态：(0/0，0/1，1/0，1/1)；参考前面的分析可知，必须满足高断低通处于低电平(I -＝0)且低断高通处于高电平(I +＝1)，即，I +/I -＝1/0，开关运放才会处于ON态，而其它三种状态，I +/I -＝(0/0，0/1，1/1)，开关运放处于OFF态；下面将看到，I +/I -＝1/0是处在一个“桥电位点”； If the switch op amp includes both a PNP controller and an NPN controller, it constitutes a "dual control word switch op amp" or "dual pass word switch op amp" (Figure 3.1), and the symbol is PA (meaning: a pair of Pair control Word op amp A) double control word switch op amp, double control word I + /I - has 4 states: (0/0, 0/1, 1/0, 1/1); It must be satisfied that the high-off low-pass is at a low level (I - = 0) and the low-off high-pass is at a high level (I + = 1), that is, I + /I - = 1/0, the switching op amp will be ON state, while the other three states, I + /I - = (0/0, 0/1, 1/1), the switching amplifier is in the OFF state; as will be seen below, I + /I - = 1/0 is At a "bridge potential point";
双通字开关运放包括了双通字零损开关，将双通字开关运放中的运放连接成电压跟随器(图3.4)，双通字开关运放就变成了双通字零损开关，简称双通字开关PS(意思是：一对Pair控制字的S)，其符号图为(图3.5和7.3)；因为“双通字开关”在本文使用频率很高，所以将双通字开关特别命名为“关/开”，“关/开”是把“开关”两个字反过来；The double-pass word switch op amp includes a double-pass word zero-loss switch, and the op-amp in the double-pass word switch op amp is connected as a voltage follower (Figure 3.4), and the double-pass word switch op amp becomes a double-pass word zero Loss switch, referred to as double-pass word switch PS (meaning: a pair of S in the Pair control word), its symbol diagram is (Figure 3.5 and 7.3); because "double-pass word switch" is used frequently in this paper, so the double-pass word switch The word switch is specially named "off/on", "off/on" is the reverse of the word "switch";
本文提出了零损开关的几种应用：零损采样保持器、零损多路开关、桥电位DAC和桥电位ADC；This paper presents several applications of zero-loss switches: zero-loss sample-and-hold, zero-loss multiplexer, bridge potential DAC, and bridge potential ADC;
实施例5：由零损开关构造成的零损开关式采样保持器，简称零损采样保持器Embodiment 5: A zero-loss switching sample-and-hold device constructed of zero-loss switches, referred to as a zero-loss sample-and-hold device
采样保持器有很多类型，主流的有反馈型采样保持器和串联型采样保持器；There are many types of sample-and-hold devices, and the mainstream ones are feedback-type sample-and-hold devices and series-type sample-and-hold devices;
某些开关运放是在I＝0时通，而某些开关运放是在I＝1时通，这里约定，无论是I＝0或I＝1，只要是使开关运放处于ON态的控制字信号命名为“ON信号”，只要是使开关运放处于OFF的控制字信号命名为“OFF信号”；Some switch op amps are turned on when I=0, and some switch op amps are turned on when I=1. It is agreed here that no matter I=0 or I=1, as long as the switch op amp is in the ON state The control word signal is named "ON signal", as long as the control word signal that makes the switch op amp OFF is named "OFF signal";
反馈型采样保持器(图4.1)，开关运放SA 1充当采样开关和输入放大器，开关运放SA 1的同相输入端充当信号输入端V in，其反相输入端与输出放大器A 1的输出端相连接，形成成大的闭环电路，采样电容C 1连接在A 1的的反相端和输出端之间，可以提高充放电速度，时钟脉冲连接到开关运放的控制字，当时钟脉冲CLK的“ON信号”到来时，开关运放SA 1导通，采样电容C 1对输入信号V in进行采样，当时钟脉冲CLK“OFF信号”到来时，开关运放关断，采样电容C 1对采样后的信号进行保持，输出放大器A 1的输出信号V out等于C 1的保持信号； Feedback sample-and-hold device (Figure 4.1), the switching operational amplifier SA 1 acts as a sampling switch and input amplifier, the non-inverting input terminal of the switching operational amplifier SA 1 serves as the signal input terminal V in , and its inverting input terminal is connected to the output of the output amplifier A 1 The terminals are connected to form a large closed-loop circuit. The sampling capacitor C1 is connected between the inverting terminal of A1 and the output terminal, which can improve the charging and discharging speed. The clock pulse is connected to the control word of the switching op amp. When the clock pulse When the "ON signal" of CLK arrives, the switch op amp SA 1 is turned on, and the sampling capacitor C 1 samples the input signal V in . When the clock pulse CLK "OFF signal" arrives, the switch op amp is turned off, and the sampling capacitor C 1 Hold the sampled signal, the output signal V out of the output amplifier A 1 is equal to the hold signal of C 1 ;
串联型采样保持器(图4.2)，零损开关AS 2充当采样开关，其输入端为V in，输出放大器A 2被连接成电压跟随器，采样电容C 2连接在AS 2的输出端与地之间，时钟脉冲连接到AS 2的控制字，当时钟脉冲CLK的“ON信号”到来时，AS 2导通，采样电容C 2对输入信号V in进行采样，当时钟脉冲CLK“OFF 信号”到来时，AS 2关断，采样电容C 2对采样后的信号进行保持，输出放大器A 2的输出信号V out等于C 2的保持信号； Series sample-and-hold device (Figure 4.2), the zero-loss switch AS 2 acts as a sampling switch, its input terminal is V in , the output amplifier A 2 is connected as a voltage follower, and the sampling capacitor C 2 is connected between the output terminal of AS 2 and the ground Between, the clock pulse is connected to the control word of AS 2 , when the "ON signal" of the clock pulse CLK arrives, AS 2 conducts, and the sampling capacitor C 2 samples the input signal V in , when the clock pulse CLK "OFF signal" When it arrives, AS 2 is turned off, the sampling capacitor C 2 holds the sampled signal, and the output signal V out of the output amplifier A 2 is equal to the holding signal of C 2 ;
以下是零损多路开关、桥电位DAC和桥电位ADC；为了叙述简便，约定：The following are zero-loss multi-channel switches, bridge potential DACs, and bridge potential ADCs; for the sake of brevity, conventions:
(1)零损多路开关、桥电位DAC和桥电位ADC命名为共同的名字“总器件”，总器件由多级“子级器件”组成；(1) The zero-loss multi-channel switch, the bridge potential DAC and the bridge potential ADC are named as the common name "total device", and the total device is composed of multi-level "sub-level devices";
(2)虚拟一个m级乘3bit的总器件，由m个子级器件组成，子级器件下标分别为α、β、γ、…、m，表示第1、第2、第3、…、第末级；原理上各个子级器件可以是不同的bit，但是为了为了叙述简便，约定各个子级器件的bit都等于3；(2) A total device of m level by 3bit is virtualized, which is composed of m sub-level devices. The final stage; in principle, each sub-level device can be a different bit, but for the sake of simplicity of description, it is agreed that the bit of each sub-level device is equal to 3;
(3)用λ通配各级下标；(3) Use λ to wildly match subscripts at all levels;
(4)数制为括号加下标，令二进制下标为“2”，八进制下标为“8”，默认模拟信号采用8进制，即没有下标的模拟信号默认为八进制数，如5默认为是(5) 8； (4) The number system is parentheses plus subscript, so that the binary subscript is "2", and the octal subscript is "8". The default analog signal adopts octal, that is, the analog signal without subscript defaults to octal number, such as 5 by default is (5) 8 ;
(5)数字信号按自然码编码；(5) The digital signal is coded according to the natural code;
实施例6：由零损开关构造成的零损多路开关，简称多路开关MS(Multiway-Switch)Embodiment 6: A zero-loss multi-way switch constructed of a zero-loss switch, referred to as a multiway switch MS (Multiway-Switch)
q bit的多路开关MS，它由q bit译码器YM λ和q bit低开关链LSC λ构成；即，MS＝YM+LSC；如果令q＝3，就构成图5.1中虚线框MS λ的电路；译码器根据控制信号在开关链中选通一个零损开关。 q bit multiplex switch MS, which is composed of q bit decoder YM λ and q bit low switch chain LSC λ ; that is, MS=YM+LSC; if q=3, it constitutes the dotted box MS λ in Figure 5.1 The circuit; the decoder selects a zero-loss switch in the switch chain according to the control signal.
实施例7：在零损多路开关基础上反方向并联零损开关构造成双向通道多路开关；Embodiment 7: On the basis of the zero-loss multi-way switch, the zero-loss switch is connected in parallel in the opposite direction to form a bidirectional channel multi-way switch;
图5.2是一个双向通道多路开关，图5.1中的多路开关是单向通道多路开关，信号只能从右往左传输，为了实现双向传输，将每个低开关LS λe并联一个反方向的低开关，就成了双向通道多路开关MS λ；图5.2是一个3bit的双向通道多路开关，这种将每个低开关LS λe并联一个反方向的低开关的办法适用于q bit的双向通道多路开关； Figure 5.2 is a two-way channel multi-way switch. The multi-way switch in Figure 5.1 is a one-way channel multi-way switch. The signal can only be transmitted from right to left. In order to achieve two-way transmission, each low switch LS λe is connected in parallel with a reverse direction The low switch of LS λe becomes a bidirectional channel multi-way switch MS λ ; Figure 5.2 is a 3-bit bidirectional channel multi-way switch. This method of connecting each low switch LS λe in parallel with a low switch in the opposite direction is applicable to q bit Bi-directional channel multiplexer;
实施例8：在多路开关基础上构造成的桥电位DAC；桥电位DAC由m个SDAC λ构成； Embodiment 8: a bridge potential DAC constructed on the basis of a multi-way switch; the bridge potential DAC is composed of m SDAC λ ;
SDAC λ包含三个模块：译码器YM λ、低开关链LSC λ(LS Chain)和电阻链RC λ(R Chain)；其中，译码器YM λ、低开关链LSC λ构成了多路开关MS λ； SDAC λ consists of three modules: decoder YM λ , low switch chain LSC λ (LS Chain) and resistance chain RC λ (R Chain); among them, decoder YM λ , low switch chain LSC λ constitute a multi-way switch MS λ ;
为了描述简单，先描述，将每个SDAC都定为3bit，令：Q＝2 q＝2 3＝8； For simplicity of description, first describe, each SDAC is set to 3 bits, set: Q=2 q =2 3 =8;
将3bit多路开关MS λ再连接一个3bit电阻链RC λ，就可以构成(图5.1)SDAC λ； Connect the 3bit multi-way switch MS λ to a 3bit resistance chain RC λ to form (Figure 5.1) SDAC λ ;
用8个阻值相等的电阻串联成一个电阻链RC λ，电阻链RC λ连接在电压V REF与地电位之间，将V REF分为8等分，每等分电压ΔV为ΔV＝V REF/8；形成8个基准电位点(V λ7～V λ0)，即V 0＝0、V λ1＝ΔV、V λ2＝2ΔV、…、V λ7＝7ΔV，(V λ8＝V REF，不充当基准电位点)，称V λe为第λ级第e阶基准电位；多路开关MS λ中的(LS λ7～LS λ0)的输入端分别连接到对应的基准电位点(V λ7～V λ0)，(LS λ7～LS λ0)的输出端汇集到 输出公共端BUS λ，这样就构成了一个3bit的SDAC λ(图5.1)； Use 8 resistors with equal resistance in series to form a resistance chain RC λ , the resistance chain RC λ is connected between the voltage V REF and the ground potential, divide V REF into 8 equal parts, and the voltage ΔV of each equal part is ΔV=V REF /8; form 8 reference potential points (V λ7 ～V λ0 ), that is, V 0 =0, V λ1 =ΔV, V λ2 =2ΔV, ..., V λ7 =7ΔV, (V λ8 =V REF , not serving as a reference potential point), V λe is called the reference potential of the e-th stage of the λth stage; the input terminals of the (LS λ7 ~ LS λ0 ) in the multi-way switch MS λ are respectively connected to the corresponding reference potential points (V λ7 ~ V λ0 ), (LS λ7 ~ LS λ0 ) output ports are collected to the output common port BUS λ , thus forming a 3-bit SDAC λ (Figure 5.1);
由m个SDAC λ可以组成一个m*3bit分辨率的桥电位DAC(图6)，桥电位DAC包括SDAC α、SDAC β、SDAC γ、…、SDAC m子级，当桥电位DAC收到一个m*3bit的数字信号时，将信号同一时间对应的送到各SDAC λ，当第λ级得到输入信号(d λ2d λ1d λ0)＝(E λ) 8后，LS λE通路ON，其它各路LS λe为OFF，LS λE将V λE传送到公共端BUS λ，(SDAC α、SDAC β、SDAC γ、…、SDAC m)各自的公共端电位分别为：(V αE、V βE、V γE、……、V mE)，V λE有双重属性，一方面，它是模拟电位，另一方面，它对应着数字信号d λ2d λ1d λ0＝(E λ) 8，即，V λE是模拟信号与数字信号的桥梁，所以命名为“桥电位”；桥电位V λE被提取后，提供给下一个环节： A bridge potential DAC with m*3bit resolution can be composed of m SDAC λ (Figure 6). The bridge potential DAC includes SDAC α , SDAC β , SDAC γ ,..., SDAC m sub-levels. When the bridge potential DAC receives a m *3bit digital signal, send the signal to each SDAC λ correspondingly at the same time, when the λth stage gets the input signal (d λ2 d λ1 d λ0 )=(E λ ) 8 , the LS λE channel is ON, and other channels LS λe is OFF, and LS λE transmits V λE to the common terminal BUS λ , (SDAC α , SDAC β , SDAC γ ,…, SDAC m ) respective common terminal potentials are: (V αE , V βE , V γE , ..., V mE ), V λE has dual properties, on the one hand, it is an analog potential, on the other hand, it corresponds to the digital signal d λ2 d λ1 d λ0 =(E λ ) 8 , that is, V λE is an analog signal The bridge with the digital signal, so it is named "bridge potential"; after the bridge potential V λE is extracted, it is provided to the next link:
构建桥电位DAC，需要建立“权桥电位V λEW”的概念；第λ级的权重运算器AW λ＝1/2 (λ-1)*3，虽然V αE～V mE都是桥电位，但是要注意到各个桥电位的权重(weight)不同，需要对各级的桥电位V λE进行权重运算，第λ级“权重运算器”符号为AW λ，AW λ也是其放大倍数符号，AW λ＝1/2 (λ-1)3，得到了1桥电位V λEW：(V αE、V βE/2 3、V γE/2 6、……、V mE/2 (m-1)3)，m个权桥电位经过求和器∑求和后就是总输出信号V Σ； To build a bridge potential DAC, it is necessary to establish the concept of “weight bridge potential V λEW ”; the weight operator AW λ =1/2 (λ-1)*3 of the λ-level weight calculator, although V αE ~V mE are all bridge potentials, but It should be noted that the weights of each bridge potential are different, and it is necessary to perform a weight calculation on the bridge potential V λE of each level. The symbol of the "weight calculator" at the λth level is AW λ , and AW λ is also the symbol of its magnification, AW λ = 1/2 (λ-1)3 , the 1-bridge potential V λEW is obtained: (V αE , V βE /2 3 , V γE /2 6 ,..., V mE /2 (m-1)3 ), m The total output signal V Σ is the total output signal V Σ after the potential of each weight bridge is summed by the summer Σ ;
总输出信号V Σ＝(V αE+V βE/2 3+V γE/2 6+…+V mE/2 (m-1)*3)， Total output signal V Σ = (V αE +V βE /2 3 +V γE /2 6 +…+V mE /2 (m-1)*3 ),
这样，由m个3bit分辨率的SDAC λ组成了一个高分辨率的桥电位DAC，其分辨率bit值＝3*m； In this way, a high-resolution bridge potential DAC is composed of m SDAC λs with 3-bit resolution, and its resolution bit value=3*m;
同样的原理，可构造成每级bit不同的m级桥电位DAC，The same principle can be constructed into an m-level bridge potential DAC with different bits for each level.
与上面每级3bit的桥电位DAC对比，其构造原理相同，只是将每级的3bit改成q λbit(λ是q的下标)，令：Q λ＝2^q λ，多路开关MS λ和电阻链RC λ都是q λbit，多路开关MS λ的输入端对应地连接到电阻链RC λ中的基准电位，当桥电位DAC收到一个m级不同bit的数字信号时，将信号同一时间对应的送到各SDAC λ，当第λ级得到输入信号(d λ(qλ-1)…d λ0)＝(E) Qλ时，(这里λ是q和Q的下标)，LS λE通路ON，其它各路LS λe为OFF，LS λE将V λE传送到公共端BUS λ，(SDAC α、SDAC β、SDAC γ、…、SDAC m)各自的公共端电位分别为：(V αE、V βE、V γE、……、V mE)，可知，得到桥电位V λE的方法与前面相同，不同的是权重运算器为AW λ＝1/2^(q α+q β+…+q (λ-1))，权桥电位V λEW＝V λE*AW λ， Compared with the bridge potential DAC with 3 bits per level above, its construction principle is the same, but the 3 bits of each level are changed to q λ bit (λ is the subscript of q), so that: Q λ =2^q λ , the multi-way switch MS Both λ and the resistance chain RC λ are q λ bits, and the input end of the multi-way switch MS λ is connected to the reference potential in the resistance chain RC λ correspondingly. When the bridge potential DAC receives a digital signal with m-level different bits, it will The signals are sent to each SDAC λ correspondingly at the same time. When the λth stage gets the input signal (d λ(qλ-1) ...d λ0 )=(E) Qλ , (where λ is the subscript of q and Q), LS λE channel is ON, other LS λe is OFF, LS λE transmits V λE to the common terminal BUS λ , (SDAC α , SDAC β , SDAC γ ,…, SDAC m ) respective common terminal potentials are: (V αE . _ _ _ _ _ _ q (λ-1) ), weight bridge potential V λEW ＝V λE *AW λ ,
总输出信号V Σ＝(V αE+V βE*AW β+V γE*AW γ+…+V mE*AW m)， Total output signal V Σ = (V αE +V βE *AW β +V γE *AW γ +…+V mE *AW m ),
桥电位DAC的分辨率等于各SDAC分辨率之和；The resolution of the bridge potential DAC is equal to the sum of the resolutions of each SDAC;
关于3bit*m级桥电位DAC权重运算器AW λ＝1/2 (λ-1)*3的分析：V αE的权重＝1，因为第β级前面已经有α级的3bit，所以V βE的权重只有1/2 3，采用比例运放器连接成一个“权重运算器”AW β，放大倍数AW β＝1/2 3，对V βE进行权重运算得到了第β级权桥电位为V βEW，V βEW＝V βE/2 3；同样，第γ级前面已经有α级和β级6bit，所以V γE的权重运算器为AW γ＝1/2 6，第γ级权桥电位为V γEW＝V γE/2 6；第λ级前面已经有(λ-1)3bit， 所以V λE的权重运算器为AW λ＝1/2 (λ-1)3， Analysis on the 3bit*m level bridge potential DAC weight calculator AW λ = 1/2 (λ-1)*3 : the weight of V αE = 1, because there is already 3 bits of α level in front of the β level, so the V βE The weight is only 1/2 3 , and a proportional operational amplifier is used to connect it into a "weight operator" AW β , the amplification factor AW β = 1/2 3 , and the weight calculation is performed on V βE to obtain the β-level weight bridge potential as V βEW , V βEW ＝V βE /2 3 ; Similarly, there are already 6 bits of α and β levels in front of the γth level, so the weight calculator of V γE is AW γ =1/2 6 , and the weight bridge potential of the γth level is V γEW =V γE /2 6 ; there is (λ-1)3bit in front of the λth stage, so the weight operator of V λE is AW λ =1/2 (λ-1)3 ,
关于m级不同bit的桥电位DAC权重运算器AW λ的分析：V αE的权重＝1，因为第β级前面已经有α级的q αbit，所以V βE的权重只有1/2^q α，采用比例运放器连接成一个“权重运算器”AW β，放大倍数AW β＝1/2^q α，对V βE进行权重运算得到了第β级权桥电位为V βEW，V βEW＝V βE*AW β；同样，第γ级前面已经有α级q αbit和β级q βbit，所以V γE的权重运算器为AW γ＝1/2^(q α+q β)，第γ级权桥电位为V γEW＝V γE/2^(q α+q β)；同样，第λ级的AW λ＝1/2^(q α+q β+…+q (λ-1))，权桥电位V λEW＝V λE*AW λ。 Analysis on the bridge potential DAC weight calculator AW λ with different bits of m level: the weight of V αE = 1, because there is already q α bit of α level in front of the β level, so the weight of V βE is only 1/2^q α , use a proportional operational amplifier to connect into a "weight operator" AW β , the amplification factor AW β =1/2^q α , carry out the weight operation on V βE to obtain the β-level weight bridge potential as V βEW , V βEW = V βE *AW β ; similarly, there are already α-level q α bit and β-level q β bit in front of the γ-th level, so the weight operator of V γE is AW γ =1/2^(q α +q β ), the first The γ level weight bridge potential is V γEW ＝V γE /2^(q α +q β ); similarly, the AW λ of the λth level ＝1/2^(q α +q β +…+q (λ-1) ), the weight bridge potential V λEW =V λE *AW λ .
实施例9：将多路开关MS与并行式ADC相结合构造成的MS式桥电位ADC；Embodiment 9: The MS type bridge potential ADC that combines multi-way switch MS and parallel type ADC to form;
MS式m*q bit桥电位ADC，MS type m*q bit bridge potential ADC,
架构：它由m个q bit SADC1 λ构成，SADC1 λ＝ADM λ+MS λ； Architecture: it consists of m q bit SADC1 λ , SADC1 λ = ADM λ + MS λ ;
如果令q＝3，q bit SADC1 λ就构成图7.1中的3bit SADC1 λ电路； If q=3, q bit SADC1 λ constitutes the 3bit SADC1 λ circuit in Figure 7.1;
将并行式ADC的符号设定为ADM λ，ADM λ中的Q个阻值相等的基准电阻串联成电阻链RC λ，将V REF分为Q等分，每等分电压ΔV为ΔV＝V REF/Q；形成Q个基准电位点(V λ(Q-1)～V λ0)，即V 0＝0、V λ1＝ΔV、V λ2＝2ΔV、…、V λ(Q-1)＝(Q-1)ΔV，(V λQ＝V REF，不充当基准电位点)，多路开关MS λ中的(LS λ(Q-1)～LS λ0)的输入端分别对应地连接到所述的基准电位点(V λ(Q-1)～V λ0)，这样就构成了一个q bit的SADC λ； Set the symbol of the parallel ADC as ADM λ , Q reference resistors with equal resistance in ADM λ are connected in series to form a resistance chain RC λ , divide V REF into Q equal parts, and the voltage ΔV of each equal part is ΔV=V REF /Q; form Q reference potential points (V λ(Q-1) ~V λ0 ), that is, V 0 =0, V λ1 =ΔV, V λ2 =2ΔV, ..., V λ(Q-1) =(Q -1) ΔV, (V λQ = V REF , does not serve as a reference potential point), the input terminals of (LS λ(Q-1) ~ LS λ0 ) in the multiplexer MS λ are respectively connected to the reference Potential point (V λ(Q-1) ~V λ0 ), thus forming a q bit SADC λ ;
工作原理：working principle:
Step1：接收从上一级SADC λ-1传输过来的模拟信号U λy，经过采样保持器T/H后稳定成模拟信号U λz，进入(并行式ADC)ADM λ进行AD转换；U λz是一个(0V～V REF)的电位，必定存在一个基准电位V λE(E＝0～(Q-1))，使得V λE＜U λz＜V λ(E+1)，基于量化单位ΔV，V λE就是采样信号U λZ的整数部分，实际上V λE就是桥电位，尾数电压U λX就是采样信号U λZ的小数部分，U λX＜ΔV；尾数电压U λX、采样信号U λZ和桥电位V λE的关系为：U λX＝U λZ-V λE Step1: Receive the analog signal U λy transmitted from the upper SADC λ-1 , stabilize it into an analog signal U λz after passing through the sample holder T/H , and enter the (parallel ADC) ADM λ for AD conversion; U λz is a (0V～V REF ), there must be a reference potential V λE (E=0～(Q-1)), so that V λE <U λz <V λ(E+1) , based on the quantization unit ΔV, V λE It is the integer part of the sampling signal U λZ , in fact V λE is the bridge potential, the mantissa voltage U λX is the fractional part of the sampling signal U λZ , U λX <ΔV; the mantissa voltage U λX , the sampling signal U λZ and the bridge potential V λE The relationship is: U λX = U λZ -V λE
Step2：ADM λ将V λE转换成数字信号D (q-1)…D 0，D (q-1)…D 0的去向分两路，一路是作为AD转换值，另一路传递给多路开关MS λ，作为路开关MS λ输入端d (q-1)…d 0的输入信号，将桥电位V λE取出； Step2: ADM λ converts V λE into a digital signal D (q-1) ... D 0 , D (q-1) ... D 0 is divided into two paths, one is used as an AD conversion value, and the other is passed to a multi-way switch MS λ , as the input signal of the road switch MS λ input terminal d (q-1) ...d 0 , the bridge potential V λE is taken out;
Step3：将U λZ和V λE送入求和器∑ λ，进行U λX＝U λZ-V λE运算，得到尾数电压U λX，然后通过放大器AM λ放大Q倍，仍是一个(0V～V REF)的电位，变成下一级SADC λ+1的输入信号U (λ+1)y； Step3: Send U λZ and V λE into the summer Σ λ , perform U λX = U λZ -V λE operation, and obtain the mantissa voltage U λX , and then amplify Q times through the amplifier AM λ , which is still a (0V～V REF ) becomes the input signal U (λ+1)y of the next stage SADC λ+1 ;
如此一级一级的转换，m个q bit的SADC就构成了m*q bit的桥电位ADC；Such a level-by-level conversion, m q bit SADCs constitute a m*q bit bridge potential ADC;
实施例10。将关/开链PSC与并行式ADC相结合构造的一种PSC式桥电位ADC；；Example 10. A PSC-type bridge potential ADC constructed by combining an off/on-chain PSC with a parallel ADC;
PSC式m*q bit桥电位ADC，如果令q＝3，就构成图7.2的m*3bit桥电位ADC；PSC-type m*q bit bridge potential ADC, if q=3, constitutes the m*3bit bridge potential ADC in Figure 7.2;
架构：将并行式ADC的符号设定为ADM λ，ADM λ中的Q个阻值相等的基准电阻串联成电阻链RC λ，将V REF分为Q等分，每等分电压ΔV为ΔV＝V REF/Q；形成Q个基准电位点(V λ(Q-1)～V λ0)，即V 0＝0、V λ1＝ΔV、 V λ2＝2ΔV、…、V λ(Q-1)＝(Q-1)ΔV，(V λQ＝V REF，不充当基准电位点)，关/开链PSC λ中的(PS λ(Q-1)～PS λ0)的输入端分别对应地连接到所述的基准电位点(V λ(Q-1)～V λ0)，这样就构成了一个3bit的SADC λ；PS λe的下方控制字(I λe)为低断高通(I +)，上方控制字(I λ(e+1))为高断低通(I -)，因为(I λe)的阶与PS λe的阶相同，所以又命名(I λe)为主控制字，(I λ(e+1))为从控制字；另外，令I λ0≡1，I λQ≡0； Architecture: Set the symbol of the parallel ADC as ADM λ , Q reference resistors with equal resistance in ADM λ are connected in series to form a resistance chain RC λ , divide V REF into Q equal parts, and each equal part voltage ΔV is ΔV= V REF /Q; form Q reference potential points (V λ(Q-1) ~V λ0 ), that is, V 0 =0, V λ1 =ΔV, V λ2 =2ΔV, ..., V λ(Q-1) = (Q-1)ΔV, (V λQ = V REF , does not serve as a reference potential point), the input terminals of (PS λ(Q-1) ~PS λ0 ) in the closed/open chain PSC λ are respectively connected to the corresponding The above-mentioned reference potential point (V λ(Q-1) ~V λ0 ), thus constitutes a 3-bit SADC λ ; the lower control word (I λe ) of PS λe is low-off high-pass (I + ), the upper control word (I λ(e+1) ) is high-off low-pass (I - ), because the order of (I λe ) is the same as that of PS λe , so it is also named (I λe ) as the main control word, (I λ(e +1) ) is the slave control word; in addition, let I λ0 ≡1, I λQ ≡0;
工作原理：working principle:
Step1：接收从上一级SADC λ-1传输过来的模拟信号U λy，经过采样保持器T/H后稳定成模拟信号U λz，进入(并行式ADC)ADM λ进行AD转换；U λz是一个(0V～V REF)的电位，必定存在一个基准电位V λE(E＝0～(Q-1))，使得V λE＜U λz＜V λ(E+1)，基于量化单位ΔV，V λE就是采样信号U λZ的整数部分，实际上V λE就是桥电位，尾数电压U λX就是采样信号U λZ的小数部分，U λX＜ΔV；尾数电压U λX、采样信号U λZ和桥电位V λE的关系为：U λX＝U λZ-V λE Step1: Receive the analog signal U λy transmitted from the upper SADC λ-1 , stabilize it into an analog signal U λz after passing through the sample holder T/H , and enter the (parallel ADC) ADM λ for AD conversion; U λz is a (0V～V REF ), there must be a reference potential V λE (E=0～(Q-1)), so that V λE <U λz <V λ(E+1) , based on the quantization unit ΔV, V λE It is the integer part of the sampling signal U λZ , in fact V λE is the bridge potential, the mantissa voltage U λX is the fractional part of the sampling signal U λZ , U λX <ΔV; the mantissa voltage U λX , the sampling signal U λZ and the bridge potential V λE The relationship is: U λX = U λZ -V λE
Step2：ADM λ中的比较器链将V λE转换成控制字组(I λ(Q-1)～I λ0)，要特别注意的是，这个控制字组与译码器的控制字组有区别，译码器的控制字组，只有被选中的那个控制字等于0，而图7.2中，因为比较器的同相输入端接U λZ而反相输入端接基准电位，所以比较器输出的控制字组是(I λE～I λ 0)＝1，(I λ(E+1)～I λ0)＝0；可以证明，I λ0～I λQ中由1…1即将变到0…0的点就是翻转点I λE，它所对应的电位点就是桥电位点V λE；当然，如果反过来，比较器的反相输入端接U λZ而同相输入端接基准电位，比较器输出的控制字组是(I λE～I λ0)＝0，(I λ(E+1)～I λ0)＝1，这样的话，需要调整为PS λe的上方控制字(I λe)为低断高通(I +)，下方控制字(I λ(e+1))为高断低通(I -)；控制字组(I λ(Q-1)～I λ0)的去向分两路，一路去编码器ENC形成数字信号，一路提供给关/开链，注意到PS λe的下方控制字(I λe)为低断高通(I +)，上方控制字(I λ(e+1))为高断低通(I -)；参考前面的分析可知，必须满足高断低通处于低电平(I -＝0)且低断高通处于高电平(I +＝1)，即，I +/I -＝1/0(下1上0)，关/开PS λe才会处于ON态，而这个PS λe的输入端正好连接在桥电位点，这个PS λe正好就是PS λE；PS λE将桥电位V λE取出送入下一个环节； Step2: The comparator chain in ADM λ converts V λE into a control word (I λ(Q-1) ~I λ0 ), it should be noted that this control word is different from the control word of the decoder , the control word group of the decoder, only the selected control word is equal to 0, and in Figure 7.2, because the non-inverting input terminal of the comparator is connected to U λZ and the inverting input terminal is connected to the reference potential, the control word output by the comparator The group is (I λE ～I λ 0 )=1, (I λ(E+1) ～I λ0 )=0; it can be proved that the point from 1...1 to 0...0 in I λ0 ～I λQ is Inversion point I λE , the potential point corresponding to it is the bridge potential point V λE ; of course, if in reverse, the inverting input terminal of the comparator is connected to U λZ and the non-inverting input terminal is connected to the reference potential, the control word group output by the comparator is (I λE ～I λ0 )=0, (I λ(E+1) ～I λ0 )=1, in this case, it is necessary to adjust the upper control word (I λe ) of PS λe to be low-off high-pass (I + ), The lower control word (I λ(e+1) ) is high-off and low-pass (I - ); the destination of the control word group (I λ(Q-1) ~I λ0 ) is divided into two paths, and one path goes to the encoder ENC to form a digital Signal, one way is provided to close/open chain, note that the lower control word (I λe ) of PS λe is low-break high-pass (I + ), and the upper control word (I λ(e+1) ) is high-break low-pass (I - ); Referring to the previous analysis, it can be seen that the high-break low-pass must be at a low level (I - = 0) and the low-break high-pass is at a high level (I + = 1), that is, I + /I - = 1/ 0 (lower 1 upper 0), turn off/on PS λe will be in the ON state, and the input terminal of this PS λe is just connected to the bridge potential point, this PS λe is just PS λE ; PS λE takes out the bridge potential V λE and sends it into the next link;
Step3：将U λZ和V λE送入求和器∑ λ，进行U λX＝U λZ-V λE运算，得到尾数电压U λX，然后通过放大器AM λ放大Q倍，仍是一个(0V～V REF)的电位，变成下一级SADC λ+1的输入信号U (λ+1)y； Step3: Send U λZ and V λE into the summer Σ λ , perform U λX = U λZ -V λE operation, and obtain the mantissa voltage U λX , and then amplify Q times through the amplifier AM λ , which is still a (0V～V REF ) becomes the input signal U (λ+1)y of the next stage SADC λ+1 ;
如此一级一级的转换，m个3bit的SADC就构成了m*3bit桥电位ADC。Such a level-by-level conversion, m 3bit SADCs constitute an m*3bit bridge potential ADC.

Claims (11)

  1. 一种开关运放，其特征在于，A switching op amp, characterized in that,
    所述开关运放是在基本运放的基础上增加一个控制级以用于控制输出级的通断，所述基本运放包括输入级、中间级、输出级；The switch op amp is based on the basic op amp with a control stage added to control the on-off of the output stage, and the basic op amp includes an input stage, an intermediate stage, and an output stage;
    所述输出级包括NPN输出三极管、PNP输出三极管；The output stage includes an NPN output transistor and a PNP output transistor;
    所述控制级由控制管对构成；The control stage is composed of control pipe pairs;
    所述控制管包括双极型三极管或场效应管，所述双极型三极管的基极或所述场效应管的栅极为所述控制管的泛基极，所述双极型三极管的发射极或所述场效应管的源极为所述控制管的泛射极，所述双极型三极管的集电极或所述场效应管的漏极为所述控制管的泛集电极，所述泛射极和所述泛集电极之间的通道为所述控制管的主流通道；泛基极的控制信号I＝0表示低电平，I＝1表示高电平；The control transistor includes a bipolar transistor or a field effect transistor, the base of the bipolar transistor or the grid of the field effect transistor is the pan-base of the control transistor, and the emitter of the bipolar transistor Or the source of the field effect tube is the flood emitter of the control tube, the collector of the bipolar triode or the drain of the field effect tube is the flood collector of the control tube, and the flood emitter The channel between the pan-collector and the pan-collector is the main channel of the control tube; the control signal I=0 of the pan-base means a low level, and I=1 means a high level;
    一个控制管对包括一个第一控制管和一个相同的第二控制管，所述两个控制管受控于同一个控制信号I；所述第一控制管的主流通道连接于电源+V CC与所述PNP输出三极管的基极之间，所述第二控制管的主流通道连接于电源-V CC与所述NPN输出三极管的基极之间； A control tube pair includes a first control tube and an identical second control tube, the two control tubes are controlled by the same control signal I; the main channel of the first control tube is connected to the power supply +V CC and Between the bases of the PNP output transistors, the main channel of the second control tube is connected between the power supply -V CC and the bases of the NPN output transistors;
    当控制信号I使得所述第一控制管和第二控制管的主流通道导通时，所述第一控制管使得所述PNP输出三极管的基极与电源+V CC连通，使所述PNP输出三极管截止；所述第二控制管使得所述NPN输出三极管的基极与电源-V CC连通，使所述NPN输出三极管截止；这时，开关运放处于OFF状态； When the control signal I makes the main channels of the first control tube and the second control tube conduct, the first control tube makes the base of the PNP output transistor communicate with the power supply +V CC , so that the PNP output The transistor is cut off; the second control tube connects the base of the NPN output transistor to the power supply -V CC , so that the NPN output transistor is cut off; at this time, the switching amplifier is in an OFF state;
    当控制信号I使得所述第一控制管和第二控制管的主流通道截止时，所述第一控制管和第二控制管相当于不存在；这时，所述开关运放处于基本运放状态，即开关运放处于ON状态；When the control signal I makes the main channel of the first control tube and the second control tube cut off, the first control tube and the second control tube are equivalent to non-existence; state, that is, the switching op amp is in the ON state;
    全文名词和符号定义：α、β、γ、…、m，分别表示第1级、第2级、第3级、…、第末级，其通配符为λ；
    Figure PCTCN2022103359-appb-100001
    的第一下标为级下标，α、β、γ、…、m，分别表示第1级、第2级、第3级、…、第末级，第二下标为阶下标，表示器件链的第0阶、第1阶、第2阶…；其阶下标通配符为e；称下标
    Figure PCTCN2022103359-appb-100002
    为第λ级第e阶；默认各种链器件的阶从小到大的排列方向为从下往上，λ、e、q λ为包括零在内的正整数；qα、qβ、qγ、…分别为第α、β、γ、…级的位数；Q λ＝2 qλ；
    Figure PCTCN2022103359-appb-100003
    Figure PCTCN2022103359-appb-100004
    Definitions of terms and symbols in the full text: α, β, γ, ..., m, respectively represent the first level, the second level, the third level, ..., the last level, and the wildcard is λ;
    Figure PCTCN2022103359-appb-100001
    The first subscript of is the level subscript, α, β, γ, ..., m, respectively represent the first level, the second level, the third level, ..., the last level, and the second subscript is the order subscript, indicating The 0th order, the 1st order, the 2nd order... of the device chain; the subscript wildcard of the order is e; it is called the subscript
    Figure PCTCN2022103359-appb-100002
    is the λth order and the eth order; the order of various chain devices is arranged from small to large by default, and the arrangement direction is from bottom to top, and λ, e, and q λ are positive integers including zero; qα, qβ, qγ, ... respectively Be the number of digits of the α, β, γ, ... stages; Q λ =2 qλ ;
    Figure PCTCN2022103359-appb-100003
    Figure PCTCN2022103359-appb-100004
  2. 根据权利要求1所述的一种开关运放，其特征在于，所述控制管对包括NPN控制管对和PNP控制管对，A switch op amp according to claim 1, wherein the pair of control transistors includes a pair of NPN control transistors and a pair of PNP control transistors,
    所述NPN控制管对包括第一NPN控制管、第二NPN控制管，The NPN control tube pair includes a first NPN control tube and a second NPN control tube,
    所述第一NPN控制管的泛集电极连接电源+V CC，所述第一NPN控制管的泛射极连接所述PNP输出三极管的基极，所述第二NPN控制管的泛射极连接电源-V CC，所述第二NPN控制管的泛集电极连接所述NPN输出三极管的基极； The flood collector of the first NPN control transistor is connected to the power supply +V CC , the flood emitter of the first NPN control transistor is connected to the base of the PNP output transistor, and the flood emitter of the second NPN control transistor is connected to Power supply-V CC , the pan-collector of the second NPN control transistor is connected to the base of the NPN output transistor;
    所述第一NPN控制管的泛基极、第二NPN控制管的泛基极同时连接于控制信号I+，当控制信号I+＝0时，所述第一NPN控制管、第二NPN控制管截止，相当于所述两个控制管这时候不存在；当控制信号I+＝1时，所述第一NPN控制管、第二NPN控制管导通，所述NPN输出三极管的基极就会被第二NPN控制管连接到电源-V CC而截止，所述PNP输出三极管的基极就会被第一NPN控制管连接到电源+V CC而截止；两个输出管截止，这时，所述开关运放处于关断状态；这是控制信号高电平关断开关运放，简称高断低通式运放，-I为高断低通控制端； The ubiquitous base of the first NPN control transistor and the ubiquitous base of the second NPN control transistor are connected to the control signal I+ at the same time, and when the control signal I+=0, the first NPN control transistor and the second NPN control transistor are cut off , which is equivalent to the fact that the two control transistors do not exist at this time; when the control signal I+=1, the first NPN control transistor and the second NPN control transistor are turned on, and the base of the NPN output transistor will be turned on by the second NPN control transistor. When the two NPN control transistors are connected to the power supply -V CC and cut off, the base of the PNP output transistor will be connected to the power supply +V CC by the first NPN control transistor and cut off; the two output transistors are cut off, and at this time, the switch The op amp is in the off state; this is the high-level turn-off switch op amp of the control signal, referred to as the high-off and low-pass op amp, and -I is the high-off and low-pass control terminal;
    所述PNP控制管对包括第一PNP控制管、第二PNP控制管；The PNP control tube pair includes a first PNP control tube and a second PNP control tube;
    所述第一PNP控制管的泛射极连接电源+V CC，所述第一PNP控制管的泛集电极连接所述PNP输出三极管的基极，所述第二PNP控制管的泛集电极连接电源-V CC，所述第二PNP控制管的泛射极连接所述NPN输出三极管的基极； The flood emitter of the first PNP control tube is connected to the power supply +V CC , the pan collector of the first PNP control tube is connected to the base of the PNP output transistor, and the pan collector of the second PNP control tube is connected to Power supply-V CC , the flood emitter of the second PNP control transistor is connected to the base of the NPN output transistor;
    所述第一PNP控制管的泛基极、第二PNP控制管的泛基极同时连接于控制信号I-，当控制信号I-＝1时，所述第一PNP控制管、第二PNP控制管截止，相当于所述两个控制管这时候不存在；当控制信号I-＝0时，所述第一PNP控制管、第二PNP控制管导通；所述NPN输出三极管的基极就会被第二PNP控制管连接到电源-V CC而截止，所述PNP输出三极管的基极就会被第一PNP控制管连接到电源+V CC而截止；两个输出管截止，这时，所述开关运放处于关断状态；这是控制信号低电平关断开关运放，简称低断高通式运放，+I为低断高通控制端； The ubiquitous base of the first PNP control transistor and the ubiquitous base of the second PNP control transistor are simultaneously connected to the control signal I-, when the control signal I-=1, the first PNP control transistor and the second PNP control transistor The tube is cut off, which means that the two control tubes do not exist at this time; when the control signal I-=0, the first PNP control tube and the second PNP control tube are turned on; the base of the NPN output transistor is on It will be cut off by the second PNP control transistor connected to the power supply -V CC , and the base of the PNP output transistor will be cut off by the first PNP control transistor connected to the power supply +V CC ; the two output transistors are cut off, at this time, The switch op amp is in an off state; this is the low level of the control signal to turn off the switch op amp, referred to as the low-cut high-pass op amp, and +I is the low-cut high-pass control terminal;
    NPN控制管对和PNP控制管对中，只要有一对控制管导通，所述NPN输出三极管的基极就会被连接到电源-V CC而截止，所述PNP输出三极管的基极就会被连接到电源+V CC而截止；这时，所述开关运放处于关断状态； In the pair of NPN control transistors and the pair of PNP control transistors, as long as one pair of control transistors is turned on, the base of the NPN output transistor will be connected to the power supply -V CC and cut off, and the base of the PNP output transistor will be turned off. connected to the power supply +V CC and cut off; at this time, the switching amplifier is in an off state;
    当全部控制管都截止时，相当于控制级在电路中不存在，这时，所述运放处于基本运放状态；When all the control tubes are cut off, it means that the control stage does not exist in the circuit, and at this moment, the operational amplifier is in the basic operational amplifier state;
    NPN控制管对和PNP控制管对都存在时为双控式运放，具有-I、+I控制端；只有NPN控制管对时为高断低通式运放，具有-I控制端；只有PNP控制管对时为低断高通式运放，具有+I控制端。When both the NPN control tube pair and the PNP control tube pair exist, it is a dual-control op amp, with -I, +I control terminals; only when the NPN control tube pair is a high-break low-pass op amp, with a -I control terminal; only The timing of the PNP control tube is a low-cut high-pass op amp with a +I control terminal.
  3. 一种包括权利要求2所述开关运放的零损开关，其特征在于，A zero-loss switch comprising a switching amplifier according to claim 2, characterized in that,
    所述开关运放的输出端与反相输入端连接就构成了零损开关，所述开关运放的同相输入端作为所述零损开关的输入端，所述开关运放的控制端作为所述零损开关的控制端；The output end of the switch op amp is connected with the inverting input end to form a zero-loss switch, the non-inverting input end of the switch op amp is used as the input end of the zero loss switch, and the control end of the switch op amp is used as the zero loss switch. The control terminal of the zero loss switch;
    只有NPN控制管对时为高断低通式零损开关，具有-I控制端，其导通条件为-I＝0；只有PNP控制管对时为低断高通式零损开关，具有+I控制端，其导通条件为+I＝1；NPN控制管对和PNP控制管对都存在时为双控零损开关，具有-I、+I控制端，其导通条件为+I＝1且-I＝0。Only the NPN control tube is a high-break low-pass type zero-loss switch with a -I control terminal, and its conduction condition is -I=0; only the PNP control tube is a low-break high-pass type zero-loss switch with +I The control terminal, its conduction condition is +I=1; when both the NPN control tube pair and the PNP control tube pair exist, it is a dual-control zero-loss switch, with -I, +I control terminals, and its conduction condition is +I=1 And -I=0.
  4. 一种包括权利要求3所述的零损开关的双向零损开关，其特征在于，A bidirectional zero-loss switch comprising the zero-loss switch according to claim 3, characterized in that,
    将两个所述零损开关进行正方向和反方向并联，并且将两者对应的控制端相连接，-I连接-I、+I连接+I，构成双向零损开关。The two zero-loss switches are connected in parallel in the forward direction and the reverse direction, and the corresponding control terminals of the two are connected, -I is connected to -I, and +I is connected to +I to form a bidirectional zero-loss switch.
  5. 一种包括权利要求2所述开关运放的反馈型采样保持器，其特征在于，反馈型采样保持器包括输入缓冲运放、输出缓冲运放、采样开关、保持电容，开关运放反馈型采样保持器的特征在于，A kind of feedback type sample-and-hold device comprising the described switching op-amp of claim 2, it is characterized in that, the feedback type sample-and-hold device comprises input buffer op-amp, output buffer op-amp, sampling switch, holding capacitor, switch op-amp feedback type sampling The retainer is characterized by,
    将原有反馈型采样保持器的输入缓冲运放用所述开关运放进行置换，所述开关运放的控制端连接时钟信号，取代原有的采样开关。The input buffer op-amp of the original feedback type sample-and-hold device is replaced with the switch op-amp, and the control terminal of the switch op-amp is connected with a clock signal to replace the original sampling switch.
  6. 一种包括权利要求3所述零损开关的串联型采样保持器，其特征在于，串联型采样保持器包括输入电压跟随器、输出电压跟随器、采样开关、保持电容，零损开关串联型采样保持器的特征在于，A series type sample-and-hold device comprising the zero-loss switch described in claim 3, characterized in that, the series-type sample-and-hold device comprises an input voltage follower, an output voltage follower, a sampling switch, a holding capacitor, and a zero-loss switch series type sampling The retainer is characterized by,
    将原有串联型采样保持器的输入电压跟随器用所述零损开关进行置换，所述零损开关的控制端连接时钟信号，取代原有的采样开关。The input voltage follower of the original serial sample-and-hold device is replaced by the zero-loss switch, and the control terminal of the zero-loss switch is connected with a clock signal to replace the original sampling switch.
  7. 一种包括权利要求3所述零损开关的零损多路开关，其特征在于，A zero-loss multiplex switch comprising the zero-loss switch described in claim 3, characterized in that,
    一个q位的零损多路开关，包括一个q位译码器和多个零损开关；所述q位译码器的2 q个输出端与所述零损开关的控制端进行连接，包括一对一的连接、一对多的连接、多对一的连接，所述零损开关的输入端作为所述零损多路开关的输入端。 A q-bit zero-loss multi-channel switch, including a q-bit decoder and a plurality of zero-loss switches; 2 q output terminals of the q-bit decoder are connected to the control terminals of the zero-loss switches, including For one-to-one connection, one-to-many connection, and many-to-one connection, the input end of the zero-loss switch is used as the input end of the zero-loss multi-way switch.
  8. 一种包括权利要求4所述双向零损开关的双向零损多路开关，其特征在于，A bidirectional zero-loss multiplex switch comprising the bidirectional zero-loss switch described in claim 4, characterized in that,
    一个q位的双向零损多路开关，包括一个q位译码器和多个双向零损开关；所述q位译码器的2 q个输出端与所述双向零损开关的控制端进行连接，包括一对一的连接、一对多的连接、多对一的连接，所述零损开关的输入端作为所述零损多路开关的输入端。 A q-bit bidirectional zero-loss multi-channel switch includes a q-bit decoder and a plurality of bidirectional zero-loss switches; 2 q output terminals of the q-bit decoder are connected to the control terminals of the bidirectional zero-loss switch The connection includes a one-to-one connection, a one-to-many connection, and a many-to-one connection, and the input end of the zero-loss switch is used as the input end of the zero-loss multi-way switch.
  9. 一种包括权利要求3所述零损开关的桥电位ADC，其特征在于，A bridge potential ADC comprising the zero-loss switch described in claim 3, characterized in that,
    一个n位零损开关桥电位ADC包括m个子级SADC，m个子级SADC α、SADC β、SADC γ、…、SADC m的位数分别为q α、q β、q γ、…、q m，其中，m为末级，n＝q α+q β+q γ+…+q m；所述第λ级子级SADC是一个q λ位SADC λ，包括一个q λ位并行式ADCB λ、一个桥电位
    Figure PCTCN2022103359-appb-100005
    的提取模块、一个中间模块；     An n-bit zero-loss switching bridge potential ADC includes m sub-levels SADC, and the number of m sub-levels SADC α , SADC β , SADC γ ,…, SADC m are q α , q β , q γ ,…, q m , Wherein, m is the final stage, n=q α +q β +q γ +...+q m ; the λth sub-level SADC is a q λ bit SADC λ , including a q λ bit parallel ADCB λ , a bridge potential
    Figure PCTCN2022103359-appb-100005
    The extraction module and an intermediate module;
    所述中间模块包括采样保持器T/H、求和器∑ λ、放大器AM λ； The intermediate module includes a sample-and-hold T/H, a summer Σ λ , an amplifier AM λ ;
    第λ级模拟信号电压
    Figure PCTCN2022103359-appb-100006
    连接采样保持器T/H处理后成为稳定信号电压
    Figure PCTCN2022103359-appb-100007
    分支两路，一路送入求和器∑ λ的被减数端，一路送入所述比较器链充当各个比较器的同相输入端信号，与各个接在比较器反相输入端的基准电位进行比较；     Level λ analog signal voltage
    Figure PCTCN2022103359-appb-100006
    After connecting the sample-and-hold T/H processing, it becomes a stable signal voltage
    Figure PCTCN2022103359-appb-100007
    There are two branches, one is sent to the minuend end of the summer Σλ , and the other is sent to the comparator chain as the non-inverting input signal of each comparator, and compared with the reference potential connected to the inverting input of each comparator ;
    所述q λ位并行式ADCB λ包括一个q λ位基准电阻链
    Figure PCTCN2022103359-appb-100008
    一个q λ位比较器链
    Figure PCTCN2022103359-appb-100009
    其中
    Figure PCTCN2022103359-appb-100010
    可以省略)、一个q λ位编码器，所述基准电位链各电阻相等， 形成Q λ个等间距ΔV的基准电位点
    Figure PCTCN2022103359-appb-100011
    The q λ -bit parallel ADCB λ includes a q λ -bit reference resistor chain
    Figure PCTCN2022103359-appb-100008
    A chain of q lambda bit comparators
    Figure PCTCN2022103359-appb-100009
    in
    Figure PCTCN2022103359-appb-100010
    can be omitted), a q λ bit encoder, the resistances of the reference potential chain are equal to form Q λ reference potential points with equal intervals of ΔV
    Figure PCTCN2022103359-appb-100011
    所述桥电位
    Figure PCTCN2022103359-appb-100012
    的提取模块包括一个由Q λ个双控零损开关
    Figure PCTCN2022103359-appb-100013
    组成的q λ位双控零损开关链，所述桥电位
    Figure PCTCN2022103359-appb-100014
    的数学表达式为：
    Figure PCTCN2022103359-appb-100015
    The bridge potential
    Figure PCTCN2022103359-appb-100012
    The extraction module consists of a dual-controlled zero-loss switch consisting of Q λ
    Figure PCTCN2022103359-appb-100013
    Composed of a chain of q λ -bit double-controlled zero-loss switches, the bridge potential
    Figure PCTCN2022103359-appb-100014
    The mathematical expression of is:
    Figure PCTCN2022103359-appb-100015
    所述比较器链各个比较器的反相输入端、所述双控零损开关链的各个双控零损开关的输入端、所述基准电阻链的各个基准电位点，三者的各个端或点按照下标的对应关系进行连接；The inverting input terminals of each comparator of the comparator chain, the input terminals of each dual-control zero-loss switch of the dual-control zero-loss switch chain, each reference potential point of the reference resistance chain, each terminal of the three or The points are connected according to the corresponding relationship of subscripts;
    所述双控零损开关
    Figure PCTCN2022103359-appb-100016
    的下方为低断高通端
    Figure PCTCN2022103359-appb-100017
    上方为高断低通端
    Figure PCTCN2022103359-appb-100018
    由
    Figure PCTCN2022103359-appb-100019
    的
    Figure PCTCN2022103359-appb-100020
    连接
    Figure PCTCN2022103359-appb-100021
    的
    Figure PCTCN2022103359-appb-100022
    的
    Figure PCTCN2022103359-appb-100023
    连接
    Figure PCTCN2022103359-appb-100024
    的
    Figure PCTCN2022103359-appb-100025
    的
    Figure PCTCN2022103359-appb-100026
    连接
    Figure PCTCN2022103359-appb-100027
    的
    Figure PCTCN2022103359-appb-100028
    …、以此类推，
    Figure PCTCN2022103359-appb-100029
    Figure PCTCN2022103359-appb-100030
    形成Q-1个连接点，每个连接点用低断高通端标出，形成双控零损开关
    Figure PCTCN2022103359-appb-100031
    的控制端链
    Figure PCTCN2022103359-appb-100032
    Figure PCTCN2022103359-appb-100033
    并且将
    Figure PCTCN2022103359-appb-100034
    的
    Figure PCTCN2022103359-appb-100035
    固定接1，
    Figure PCTCN2022103359-appb-100036
    的
    Figure PCTCN2022103359-appb-100037
    固定接0；     The dual control zero loss switch
    Figure PCTCN2022103359-appb-100016
    Below is the low-off high-pass end
    Figure PCTCN2022103359-appb-100017
    The top is the high-break low-pass end
    Figure PCTCN2022103359-appb-100018
    Depend on
    Figure PCTCN2022103359-appb-100019
    of
    Figure PCTCN2022103359-appb-100020
    connect
    Figure PCTCN2022103359-appb-100021
    of
    Figure PCTCN2022103359-appb-100022
    of
    Figure PCTCN2022103359-appb-100023
    connect
    Figure PCTCN2022103359-appb-100024
    of
    Figure PCTCN2022103359-appb-100025
    of
    Figure PCTCN2022103359-appb-100026
    connect
    Figure PCTCN2022103359-appb-100027
    of
    Figure PCTCN2022103359-appb-100028
    …and so on,
    Figure PCTCN2022103359-appb-100029
    Figure PCTCN2022103359-appb-100030
    Form Q-1 connection points, and each connection point is marked with a low-off high-pass terminal to form a double-control zero-loss switch
    Figure PCTCN2022103359-appb-100031
    console chain
    Figure PCTCN2022103359-appb-100032
    Figure PCTCN2022103359-appb-100033
    and will
    Figure PCTCN2022103359-appb-100034
    of
    Figure PCTCN2022103359-appb-100035
    fixed connection 1,
    Figure PCTCN2022103359-appb-100036
    of
    Figure PCTCN2022103359-appb-100037
    Fixed connection 0;
    比较器链的输出端控制字
    Figure PCTCN2022103359-appb-100038
    有两个输出方向，一个输出方向是编码器，通过编码器得到第λ级ADCB λ的q λ位数字信号，实现第λ级的AD转换；另一个输出方向是作为控制字连接到对应下标的所述双控零损开关控制端
    Figure PCTCN2022103359-appb-100039
    所述双控零损开关的各个输出端都连接到公共输出端BUS λ进而连接到求和器∑ λ的减数端；     The output control word of the comparator chain
    Figure PCTCN2022103359-appb-100038
    There are two output directions, one output direction is the encoder, the q λ bit digital signal of the λ-level ADCB λ is obtained through the encoder, and the AD conversion of the λ-level is realized; the other output direction is connected to the corresponding subscript as a control word The dual control zero loss switch control terminal
    Figure PCTCN2022103359-appb-100039
    Each output end of the double-controlled zero-loss switch is connected to the common output end BUS λ and then connected to the subtrahend end of the summer Σ λ ;
    当所述q λ位并行式ADCB λ得到模拟信号电压
    Figure PCTCN2022103359-appb-100040
    时，
    Figure PCTCN2022103359-appb-100041
    值必处于两个基准电位之间，其中，将下面这个基准电位定义为桥电位
    Figure PCTCN2022103359-appb-100042
    桥电位
    Figure PCTCN2022103359-appb-100043
    是不大于并最接近于
    Figure PCTCN2022103359-appb-100044
    的基准电位，其数学表达式为：
    Figure PCTCN2022103359-appb-100045
    When the q λ bit parallel ADCB λ gets the analog signal voltage
    Figure PCTCN2022103359-appb-100040
    hour,
    Figure PCTCN2022103359-appb-100041
    The value must lie between two reference potentials, where the following reference potential is defined as the bridge potential
    Figure PCTCN2022103359-appb-100042
    bridge potential
    Figure PCTCN2022103359-appb-100043
    is not greater than and closest to
    Figure PCTCN2022103359-appb-100044
    The reference potential of , its mathematical expression is:
    Figure PCTCN2022103359-appb-100045
    桥电位
    Figure PCTCN2022103359-appb-100046
    及以下的基准电位点所对应下标的比较器输出值等于1，大于桥电位
    Figure PCTCN2022103359-appb-100047
    值的基准电位点所对应下标的比较器输出值等于0，即，以
    Figure PCTCN2022103359-appb-100048
    分界点，
    Figure PCTCN2022103359-appb-100049
    及下面的比较器输出值是一串1，
    Figure PCTCN2022103359-appb-100050
    上面的比较器输出值是一串0；只有
    Figure PCTCN2022103359-appb-100051
    处于一串1变成一串0的临界点，所述双控零损开关
    Figure PCTCN2022103359-appb-100052
    的导通条件为：低断高通端
    Figure PCTCN2022103359-appb-100053
    且高断低通端
    Figure PCTCN2022103359-appb-100054
    即，只有
    Figure PCTCN2022103359-appb-100055
    满足
    Figure PCTCN2022103359-appb-100056
    且
    Figure PCTCN2022103359-appb-100057
    的导通条件，其它的双控零损开关，要么上下控制字全1，要么上下控制字全0，不满足导通条件；
    Figure PCTCN2022103359-appb-100058
    导通将桥电位
    Figure PCTCN2022103359-appb-100059
    取出并送入公共输出端BUS λ，进而送入求和器∑ λ减数端，求和器∑ λ进行
    Figure PCTCN2022103359-appb-100060
    运算后得到一个小于ΔV的值，命名为尾数电压
    Figure PCTCN2022103359-appb-100061
    然后通过放大器AM λ放大2 qλ倍，将
    Figure PCTCN2022103359-appb-100062
    扩大到(-V REF～V REF)的电压范围，变成下一级SADC λ+1的输入信号U (λ+1)y；     bridge potential
    Figure PCTCN2022103359-appb-100046
    The comparator output value corresponding to the subscript of the reference potential point below is equal to 1, which is greater than the bridge potential
    Figure PCTCN2022103359-appb-100047
    The comparator output value of the subscript corresponding to the reference potential point of the value is equal to 0, that is, with
    Figure PCTCN2022103359-appb-100048
    Demarcation point,
    Figure PCTCN2022103359-appb-100049
    and the following comparator output value is a string of 1s,
    Figure PCTCN2022103359-appb-100050
    The above comparator output value is a string of 0; only
    Figure PCTCN2022103359-appb-100051
    At the critical point where a string of 1s becomes a string of 0s, the dual-control zero-loss switch
    Figure PCTCN2022103359-appb-100052
    The conduction condition is: low-off high-pass end
    Figure PCTCN2022103359-appb-100053
    And high-off low-pass end
    Figure PCTCN2022103359-appb-100054
    That is, only
    Figure PCTCN2022103359-appb-100055
    Satisfy
    Figure PCTCN2022103359-appb-100056
    and
    Figure PCTCN2022103359-appb-100057
    For other dual-control zero-loss switches, either the upper and lower control words are all 1, or the upper and lower control words are all 0, which does not meet the conduction condition;
    Figure PCTCN2022103359-appb-100058
    Turn-on will bridge the potential
    Figure PCTCN2022103359-appb-100059
    Take it out and send it to the public output terminal BUS λ , and then send it to the subtrahend end of the summer ∑ λ , and the summer ∑ λ for
    Figure PCTCN2022103359-appb-100060
    After the operation, a value less than ΔV is obtained, which is named as the mantissa voltage
    Figure PCTCN2022103359-appb-100061
    Then it is amplified by 2 qλ times through the amplifier AM λ , and the
    Figure PCTCN2022103359-appb-100062
    Expand to the voltage range of (-V REF ~V REF ), and become the input signal U (λ+1)y of the next stage SADC λ+1 ;
    这样，从α级开始，一级接一级往后转换，最后得到一个n位的数字信号。In this way, starting from the alpha level, one level after another is converted backwards, and finally an n-bit digital signal is obtained.
  10. 一种包括权利要求9所述零损开关的桥电位ADC，其特征在于，A bridge potential ADC comprising the zero-loss switch described in claim 9, characterized in that,
    所述桥电位
    Figure PCTCN2022103359-appb-100063
    的提取模块包括一个q λ位零损多路开关；所述q λ位零损多路开关包括一个q λ位译码器、一个零损开关链
    Figure PCTCN2022103359-appb-100064
    其各个零损开关输出端连接到公共输出端BUS λ；     The bridge potential
    Figure PCTCN2022103359-appb-100063
    The extraction module includes a q λ -bit zero-loss multiplexer; the q λ -bit zero-loss multiplexer includes a q λ -bit decoder, a zero-loss switch chain
    Figure PCTCN2022103359-appb-100064
    Each of its zero-loss switch output terminals is connected to the common output terminal BUS λ ;
    所述零损开关链的各个零损开关的输入端、所述比较器链各个比较器的反相输入端、所述基准 电阻链的各个基准电位点，三者的各个端或点按照下标的对应关系进行连接。The input terminals of each zero-loss switch of the zero-loss switch chain, the inverting input terminals of each comparator of the comparator chain, and each reference potential point of the reference resistance chain, each terminal or point of the three is according to the subscript Corresponding relationship is connected.
  11. 一种包括权利要求7所述零损多路开关的桥电位式DAC，其特征在于，A bridge potential type DAC comprising the zero-loss multi-way switch described in claim 7, characterized in that,
    一个n位DAC由m个子级SDAC和一个比例求和运放构成，m个子级SDAC(α级、β级、γ级、…、m级)的位数分别为(q α、q β、q γ、…、q m)，其中，m为末级，n＝q α+q β+q γ+…+q m；所述比例求和运放中，(α级、β级、γ级、…、m级)的权计算器(AW α、AW β、AW γ、…、AW m)，权计算器放大倍数分别为(AW α、AW β、AW γ、…、AW m)，以AW α为基准，令 An n-bit DAC is composed of m sub-level SDACs and a proportional summation op amp. The number of bits of m sub-level SDACs (α level, β level, γ level, ..., m level) are (q α , q β , q γ ,...,q m ), wherein, m is the final stage, n=q α +q β +q γ +...+q m ; in the proportional summation operational amplifier, (α level, β level, γ level, ..., level m) weight calculator (AW α , AW β , AW γ , ..., AW m ), the magnifications of the weight calculator are (AW α , AW β , AW γ , ..., AW m ), with AW α as the benchmark, let
    AW β/AW α＝1/2 qα、AW γ/AW α＝1/2 qα+qβ、…、AW m/AW α＝1/2 qα+qβ+□+q(m-1) AW β /AW α = 1/2 qα , AW γ /AW α = 1/2 qα+qβ , ..., AW m /AW α = 1/2 qα+qβ+□+q(m-1)
    所述第λ子级SDAC λ，其位数为q λ，SDAC λ包含一个q λ位多路开关和一个q λ位基准电阻链；所述基准电位链各电阻相等，共2 qλ个等间距的基准电位点
    Figure PCTCN2022103359-appb-100065
    所述多路开关由一个q λ位译码器和一个q λ位零损开关链
    Figure PCTCN2022103359-appb-100066
    构成，各个零损开关的输入端按顺序对应下标连接到所述基准电位点，所有零损开关的输出端连接到第λ级公共输出端BUS λ；     The number of digits of the λth sub-stage SDAC λ is q λ , and SDAC λ includes a q λ bit multiplexer and a q λ bit reference resistor chain; the resistances of the reference potential chain are equal, a total of 2 qλ equidistant The reference potential point of
    Figure PCTCN2022103359-appb-100065
    The multiplexer consists of a q λ bit decoder and a q λ bit lossless switch chain
    Figure PCTCN2022103359-appb-100066
    Composition, the input ends of each zero-loss switch are connected to the reference potential point corresponding to the subscript in order, and the output ends of all zero-loss switches are connected to the λ-level common output terminal BUS λ ;
    各级SDAC λ的(BUS α、BUS β、BUS γ、……、BUS λ)分别送入对应下标的权计算器(AW α、AW β、AW γ、…、AW m)，各个权计算器汇聚到求和器∑ λ进行求和，实现DA转换 The SDAC λ at all levels (BUS α , BUS β , BUS γ , ..., BUS λ ) are respectively sent to the weight calculators (AW α , AW β , AW γ , ..., AW m ) corresponding to the subscripts, each weight calculator Converge to the summer ∑ λ for summing to realize DA conversion
    当SDAC λ接收到一个数字信号时，所述译码器会在所述2 qλ个零损开关中唯一的选通一个，该零损开关将所连接的基准电位取出，该基准电位是数字信号和模拟信号的桥梁，命名为桥电位
    Figure PCTCN2022103359-appb-100067
    桥电位
    Figure PCTCN2022103359-appb-100068
    被取出后送入所述公共输出端，实现该子级SDAC λ的DA转换；     When SDAC λ receives a digital signal, the decoder will only select one of the 2 qλ zero-loss switches, and the zero-loss switch will take out the connected reference potential, which is a digital signal and the bridge of the analog signal, named bridge potential
    Figure PCTCN2022103359-appb-100067
    bridge potential
    Figure PCTCN2022103359-appb-100068
    After being taken out, it is sent to the common output terminal to realize the DA conversion of the sub-level SDAC λ ;
    用这种方法，获得α级、β级、γ级、…、m级的桥电位分别为
    Figure PCTCN2022103359-appb-100069
    各级桥电位的权是不同的，在对各级桥电位进行权运算后相加，就得到了DA转换的总输出电压V out；权计算以及相加的电路可以采用比例求和运放；     In this way, the bridge potentials of α-level, β-level, γ-level, ..., m-level are obtained respectively
    Figure PCTCN2022103359-appb-100069
    The weights of the bridge potentials at all levels are different. After adding the weights of the bridge potentials at all levels, the total output voltage V out of the DA conversion is obtained; the weight calculation and addition circuits can use proportional summation op amps;
    Figure PCTCN2022103359-appb-100070
    Figure PCTCN2022103359-appb-100070
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Citations (4)

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US20140266840A1 (en) * 2013-03-14 2014-09-18 Linear Technology Corporation Output stage with fast feedback for driving adc
CN204539123U (en) * 2015-04-08 2015-08-05 南京华士电子科技有限公司 Novel VI converts analogue quantity output circuit
CN110635770A (en) * 2018-06-24 2019-12-31 陈启星 Sampling holder for controlling on-off of input amplifier signal loop by power switch
CN210431372U (en) * 2019-08-29 2020-04-28 华南理工大学 Narrow pulse peak value sampling hold circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140266840A1 (en) * 2013-03-14 2014-09-18 Linear Technology Corporation Output stage with fast feedback for driving adc
CN204539123U (en) * 2015-04-08 2015-08-05 南京华士电子科技有限公司 Novel VI converts analogue quantity output circuit
CN110635770A (en) * 2018-06-24 2019-12-31 陈启星 Sampling holder for controlling on-off of input amplifier signal loop by power switch
CN210431372U (en) * 2019-08-29 2020-04-28 华南理工大学 Narrow pulse peak value sampling hold circuit

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