CN115204097A - 32-bit high-precision DAC layout structure design method - Google Patents
32-bit high-precision DAC layout structure design method Download PDFInfo
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- CN115204097A CN115204097A CN202210901677.7A CN202210901677A CN115204097A CN 115204097 A CN115204097 A CN 115204097A CN 202210901677 A CN202210901677 A CN 202210901677A CN 115204097 A CN115204097 A CN 115204097A
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- 238000013461 design Methods 0.000 title claims abstract description 17
- 238000003491 array Methods 0.000 claims abstract description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 10
- 238000011161 development Methods 0.000 abstract description 2
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- 238000006243 chemical reaction Methods 0.000 description 2
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention relates to the technical field of integrated circuit development, in particular to a 32-bit high-precision DAC layout structure design method, wherein the DAC layout structure comprises a plurality of directly connected poly resistors, an I-path switch and a Q-path switch, the I-path switch and the Q-path switch are vertically symmetrical about the poly resistors and are connected with corresponding poly resistors, and the I-path switch and the Q-path switch are 32-bit switch arrays. The invention can effectively reduce parasitic and layout areas caused by routing, improve the matching of the switch tube and reduce process mismatch, thereby realizing the high-precision design target of the DAC.
Description
Technical Field
The invention relates to the technical field of integrated circuit development, in particular to a 32-bit high-precision DAC layout structure design method.
Background
Digital-to-analog converters, i.e. D/a converters, DAC for short, are devices that convert digital signals into analog signals and are widely used in digital computer technology, communication and detection. The DAC conversion accuracy is mainly affected by gain error, offset error, differential non-linear error (DNL), and integral non-linear error (INL). However, the layout connection line of the layout directly affects the performance index of the DAC, and as the DAC is widely used in the field of digital communication, the requirement for the layout of the DAC is higher and higher. The common DAC with the switch resistor array structure mostly adopts a layout mode of parallel arrangement of resistors and parallel arrangement of adjacent switch tubes to realize a DAC layout, so that connecting lines between the resistors and the switch tubes are long no matter between the switch tubes or between the resistors, parasitic resistance is large, the matching of the switch tubes is poor, and differential nonlinear error (DNL) and integral nonlinear error (INL) of the DAC are influenced.
As shown in fig. 5, if the Poly resistors are connected by the first Metal layer (Metal 1), the Parasitic resistors (Parasitic Res, metal trace resistors) and the Poly resistors (Poly Res) presented on the left side of fig. 5 are connected in series, and the Parasitic resistance causes integral nonlinear error and differential nonlinear error.
Disclosure of Invention
The invention provides a 32-bit high-precision DAC layout structure design method, which can realize the high-precision design target of a DAC.
In order to realize the purpose of the invention, the technical scheme adopted by the design is as follows: a design method for a 32-bit high-precision DAC layout structure comprises a plurality of directly connected poly resistors, an I-way switch and a Q-way switch, wherein the I-way switch and the Q-way switch are vertically symmetrical about the poly resistors and are connected with the corresponding poly resistors, and the I-way switch and the Q-way switch are 32-bit switch arrays.
As an optimized scheme of the invention, the I-path switch and the Q-path switch are both tree-type circuits, the I-path switch and the Q-path switch respectively comprise a first-stage 32 switch tubes, a second-stage 16 switch tubes, a third-stage 8 switch tubes, a fourth-stage 4 switch tubes and a fifth-stage 2 switch tubes, the first-stage 32 switch tubes and the second-stage switch tubes are in a group and are respectively connected with the second-stage 16 switch tubes, the second-stage 16 switch tubes and the second-stage switch tubes are in a group and are respectively connected with the third-stage 8 switch tubes, the third-stage 8 switch tubes and the fourth-stage 4 switch tubes are in a group and are respectively connected with the fourth-stage 4 switch tubes, and the fourth-stage 4 switch tubes and the second-stage 4 switch tubes are in a group and are respectively connected with the fifth-stage 2 switch tubes.
As an optimization scheme of the invention, the first-stage 32 switching tubes of the I-path switch comprise a 101 th switching tube and a 102 th switching tube, the first-stage 32 switching tubes of the Q-path switch comprise a 101 th switching tube and a 102 th switching tube, a plurality of directly connected poly resistors comprise resistors R0, one ends of the resistors R0 are connected with the 101 th switching tube and the 101 th switching tube, and the other ends of the resistors R0 are connected with the 102 th switching tube and the 102 th switching tube.
As an optimized scheme of the invention, 5 dummy switch tubes DM are respectively arranged at the left side and the right side of the I-path switch and the Q-path switch.
The invention has the positive effects that: 1) The invention can effectively reduce the parasitic area and the layout area caused by wiring, improve the matching of the switch tube and reduce the process mismatch, thereby realizing the high-precision design target of the DAC.
2) The whole DAC is vertically symmetrical in the X direction and horizontally symmetrical in the Y direction, and the whole DAC is simple and compact in layout, high in matching performance and small in process mismatch.
Drawings
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
FIG. 1 is a layout and wiring schematic diagram of the DAC layout structure design method of the present invention;
FIG. 2 is a schematic diagram of a DAC layout method of the present invention;
FIG. 3 is a schematic diagram of a local layout of a DAC layout according to the present invention;
FIG. 4 is a schematic diagram of poly resistor layout of a DAC layout according to the present invention;
fig. 5 is a schematic diagram of a poly resistor layout of a conventional DAC layout.
Detailed Description
As shown in FIG. 1, the invention discloses a design method of a 32-bit high-precision DAC layout structure, the DAC layout structure comprises a plurality of directly connected poly resistors, I-path switches and Q-path switches, the I-path switches and the Q-path switches are vertically symmetrical about the poly resistors and are connected with the corresponding poly resistors, and the I-path switches and the Q-path switches are 32-bit switch arrays.
As shown in fig. 2, the I-way switch and the Q-way switch are both tree-type circuits, the I-way switch and the Q-way switch each include 32 first-stage switching tubes, 16 second-stage switching tubes, 8 third-stage switching tubes, 4 fourth-stage switching tubes and 2 fifth-stage switching tubes, two first-stage switching tubes of 32 first-stage switching tubes are connected with 16 second-stage switching tubes respectively for one set, two second-stage switching tubes of 16 second-stage switching tubes are connected with 8 third-stage switching tubes respectively for one set, two third-stage switching tubes of 8 third-stage switching tubes are connected with 4 fourth-stage switching tubes respectively for one set, and two fourth-stage switching tubes of 4 fourth-stage switching tubes are connected with 2 fifth-stage switching tubes respectively for one set.
32 switch tubes of first order of I way switch include 101 st switch tube and 102 th switch tube, 32 switch tubes of first order of Q way switch include 101' th switch tube and 102 th switch tube, and a plurality of direct continuous poly resistance include resistance R0, and resistance R0's one end all links to each other with 101 th switch tube and 101' th switch tube, and resistance R0's the other end all links to each other with 102 th switch tube and 102' th switch tube.
The left and right sides of the I-path switch and the Q-path switch are respectively provided with 5 dummy switching tubes DM.
The input signal generates required resistance voltage division by regulating and controlling the 32-bit switch array, the function of digital-to-analog conversion is realized, the whole layout structure is symmetrical up and down about the resistance, and the 32-bit digital signal is converted into analog signals I _ outp output and Q _ outp output by the resistance voltage division, so that a synchronous group mode can be adopted in the layout, the consistency of the switch of the I path and the switch of the Q path can be ensured, and the working efficiency can be improved. A single-view I-path switch and a tree-type circuit are characterized in that switch tubes are named by 1,2,3,4,5 from bottom to top respectively, the first switch tube at 1 represents 32 switch tubes at the first level of the bottom layer, the second switch tube at 2 represents 16 switch tubes at the second level of the bottom layer, the third switch tube at the middle layer represents 8 switch tubes at 3, the fourth switch tube at the second upper level represents 4 switch tubes at 4, and the fifth switch tube at the top layer represents 2 switch tubes at 5, the layout mode of the invention is shown in figure 2, 101, 102, 201, 202, 103, 104, 301, 302, 105, 106, 203, 204, 107, 108, 401, 402, 109, 110, 205, 206, 111, 112, 303, 304, 113, 114, 207, 208, 115, 116, 501, 502, 117, 118, 209, 210, 119, 305, 306, 121, 122, 211, 212, 123, 124, 403, 404, 125, 126, 213, 214, 127, 128, 307, 308, 129, 130, 215, 216, 131, 132, one resistance under each set of switching tubes. The left side and the right side of the outermost switch tube are respectively added with 5 dummy switch tubes DM, so that the influence of noise on the resistance can be reduced, the whole I-path switch Guan Guancheng is centrosymmetric and matched, and the process mismatch is effectively reduced.
The layout of the Q route and the I route, 101', 102', 201 ', 202 ', 103 ', 104 ', 301 ', 302 ', 105 ', 106 ', 203 ', 204 ', 107 ', 108 ', 401 ', 402
109`_110`、205`_206`、111`_112`、303`_304`、113`_114`、207`_208`、115`_116`、501`_502`、117`_118`、209`_210`、
119 ', 305 ', 306 ', 121 ', 122 ', 211 ', 212 ', 123 ', 124 ', 403 ', 404 ', 125 ', 126 ', 213 ', 214 ', 127 ', 128 ', 307 ', 308 ', 129 ' 130 ', 215 ', 216 ' and 131 ' 132 ', 5 dummy switching tubes DM are respectively arranged on the left side and the right side of the outermost switching tube, and a resistor is arranged below each group of the dummy switching tubes DM. The whole Q-way opening Guan Guancheng is centrosymmetrically matched, and the process mismatch is effectively reduced. The entire DAC is vertically symmetric about the X-axis.
As shown in fig. 3, the first-stage 32 switching tubes of the I-path switch include a 101 th switching tube and a 102 th switching tube, the first-stage 32 switching tubes of the Q-path switch include a 101 th switching tube and a 102 th switching tube, the plurality of directly connected poly resistors include a resistor R0, one end of the resistor R0 is connected with the 101 th switching tube and the 101 th switching tube, and the other end of the resistor R0 is connected with the 102 th switching tube and the 102 th switching tube. The resistor and the switch tube are connected simply, and parasitic electricity caused by wiring is reduced. The wiring is simple, the wiring is short, and the parasitic resistance is small.
As shown in fig. 4, the invention adopts a direct connection manner between the Poly resistors presented on the right side of fig. 4 for the parallel arrangement structure of the resistors in fig. 1, specifically as shown in fig. 2, so that the parasitic resistors are connected in parallel with the Poly resistors, and the parasitic resistances cause only small integral non-linearity errors and differential non-linearity errors.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. A32-bit high-precision DAC layout structure design method is characterized by comprising the following steps: the DAC layout structure comprises a plurality of directly connected poly resistors, an I-path switch and a Q-path switch, wherein the I-path switch and the Q-path switch are vertically symmetrical about the poly resistors and are connected with the corresponding poly resistors, and the I-path switch and the Q-path switch are 32-bit switch arrays.
2. The design method of the 32-bit high-precision DAC layout structure according to claim 1, characterized in that: the I way switch and the Q way switch be tree type circuit, I way switch and Q way switch all include 32 switch tubes of first order, 16 switch tubes of second level, 8 switch tubes of third level, 4 switch tubes of fourth level and 2 switch tubes of fifth level, two switch tubes of 32 switch tubes of first order are a set of and link to each other with 16 switch tubes of second level respectively, two switch tubes of 16 switch tubes of second level are a set of and link to each other with 8 switch tubes of third level respectively, two switch tubes of 8 switch tubes of third level are a set of and link to each other with 4 switch tubes of fourth level respectively, two switch tubes of 4 switch tubes of fourth level are a set of and link to each other with 2 switch tubes of fifth level respectively.
3. The design method of the 32-bit high-precision DAC layout structure according to claim 2, wherein: 32 switch tubes of first order of I way switch include 101 st switch tube and 102 th switch tube, 32 switch tubes of first order of Q way switch include 101' th switch tube and 102 th switch tube, and a plurality of direct continuous poly resistance include resistance R0, and resistance R0's one end all links to each other with 101 th switch tube and 101' th switch tube, and resistance R0's the other end all links to each other with 102 th switch tube and 102' th switch tube.
4. The design method of the 32-bit high-precision DAC layout structure according to claim 3, wherein the design method comprises the following steps: the left and right sides of the I-path switch and the Q-path switch are respectively provided with 5 dummy switching tubes DM.
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| CN202210901677.7A CN115204097A (en) | 2022-07-28 | 2022-07-28 | 32-bit high-precision DAC layout structure design method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116306466A (en) * | 2023-05-18 | 2023-06-23 | 北京紫光青藤微系统有限公司 | Layout method and layout structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116306466A (en) * | 2023-05-18 | 2023-06-23 | 北京紫光青藤微系统有限公司 | Layout method and layout structure |
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