CN110460322B - Narrow pulse peak value sampling hold circuit and control method thereof - Google Patents
Narrow pulse peak value sampling hold circuit and control method thereof Download PDFInfo
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Abstract
The invention discloses a narrow pulse peak value sampling and holding circuit and a control method thereof, wherein the narrow pulse peak value sampling and holding circuit comprises a peak value signal sampling and holding part, a comparator control part, a capacitor voltage compensation part, a following output part and a DSP signal control and processing part, wherein the comparator control part, the capacitor voltage compensation part, the following output part and the DSP signal control and processing part are respectively connected with the peak value signal sampling and holding part; the comparator control part comprises a second operational amplifier and a fifth resistor, and is used for controlling a second analog switch of the peak signal sampling and holding part to be turned off at a peak value and cutting off a leakage current channel of a sampling capacitor of the peak signal sampling and holding part; the capacitor voltage compensation part comprises a first junction field effect transistor, a third resistor and a first capacitor and is used for compensating the voltage loss of the sampling capacitor caused by the charging of the junction capacitor of the second junction field effect transistor of the peak signal sampling and holding part. The circuit has the characteristics of high speed and high precision, and is suitable for occasions for extracting high-speed narrow pulse peaks.
Description
Technical Field
The invention relates to the technical field of junction temperature monitoring of power devices, in particular to a narrow pulse peak value sampling hold circuit and a control method thereof.
Background
In the on-line monitoring of the junction temperature of a power device, the junction temperature is extracted by an electrical parameter method. Wherein the parasitic inductance of the source electrode is related to the junction temperature of the induced voltage peak generated at the time of switching off the device. The turn-off time of the common device is hundreds of nanoseconds, the turn-off time of the high-speed device is even lower than tens of nanoseconds, the rise time of pulse peak generated during the turn-off time is shorter, and the amplitude is also changed, so that the design of the nanosecond high-speed narrow pulse peak value sample-hold circuit with high accuracy is one of the necessary conditions for realizing the on-line monitoring of junction temperature by using the method.
However, the existing peak sample hold circuit has the defects of insufficient bandwidth, slow tracking speed and insufficient precision. In order to meet the speed requirement, the adopted sampling capacitor is mostly a pF-level small capacitor, and after the peak value is reached, the parasitic capacitance of the diode can cause the leakage of the charge of the diode, the voltage held by the sampling capacitor can be reduced to a certain extent, and the accuracy of the sampling peak value is affected.
Disclosure of Invention
The invention aims to overcome the defects and shortcomings of the prior art, and provides a narrow pulse peak value sampling and holding circuit and a control method thereof, which have the characteristics of high speed and high precision and are suitable for occasions of extracting high-speed narrow pulse peak values.
In order to achieve the above purpose, the technical scheme provided by the invention is as follows: the narrow pulse peak value sampling and holding circuit comprises a peak value signal sampling and holding part, a comparator control part, a capacitor voltage compensation part, a following output part and a DSP signal control and processing part, wherein the comparator control part, the capacitor voltage compensation part, the following output part and the DSP signal control and processing part are respectively connected with the peak value signal sampling and holding part; the comparator control part comprises a second operational amplifier and a fifth resistor, and is used for controlling a second analog switch of the peak signal sampling and holding part to be turned off at a peak value, cutting off a leakage current channel of a sampling capacitor of the peak signal sampling and holding part and reducing voltage loss, and the capacitor voltage compensation part comprises a first junction field effect transistor, a third resistor and a first capacitor, and is used for compensating the voltage loss on the sampling capacitor caused by the charging of the junction capacitor of the second junction field effect transistor of the peak signal sampling and holding part; the non-inverting input end of the second operational amplifier is respectively connected with the first analog switch, one end of the first resistor and one end of the second resistor of the peak signal sampling and holding part, the inverting input end of the second operational amplifier is respectively connected with the inverting input end of the first operational amplifier, one end of the sixth resistor and the grid electrode of the first junction field effect transistor of the peak signal sampling and holding part, the output end of the second operational amplifier is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with the control end of the second analog switch of the peak signal sampling and holding part; the grid electrode of the first junction field effect transistor is respectively connected with the inverting input end of the second operational amplifier, the inverting input end of the first operational amplifier and one end of the sixth resistor, the source electrode and the drain electrode of the first junction field effect transistor are respectively connected with one end of the third resistor, the other end of the third resistor is connected with one end of the first capacitor, and the other end of the first capacitor is respectively connected with one end of the second analog switch of the peak signal sampling and holding part and the output end of the first operational amplifier.
Further, the peak signal sampling and holding part performs peak sampling on the narrow pulse input signal Vin, and comprises a first analog switch, a first resistor, a second resistor, a first operational amplifier, a second analog switch, a fourth resistor, a second junction field effect transistor, a sixth resistor, a third analog switch and a second capacitor serving as a sampling capacitor, and the following output part comprises a seventh resistor, a first triode and an eighth resistor; the on and off of the first analog switch and the third analog switch are controlled by a DSP signal control processing part through a DSP chip, the narrow pulse input signal Vin is connected with one end of the first analog switch, the other end of the first analog switch is respectively connected with one end of a first resistor, one end of a second resistor and an in-phase input end of a second operational amplifier, the other end of the first resistor is connected with the ground, the other end of the second resistor is connected with the in-phase input end of the first operational amplifier, the inverting input end of the first operational amplifier is respectively connected with the inverting input end of the second operational amplifier, the grid electrode of a first junction field effect transistor and one end of a sixth resistor, the output end of the first operational amplifier is respectively connected with one end of the second analog switch and one end of the first capacitor, the other end of the second analog switch is connected with one end of the fourth resistor, the other end of the fourth resistor is connected with the grid electrode of the second junction field effect transistor, the source electrode and the drain electrode of the second junction field effect transistor are respectively connected with the third analog switch, one end of the seventh capacitor and the other end of the second resistor is connected with the eighth resistor and the eighth resistor; one end of the seventh resistor is connected with the source electrode and the drain electrode of the second junction field effect transistor, one end of the third analog switch and one end of the second capacitor, the other end of the seventh resistor is connected with the base electrode of the first triode, the collector electrode of the first triode is connected with the ground, the emitting stage of the first triode is connected with one end of the eighth resistor, the other end of the eighth resistor is connected with the sampled output voltage Vout, and the sampled output voltage Vout is sampled and stored through the ADC module of the DSP chip.
Further, the first operational amplifier is a transconductance operational amplifier.
Further, the second operational amplifier is a low-delay high-speed comparator.
The invention provides a control method of the narrow pulse peak value sampling hold circuit, firstly, a DSP signal control processing part outputs a control signal (Signal input control) to control a first analog switch to be opened, when a narrow pulse input signal Vin rises, the voltage of an in-phase end of a second operational amplifier is larger than the voltage of an opposite-phase end, a high level is output to control the second analog switch to be opened, meanwhile, the voltage of the in-phase end of the first operational amplifier is larger than the voltage of the opposite-phase end, a transconductance operational amplifier outputs forward current, a second junction field effect transistor is conducted to charge a second capacitor, at the moment, the voltage of the opposite-phase end of the first operational amplifier is smaller than the voltage of an output end, the first junction field effect transistor is cut off, and the junction capacitors of the first capacitor and the first junction field effect transistor are reversely charged to store charges; when the narrow pulse input signal Vin is in a falling stage, the input voltage is smaller than the output voltage, the in-phase end voltage of the first operational amplifier is smaller than the anti-phase end voltage, the output current of the transconductance operational amplifier is reversed, the second junction field effect transistor is cut off, the voltage of the second capacitor is kept at a peak value, the second capacitor charges the junction capacitance of the second junction field effect transistor at the moment to cause voltage drop, the junction capacitance of the first junction field effect transistor charges the junction capacitance of the second junction field effect transistor through a compensation loop at the moment, the reduced charge of the second capacitor caused by the existence of the junction capacitance of the second junction field effect transistor is compensated, the voltage drop of the second capacitor is reduced, the precision of a sampling peak value is improved, meanwhile, the in-phase end voltage of the second operational amplifier is smaller than the anti-phase end voltage, the output low level is output, the second analog switch is turned off, a channel of the reverse current of the second junction field effect transistor is cut off, the leakage current of the second capacitor is reduced, the voltage drop is reduced, the precision of the sampling peak value is further improved, at the moment, the voltage on the junction capacitance of the first junction field effect transistor is output after the junction capacitance follows the output part, the output voltage Vout is controlled by the compensation loop, the voltage Vout is controlled by the DSP, the DSP part, the voltage is controlled by the DSP part to control the ADC part, the sampling peak value is controlled by the DSP, the signal is controlled by the DSP to carry out, the signal hold, and the signal is sampled by the signal, and the signal is processed, and the signal is sampled by the peak, and is processed, and the signal is output.
Compared with the prior art, the invention has the following advantages and beneficial effects:
1. the circuit adopts the transconductance operational amplifier, has high bandwidth, large output impedance and large output current, and meets the requirement of rapidly charging the sampling capacitor.
2. The circuit of the invention adopts the junction field effect transistor to replace the Schottky diode, has the characteristics of low junction capacitance and low leakage current, and reduces the loss of charge of the sampling holding capacitor.
3. The circuit adopts the low-delay high-speed comparator to control the analog switch to be turned off at the peak value, cuts off the leakage current channel of the sampling holding capacitor, and reduces the voltage loss.
4. The circuit adopts the compensation capacitor to compensate the voltage loss of the sampling capacitor caused by the junction capacitor charging of the junction field effect transistor, and improves the sampling precision.
Therefore, the circuit has the characteristics of high speed and high precision, and is suitable for occasions of extracting high-speed narrow pulse peaks.
Drawings
FIG. 1 is a schematic diagram of a narrow pulse peak sample-and-hold circuit; in the figure, signal input control is a control signal sent by the DSP and used for controlling the input and disconnection of the input signal Vin, and controlling the first analog switch S1; the hold control is a control signal generated by the second operational amplifier U2 and used for controlling the on-off of the second analog switch S2; the clear signal is a control signal sent by the DSP to control the on/off of the third analog switch S3, and is used to clear or maintain the voltage on the second capacitor C2.
Fig. 2 is a waveform diagram of the input signal Vin, the output terminal voltage of the second op-amp U2, and the output signal Vout.
Detailed Description
The invention will be further illustrated with reference to specific examples.
As shown in fig. 1, the narrow pulse peak sample hold circuit provided in this embodiment includes a peak signal sample hold section 1, a comparator control section 2, a capacitor voltage compensation section 3, a follower output section 4, and a DSP signal control processing section 5, the comparator control section 2, the capacitor voltage compensation section 3, the follower output section 4, and the DSP signal control processing section 5 being connected to the peak signal sample hold section 1, respectively; the peak signal sampling and holding part 1 performs peak sampling on a narrow pulse input signal Vin, and comprises a first analog switch S1, a first resistor R1, a second resistor R2, a first operational amplifier U1, a second analog switch S2, a fourth resistor R4, a second junction field effect transistor J1, a sixth resistor R6, a third analog switch S3 and a second capacitor C2 serving as a sampling capacitor; the following output part comprises a seventh resistor R7, a first triode U3 and an eighth resistor R8 and is used for carrying out following output on the sampling capacitor voltage and isolating the influence of the output voltage on the front stage; the comparator control part 2 comprises a second operational amplifier U2 and a fifth resistor R5, and is used for controlling the second analog switch S2 to be turned off at the peak value, cutting off a leakage current channel of the sampling capacitor and reducing voltage loss; the capacitance-voltage compensation part 3 comprises a first junction field effect transistor J2, a third resistor R3 and a first capacitor C1, and is used for compensating voltage loss on a sampling capacitor caused by the charging of the junction capacitor of the second junction field effect transistor J1 of the peak signal sampling and holding part; the on and off of the first analog switch S1 and the third analog switch S3 are controlled by a DSP signal control processing part through a DSP chip, the first operational amplifier U1 is a transconductance operational amplifier, and the second operational amplifier U2 is a low-delay high-speed comparator; the non-inverting input end of the second operational amplifier U2 is respectively connected with the first analog switch S1, one end of the first resistor R1 and one end of the second resistor R2, the inverting input end of the second operational amplifier U2 is respectively connected with the inverting input end of the first operational amplifier U1, one end of the sixth resistor R6 and the grid electrode of the first junction field effect transistor J2, the output end of the second operational amplifier U2 is connected with one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected with the control end of the second analog switch S2; the grid electrode of the first junction field effect transistor J2 is respectively connected with the inverting input end of the second operational amplifier U2, the inverting input end of the first operational amplifier U1 and one end of the sixth resistor R6, the source electrode and the drain electrode of the first junction field effect transistor J2 are respectively connected with one end of the third resistor R3, the other end of the third resistor R3 is connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is respectively connected with one end of the second analog switch S2 and the output end of the first operational amplifier U1; the narrow pulse input signal Vin is connected with one end of a first analog switch S1, the other end of the first analog switch S1 is respectively connected with one end of a first resistor R1, one end of a second resistor R2 and the in-phase input end of a second operational amplifier U2, the other end of the first resistor R1 is connected with the ground, the other end of the second resistor R2 is connected with the in-phase input end of the first operational amplifier U1, the inverting input end of the first operational amplifier U1 is respectively connected with the inverting input end of the second operational amplifier U2, the grid electrode of a first junction field effect transistor J2 and one end of a sixth resistor R6, the output end of the first operational amplifier U1 is respectively connected with one end of the second analog switch S2 and one end of a first capacitor C1, the other end of the second analog switch S2 is connected with one end of a fourth resistor R4, the other end of the fourth resistor R4 is connected with the grid electrode of the second junction field effect transistor J1, the source electrode and the drain electrode of the second junction field effect transistor J1 are respectively connected with the third analog switch S3 and the other end of the third capacitor C3 and the third capacitor R3 and the other end of the third capacitor R3 and the eighth resistor R8 is connected with the other end of the third resistor R3 and the third capacitor R6 is connected with the other end of the third resistor is connected with the third resistor C3; one end of the seventh resistor R7 is connected with the source electrode and the drain electrode of the second junction field effect tube J1, one end of the third analog switch S3 and one end of the second capacitor C2, the other end of the seventh resistor R7 is connected with the base electrode of the first triode U3, the collector electrode of the first triode U3 is connected with the ground, the emitting stage of the first triode U3 is connected with one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected with the sampled output voltage Vout, and the sampled output voltage Vout is sampled and stored through the ADC module of the DSP chip.
As shown in fig. 2, waveforms of the input voltage signal Vin, the output voltage VCOMP of the second op amp U2, and the output voltage Vout are given, in which the U2 output voltage VCOMP is high before the input signal Vin reaches the first peak, and becomes low after reaching the peak, the output voltage Vout is maintained at the first peak, and similarly, the output voltage Vout is maintained at the second peak after the input signal Vin reaches the second peak.
The following is the working principle of the narrow pulse peak value sample-hold circuit according to this embodiment, which is specifically as follows:
the DSP signal control processing part 5 outputs a control signal (Signal input control) to control the first analog switch S1 to be turned on, when the narrow pulse input signal Vin rises, the in-phase terminal voltage of the second operational amplifier U2 is greater than the reverse-phase terminal voltage, a high level is output to control the second analog switch S2 to be turned on, meanwhile, the in-phase terminal voltage of the first operational amplifier U1 is greater than the reverse-phase terminal voltage, the transconductance operational amplifier outputs forward current, the second junction field effect transistor J1 is conducted to charge the second capacitor C2, at the moment, the reverse-phase terminal voltage of the first operational amplifier U1 is less than the output terminal voltage, the first junction field effect transistor J2 is turned off, and the junction capacitors of the first capacitor C1 and the first junction field effect transistor J2 are reversely charged to store charges; when the narrow pulse input signal Vin is in the falling stage, the input voltage is smaller than the output voltage, the in-phase terminal voltage of the first operational amplifier U1 is smaller than the opposite-phase terminal voltage, the transconductance operational amplifier output current is reversed, the second junction field effect transistor J1 is cut off, the voltage of the second capacitor C2 is kept at the peak value, the second capacitor C2 charges the junction capacitance of the second junction field effect transistor J1 to cause voltage drop, the junction capacitance of the first junction field effect transistor J2 charges the junction capacitance of the second junction field effect transistor J1 through the compensation loop at the moment, the reduced charge of the second capacitor C2 caused by the existence of the junction capacitance of the second junction field effect transistor J1 is compensated, the voltage drop of the second capacitor C2 is reduced, the accuracy of sampling peak values is further improved, simultaneously, the in-phase terminal voltage of the second operational amplifier U2 is smaller than the opposite-phase terminal voltage, a low level is output, the second analog switch S2 is turned off, a channel of reverse current of the second junction field effect transistor J1 is cut off, leakage current of the second capacitor C2 is reduced, voltage drop is reduced, and then accuracy of sampling peak values is improved, at the moment, the voltage on the second capacitor C2 is in a holding stage, the voltage is output through the following output part 4, the output voltage Vout is sampled and stored through an ADC (analog to digital) module of a DSP chip of the DSP signal control processing part, peak value sampling is completed, after sampling is completed, the DSP signal control processing part gives a discharge control signal (clear signal), the third analog switch S3 is turned on, the second capacitor C2 is discharged, and preparation is made for the next peak value sampling and holding.
In summary, compared with the prior art, the invention adopts the transconductance operational amplifier, which has high bandwidth, large output impedance and large output current, and meets the requirement of rapidly charging the sampling capacitor; the junction field effect transistor is adopted to replace the Schottky diode, so that the device has the characteristics of low junction capacitance and low leakage current, the loss of charge of the sampling and holding capacitor is reduced, and the error is reduced; the high-speed comparator is adopted to control the analog switch to be turned off at the peak value, so that a leakage current channel of the sampling holding capacitor is cut off, and the voltage loss is reduced; the compensation loop is adopted to compensate the voltage loss on the sampling capacitor caused by the junction capacitor charging of the junction field effect transistor, so that the sampling precision is improved. Therefore, the circuit has the characteristics of high speed and high precision, is suitable for occasions of extracting high-speed narrow pulse peaks, has practical application value and is worthy of popularization.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, so variations in shape and principles of the present invention should be covered.
Claims (5)
1. The narrow pulse peak sample hold circuit comprises a peak signal sample hold part (1), a comparator control part (2), a capacitor voltage compensation part (3), a following output part (4) and a DSP signal control processing part (5), wherein the comparator control part (2), the capacitor voltage compensation part (3), the following output part (4) and the DSP signal control processing part (5) are respectively connected with the peak signal sample hold part (1); the method is characterized in that: the comparator control part (2) comprises a second operational amplifier (U2) and a fifth resistor (R5), the second analog switch (S2) used for controlling the peak signal sampling and holding part (1) is turned off at the peak value, a leakage current channel of a sampling capacitor of the peak signal sampling and holding part (1) is cut off, voltage loss is reduced, the capacitor voltage compensation part (3) comprises a first junction field effect transistor (J2), a third resistor (R3) and a first capacitor (C1), and the capacitor voltage compensation part is used for compensating the voltage loss on the sampling capacitor caused by junction capacitor charging of the second junction field effect transistor (J1) of the peak signal sampling and holding part (1); the non-inverting input end of the second operational amplifier (U2) is respectively connected with a first analog switch (S1), one end of a first resistor (R1) and one end of a second resistor (R2) of the peak signal sampling and holding part (1), the inverting input end of the second operational amplifier (U2) is respectively connected with the inverting input end of the first operational amplifier (U1) of the peak signal sampling and holding part (1), one end of a sixth resistor (R6) and the grid electrode of a first junction field effect transistor (J2), the output end of the second operational amplifier (U2) is connected with one end of a fifth resistor (R5), and the other end of the fifth resistor (R5) is connected with the control end of the second analog switch (S2) of the peak signal sampling and holding part (1); the grid of first knot type field effect transistor (J2) is connected with the inverting input end of second operational amplifier (U2), the inverting input end of first operational amplifier (U1) and one end of sixth resistor (R6) respectively, the source electrode and the drain electrode of first knot type field effect transistor (J2) are connected with one end of third resistor (R3) respectively, the other end of third resistor (R3) is connected with one end of first electric capacity (C1), the other end of first electric capacity (C1) is connected with one end of second analog switch (S2) and the output of first operational amplifier (U1) of peak signal sample hold part (1) respectively.
2. The narrow pulse peak sample and hold circuit of claim 1, wherein: the peak signal sampling and holding part (1) performs peak sampling on a narrow pulse input signal Vin, and comprises a first analog switch (S1), a first resistor (R1), a second resistor (R2), a first operational amplifier (U1), a second analog switch (S2), a fourth resistor (R4), a second junction field effect transistor (J1), a sixth resistor (R6), a third analog switch (S3) and a second capacitor (C2) serving as a sampling capacitor, and the following output part (4) comprises a seventh resistor (R7), a first triode (U3) and an eighth resistor (R8); the on and off of the first analog switch (S1) and the third analog switch (S3) are controlled by a DSP signal control processing part (5) through a DSP chip, the narrow pulse input signal Vin is connected with one end of the first analog switch (S1), the other end of the first analog switch (S1) is respectively connected with one end of a first resistor (R1), one end of a second resistor (R2) and the non-inverting input end of a second operational amplifier (U2), the other end of the first resistor (R1) is connected with the ground, the other end of the second resistor (R2) is connected with the non-inverting input end of the first operational amplifier (U1), the inverting input end of the first operational amplifier (U1) is respectively connected with one end of a second operational amplifier (U2), the grid electrode of a first junction field effect transistor (J2) and one end of a sixth resistor (R6), the output end of the first operational amplifier (U1) is respectively connected with one end of the second analog switch (S2), the other end of the first capacitor (C1) is connected with the first junction transistor (S2), the drain electrode (S4) is connected with the other end of the fourth resistor (S2), the drain electrode (S2) is connected with the first junction transistor (S2) and the other end of the fourth resistor (S1) is connected with the drain electrode (S1), the other end of the second capacitor (C2) is connected with the other end of the third analog switch (S3) and the ground, and the other end of the sixth resistor (R6) is respectively connected with the emitter of the first triode (U3) and one end of the eighth resistor (R8); one end of the seventh resistor (R7) is connected with a source electrode and a drain electrode of the second junction field effect transistor (J1), one end of the third analog switch (S3) and one end of the second capacitor (C2), the other end of the seventh resistor (R7) is connected with a base electrode of the first triode (U3), a collector electrode of the first triode (U3) is connected with the ground, an emitting stage of the first triode (U3) is connected with one end of the eighth resistor (R8), and the other end of the eighth resistor (R8) is connected with an output voltage Vout of sampling, and the output voltage Vout is sampled and stored through an ADC module of the DSP chip.
3. The narrow pulse peak sample and hold circuit of claim 1, wherein: the first operational amplifier (U1) is a transconductance operational amplifier.
4. The narrow pulse peak sample and hold circuit of claim 1, wherein: the second op-amp (U2) is a low delay high speed comparator.
5. A control method of the narrow pulse peak sample-and-hold circuit according to any one of claims 1 to 4, characterized in that: firstly, a DSP signal control processing part (5) outputs a control signal to control a first analog switch (S1) to be opened, when a narrow pulse input signal Vin rises, the in-phase terminal voltage of a second operational amplifier (U2) is larger than the opposite-phase terminal voltage, a high level is output to control the second analog switch (S2) to be opened, meanwhile, the in-phase terminal voltage of the first operational amplifier (U1) is larger than the opposite-phase terminal voltage, a transconductance operational amplifier outputs forward current, a second junction field effect transistor (J1) is conducted to charge a second capacitor (C2), at the moment, the opposite-phase terminal voltage of the first operational amplifier (U1) is smaller than the output terminal voltage, the first junction field effect transistor (J2) is turned off, and junction capacitors of the first capacitor (C1) and the first junction field effect transistor (J2) are reversely charged to store charges; when the narrow pulse input signal Vin is in a falling stage, the input voltage is smaller than the output voltage, the in-phase end voltage of the first operational amplifier (U1) is smaller than the opposite-phase end voltage, the transconductance operational amplifier outputs current reversely, the second junction field effect transistor (J1) is cut off, the voltage of the second capacitor (C2) is kept at a peak value, the second capacitor (C2) charges the junction capacitor of the second junction field effect transistor (J1) so as to lead to voltage drop, the junction capacitor of the first junction field effect transistor (J2) charges the junction capacitor of the second junction field effect transistor (J1) through a compensation loop so as to compensate the reduced charge of the second capacitor (C2) caused by the existence of the junction capacitor of the second junction field effect transistor (J1) and reduce the voltage drop of the second capacitor (C2), and at the same time, the in-phase terminal voltage of the second operational amplifier (U2) is smaller than the reverse-phase terminal voltage, and outputs a low level, the second analog switch (S2) is turned off, the channel of the reverse current of the second junction field effect transistor (J1) is cut off, the leakage current of the second capacitor (C2) is reduced, the voltage drop is reduced, and the accuracy of the sampling peak value is further improved, at the moment, the voltage on the second capacitor (C2) is output by the following output part (4) in a holding stage, and is an output voltage Vout, the output voltage Vout is sampled and stored by the ADC module of the DSP chip of the DSP signal control processing part (5), the sampling of the peak value is completed, the DSP signal control processing part (5) gives a discharge control signal, the third analog switch (S3) is turned on, and the second capacitor (C2) is discharged to prepare for the next peak sample hold.
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| CN112379179B (en) * | 2020-09-25 | 2024-01-30 | 华东光电集成器件研究所 | Pulse sampling hold circuit with adjustable built-in pulse width |
| CN112787656B (en) * | 2020-12-31 | 2022-11-15 | 重庆西山科技股份有限公司 | Sample-hold control method, device and host |
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| CN203225725U (en) * | 2013-04-14 | 2013-10-02 | 中国科学院近代物理研究所 | Narrow pulse peak value holding device |
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