CN210142495U - Pixel circuit, display panel and display device - Google Patents
Pixel circuit, display panel and display device Download PDFInfo
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- CN210142495U CN210142495U CN201921405751.6U CN201921405751U CN210142495U CN 210142495 U CN210142495 U CN 210142495U CN 201921405751 U CN201921405751 U CN 201921405751U CN 210142495 U CN210142495 U CN 210142495U
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Abstract
The embodiment of the utility model discloses pixel circuit, display panel and display device. The pixel circuit includes: the circuit comprises a scanning signal input end, a data signal input end, a first power supply end, at least two first transistors, a storage module and a driving module; a gate of the first transistor is electrically connected to the scan signal input terminal, a first electrode of the first transistor is electrically connected to the data signal input terminal, and a substrate of the first transistor is electrically connected to the first power terminal; the storage module is electrically connected with a second pole of the first transistor and is used for storing a data signal written into the storage module through the conducted first transistor; the driving module comprises a driving control end, the driving control end is electrically connected with the storage module, and the driving module is used for responding to the data signal to drive the light-emitting device to emit light. The utility model provides the high data signal's transmission rate has solved the not enough problem of scanning time appears in pixel circuit.
Description
Technical Field
The embodiment of the utility model provides a relate to and show technical field, especially relate to a pixel circuit, display panel and display device.
Background
With the continuous development of display technology, the application range of display panels is wider and wider, and the requirements of people on the display panels are higher and higher. The pixel circuit in the display panel plays a very important role in driving the light emitting device to emit light. However, the performance of the conventional pixel circuit is not satisfactory, and as the refresh frequency, the number of gray scales, and the pixel density (pixel Per inc, PPI) increase, the scanning time of the pixel circuit is compressed, and the phenomenon of insufficient scanning time is likely to occur.
SUMMERY OF THE UTILITY MODEL
The embodiment of the utility model provides a pixel circuit, display panel and display device to promote data signal's transmission rate, solve the problem that scanning time is not enough appears in pixel circuit.
In order to achieve the technical purpose, the embodiment of the utility model provides a following technical scheme:
a pixel circuit, comprising: the circuit comprises a scanning signal input end, a data signal input end, a first power supply end, at least two first transistors, a storage module and a driving module;
a gate of the first transistor is electrically connected to the scan signal input terminal, a first electrode of the first transistor is electrically connected to the data signal input terminal, and a substrate of the first transistor is electrically connected to the first power terminal;
the storage module is electrically connected with a second pole of the first transistor and is used for storing a data signal written into the storage module through the conducted first transistor;
the driving module comprises a driving control end, the driving control end is electrically connected with the storage module, and the driving module is used for responding to the data signal to drive the light-emitting device to emit light.
According to the above technical scheme, the embodiment of the utility model provides a through setting up two at least first transistor parallel connection, two at least first transistors open simultaneously promptly and turn-off, have increased data signal transmission channel's width to length ratio to transmission channel's on-resistance has been reduced. And, the substrate of first transistor is connected with first power end electricity, has increased the potential difference of substrate in other words, has strengthened the substrate and has adsorbed the minority carrier's ability, has accelerated the rate of motion of minority carrier, helps shortening the formation time of conducting channel, consequently, the embodiment of the utility model provides a speed of switching on of first transistor has been accelerated to the response speed of transmission gate has been accelerated, data signal's transmission rate has been accelerated, the speed that data signal transmitted drive module's drive control end has been accelerated, and then pixel circuit's scanning speed has been promoted, be favorable to solving the problem that scanning time is not enough appears in the pixel circuit. In view of this, the embodiments of the present invention can meet the requirements of the display panel with high refresh rate, high gray scale number and high PPI, and is favorable for improving the display quality of the display panel.
Further, the at least two first transistors are both P-type transistors, or the at least two first transistors are both N-type transistors. Preferably, the at least two first transistors are all P-type transistors, and the first power signal inputted from the first power terminal is at a high potential. The substrate of first transistor is P type semiconductor, and minority carrier in the P type semiconductor is electron, the embodiment of the utility model provides a with the substrate access high potential of first transistor, be favorable to strengthening the ability that the substrate adsorbs the electron for the moving speed of electron to be favorable to forming the conducting channel fast, promoted the turn-on speed of first transistor. In addition, the manufacturing process of the P-type transistor is simple, and the embodiment of the utility model provides a set up first transistor and be favorable to reducing the cost of manufacture of pixel circuit for the P-type transistor.
Further, the memory module comprises a memory input terminal and a memory output terminal, wherein the memory input terminal is electrically connected with the second pole of the first transistor; the drive control end is electrically connected with the storage input end, or the drive control end is electrically connected with the storage output end. The electric potentials of the storage input end and the storage output end of the storage module are stored and changed correspondingly at the same time, namely when the electric potential of the storage input end is kept unchanged, the electric potential of the storage output end is also kept unchanged, and when the electric potential of the storage input end is changed, the electric potential of the storage output end is changed correspondingly, so that the driving control end is electrically connected with the storage input end or the driving control end is electrically connected with the storage output end, and the data signals received by the driving control end of the driving module are stored data signals.
Further, the memory module includes a first inverter and a second inverter; and the inverted input end of the first phase inverter and the inverted output end of the second phase inverter are short-circuited and then serve as the storage input end of the storage module, and the inverted output end of the first phase inverter and the inverted input end of the second phase inverter are short-circuited and then serve as the storage output end of the storage module. The first inverter and the second inverter are connected in anti-parallel to form a storage module which is a latch. The electric potential input by the storage input end passes through the first inverter to obtain the opposite electric potential of the electric potential, the opposite electric potential is output by the storage output end, and the opposite electric potential is changed into the original electric potential through the second inverter and is connected back to the storage input end. Therefore, the electric potential of the storage input end is kept unchanged after passing through the first inverter and the second inverter, the original electric potential and the opposite electric potential of the original electric potential are circularly latched in the first inverter and the second inverter before the electric potential input by the storage input end is changed, and the storage module plays a role in storing signals.
Further, a second power supply terminal and a third power supply terminal are included; the first inverter includes: a second transistor and at least two third transistors; the grid electrode of the second transistor is used as the inverting input end of the first inverter, and the first electrode of the second transistor is electrically connected with the second power supply end; a gate of the third transistor is electrically connected to a second end thereof; and the at least two third transistors are connected in series, the first pole of the third transistor of the first stage is short-circuited with the second pole of the second transistor and then used as the inverted output end of the first inverter, and the second pole of the third transistor of the last stage is electrically connected with the third power supply end. Wherein, when the second transistor switches on, can produce the pressure drop on at least two third transistors, the embodiment of the utility model provides a quantity that sets up the third transistor is at least two, can play partial pressure and current-limiting's effect, reduces consumption on second transistor and the third transistor.
Further, the width-to-length ratio of the third transistor is smaller than that of the second transistor, that is, the equivalent resistance of the third transistor is larger than that of the second transistor. When the second transistor is turned on, the Equivalent Series Resistances (ESR) of the at least two third transistors are relatively large, and the voltage drop is mainly on the ESR, so that the voltage division of the second transistor is relatively small, and the potential of the inverting output end of the first inverter is kept at the potential of the second power supply signal. In addition, the ESR of at least two third transistors is larger, which is beneficial to further reducing the power consumption of the third transistors.
Further, the second inverter includes: a fourth transistor and at least two fifth transistors; a gate of the fourth transistor is used as an inverting input end of the second inverter, and a first electrode of the fourth transistor is electrically connected with the second power supply end; the grid electrode of the fifth transistor is electrically connected with the second end of the fifth transistor; and the at least two fifth transistors are connected in series, the first pole of the fifth transistor of the first stage is short-circuited with the second pole of the fourth transistor and then used as the inverted output end of the second inverter, and the second pole of the fifth transistor of the last stage is electrically connected with the third power supply end. The embodiment of the utility model provides a set up the structure of second phase inverter and the structure of first phase inverter is the same, can ensure the structural symmetry of storage module on the one hand, be favorable to the stability of the signal of storage input end and storage output end; on the other hand, the first inverter and the second inverter can be manufactured in the same process, so that the process steps are reduced, and the manufacturing cost of the pixel circuit is reduced.
Correspondingly, the utility model also provides a display panel, which comprises the pixel circuit according to any embodiment of the utility model; the display panel further includes a plurality of scan lines, a plurality of data lines, and a first power signal line, the scan lines and the data lines crossing to define the pixel circuits, the scan signal input terminals being electrically connected to the corresponding scan lines, the data signal input terminals being electrically connected to the corresponding data lines, and the first power terminal being electrically connected to the first power signal line.
Further, the display panel further includes a second power supply signal line and a third power supply signal line; the driving module further comprises a driving input end and a driving output end, and the driving input end is electrically connected with the second power signal line; a first pole of the light emitting device is electrically connected with the driving output end, and a second pole of the light emitting device is electrically connected with the third power signal line; the second power supply signal line is multiplexed as the first power supply signal line, or the third power supply signal line is multiplexed as the first power supply signal line.
The driving module and the light emitting device are connected in series between the second power signal line and the third power signal line, and the second power signal line, the driving module, the light emitting device and the third power signal line provide a conduction path of a driving current. The second power supply signal line may be multiplexed as the first power supply signal line if the second power supply signal line has the same potential as the first power supply signal line; similarly, if the third power supply signal on the third power supply signal line has the same potential as the first power supply signal on the first power supply signal line, the third power supply signal line may be multiplexed with the first power supply signal line. The embodiment of the utility model provides a be provided with the quantity that does benefit to and reduce power signal line like this to be favorable to display panel's wiring.
Correspondingly, the utility model also provides a display device, which comprises the display panel as any embodiment of the utility model; the display device further includes: the device comprises a row scanning module, a column scanning module and a driving control module; the line scanning module comprises a time sequence input end and a plurality of scanning output ends, the time sequence input end is electrically connected with the driving control module, and the plurality of scanning output ends are electrically connected with the corresponding scanning lines; the column scanning module comprises a data input end and a plurality of data output ends, the data input end is electrically connected with the driving control module, and the data output ends are electrically connected with the corresponding data lines.
The embodiment of the utility model provides a through setting up two at least first transistor parallel connection, two at least first transistors are opened simultaneously and are turn-offed promptly, have increased data signal transmission channel's width length ratio to transmission channel's on-resistance has been reduced. And, the substrate of first transistor is connected with first power end electricity, has increased the potential difference of substrate in other words, has strengthened the substrate and has adsorbed the minority carrier's ability, has accelerated the rate of motion of minority carrier, helps shortening the formation time of conducting channel, consequently, the embodiment of the utility model provides a speed of switching on of first transistor has been accelerated to the response speed of transmission gate has been accelerated, data signal's transmission rate has been accelerated, the speed that data signal transmitted drive module's drive control end has been accelerated, and then pixel circuit's scanning speed has been promoted, be favorable to solving the problem that scanning time is not enough appears in the pixel circuit. In view of this, the embodiments of the present invention can meet the requirements of the display panel with high refresh rate, high gray scale number and high PPI, and is favorable for improving the display quality of the display panel.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
An embodiment of the present invention provides a pixel circuit, which is applicable to an analog driving method or a digital driving method. Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention. Referring to fig. 1, the pixel circuit includes: a scan signal input terminal 101, a data signal input terminal 102, a first power supply terminal 201, at least two first transistors (the number of the first transistors is exemplarily shown as two in fig. 1, respectively, a first transistor T1-1 and a second first transistor T1-2), a memory module 400, and a driving module 500. The gates of the first and second first transistors T1-1 and T1-2 are electrically connected to the scan signal input terminal 101, the first electrodes of the first and second first transistors T1-1 and T1-2 are electrically connected to the data signal input terminal 102, and the substrates of the first and second first transistors T1-1 and T1-2 are electrically connected to the first power supply terminal 201. The memory module 400 is electrically connected to the second poles of the first and second first transistors T1-1 and T1-2, and the memory module 400 is used to store data signals written into the memory module 400 through the turned-on first and second first transistors T1-1 and T1-2. The driving module 500 includes a driving control terminal 501, the driving control terminal 501 is electrically connected to the memory module 400, and the driving module 500 is configured to drive the light emitting device LD to emit light in response to a data signal.
Wherein, the scan signal input terminal 101 is used for inputting a scan signal, the data signal input terminal 102 is used for inputting a data signal, and the first power terminal 201 is used for inputting a first power signal. At least two first transistors are connected in parallel to form a transmission gate 300, and the transmission gate 300 transmits the data signal input from the data signal input terminal 102 to the memory module 400 in response to the scan signal input from the scan signal input terminal 101. The memory module 400 stores the data signal means that the memory module 400 can keep the potential of the data signal unchanged. The data signal to which the driving module 500 responds refers to the signal input from the data signal input terminal 102, transmitted through the transmission gate 300, and held by the memory module 400, and therefore, the signal input from the data signal input terminal 102, the signal output from the transmission gate 300, the signal stored in the memory module 400, and the signal input from the driving control terminal 501 are collectively referred to as a data signal. The driving module 500 generates a driving signal in response to the data signal, and the driving signal drives the light emitting device LD to emit light.
The embodiment of the utility model provides a through setting up two at least first transistor parallel connection, two at least first transistors are opened simultaneously and are turn-offed promptly, have increased data signal transmission channel's width length ratio to transmission channel's on-resistance has been reduced. And, the substrate of first transistor is connected with first power end 201 electricity, has increased the potential difference of substrate in other words, has strengthened the ability that the substrate adsorbs the minority carrier, has accelerated the rate of motion of minority carrier, helps shortening the formation time of conducting channel, consequently, the embodiment of the utility model provides a speed of switching on of first transistor has been accelerated to the response speed of transmission gate 300 has been accelerated, data signal's transmission rate has been accelerated, data signal has been accelerated to the speed of drive control end 501 of drive module 500, and then has promoted pixel circuit's scanning speed, is favorable to solving the problem that scanning time is not enough appears in the pixel circuit. In view of this, the embodiments of the present invention can meet the requirements of the display panel with high refresh rate, high gray scale number and high PPI, and is favorable for improving the display quality of the display panel.
With continued reference to fig. 1, on the basis of the above embodiment, optionally, the first transistors are all P-type transistors, and the first power signal inputted from the first power terminal 201 is at a high potential. The substrate of first transistor is P type semiconductor, and minority carrier in the P type semiconductor is electron, the embodiment of the utility model provides a with the substrate access high potential of first transistor, be favorable to strengthening the ability that the substrate adsorbs the electron for the moving speed of electron to be favorable to forming the conducting channel fast, promoted the turn-on speed of first transistor. In addition, the manufacturing process of the P-type transistor is simple, and the embodiment of the utility model provides a set up first transistor and be favorable to reducing the cost of manufacture of pixel circuit for the P-type transistor.
It should be noted that fig. 1 exemplarily shows that the first transistors are all P-type transistors, which is not a limitation of the present invention, and in other embodiments, the first transistors may be all N-type transistors, and may be set as needed in practical applications.
On the basis of the above embodiments, the storage module 400 may optionally include a storage capacitor, for example. Storage capacitor can save the data signal of different electric potentials, consequently, adopts storage capacitor's pixel drive circuit can be suitable for analog drive method and digital drive method, the embodiment of the utility model provides a scan time through reducing pixel circuit is favorable to improving the ratio of taking up of luminescent device luminous time in the frame to be favorable to improving display panel's display brightness.
With reference to fig. 1, based on the foregoing embodiments, optionally, the memory module 400 includes a memory input terminal 401 and a memory output terminal 402, the memory input terminal 401 is electrically connected to the second pole of the first transistor, and the driving control terminal 501 is electrically connected to the memory output terminal 402, that is, the data signal received by the driving control terminal 501 is the data signal processed by the memory module 400, so in practical applications, the potential of the data signal output by the memory output terminal 402 may be set to be the same as or different from the potential of the data signal input to the memory input terminal 401 as needed.
It should be noted that fig. 1 exemplarily shows that the driving control terminal 501 is electrically connected to the storage output terminal 402, and is not a limitation of the present invention. In other embodiments, referring to fig. 2, the driving control terminal 501 may be further configured to be electrically connected to the storage input terminal 401. The potentials of the storage input terminal 401 and the storage output terminal 402 of the storage module 400 are stored and changed correspondingly, that is, when the potential of the storage input terminal 401 is kept unchanged, the potential of the storage output terminal 402 is also kept unchanged, and when the potential of the storage input terminal 401 is changed, the potential of the storage output terminal 402 is also changed correspondingly, so that the driving control terminal 501 is electrically connected with the storage input terminal 401, and the data signal received by the driving control terminal 501 of the driving module 500 is also the stored data signal.
Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 3, on the basis of the foregoing embodiments, optionally, the memory module 400 includes a first inverter 410 and a second inverter 420, an inverting input terminal of the first inverter 410 and an inverting output terminal of the second inverter 420 are shorted to serve as the memory input terminal 401 of the memory module 400, and an inverting output terminal of the first inverter 410 and an inverting input terminal of the second inverter 420 are shorted to serve as the memory output terminal 402 of the memory module 400.
The first inverter 410 and the second inverter 420 are connected in anti-parallel to form the memory module 400, and the memory module 400 is a latch. The potential inputted from the storage input terminal 401 gets the reverse potential of the potential through the first inverter 410, and is outputted from the storage output terminal 402, and the reverse potential becomes the original potential through the second inverter 420 and is connected back to the storage input terminal 401. It can be seen that the potential of the storage input terminal 401 remains unchanged after passing through the first inverter 410 and the second inverter 420, and the original potential and the opposite potential are cyclically latched in the first inverter 410 and the second inverter 420 before the potential input by the storage input terminal 401 changes, so that the storage module 400 plays a role of storing signals.
Since the potentials stored in the first inverter 410 and the second inverter 420 can only change between a high potential and a low potential, the pixel circuit provided by the embodiment of the invention is suitable for the digital driving method. The digital driving method refers to adjusting the light emitting brightness of the display panel by controlling the light emitting area or the light emitting time of the light emitting device. Compared with an analog driving method, the digital driving method has the advantages of low image noise and high switching speed, and reduces the requirements of high-precision gray scale on digital-to-analog conversion, process and materials.
The embodiment of the utility model provides a storage module 400 adopts the structure of first phase inverter 410 and second phase inverter 420 for storage module 400's simple structure, control method is simple, is favorable to simplifying pixel circuit's structure. And, compare with storage capacitor, the embodiment of the utility model provides a save storage capacitor's charge-discharge time, shortened storage time, be favorable to pixel circuit's quick scanning.
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Referring to fig. 4, on the basis of the above embodiments, optionally, the pixel circuit further includes a second power source terminal 202 and a third power source terminal 203. The first inverter 410 includes: a second transistor T2 and at least two third transistors (the number of the third transistors is exemplarily shown as two in fig. 4, a first-stage third transistor T3-1 and a second-stage third transistor T3-2, respectively), the gate of the second transistor T2 serving as the inverting input terminal 411 of the first inverter 410, and the first electrode of the second transistor T2 electrically connected to the second power supply terminal 202. The gates of the first stage third transistor and the second stage third transistor T3-2 are electrically connected to the second terminal thereof, the first stage third transistor and the second stage third transistor T3-2 are connected in series, the first terminal of the first stage third transistor T3-1 is shorted to the second terminal of the second transistor T2 to be the inverting output terminal 412 of the first inverter 410, and the second terminal of the last stage third transistor T3-2 is electrically connected to the third power terminal 203.
Illustratively, the second transistor T2 and the at least two third transistors are P-type transistors, the second power signal inputted from the second power source terminal 202 is at a high potential, and the third power signal inputted from the third power source terminal 203 is at a low potential. When the inverting input terminal 411 of the first inverter 410 inputs a low potential, the second transistor T2 is turned on; since the connection manner of the at least two third transistors can be equivalent to two diodes connected in series, at this time, the high potential generates a voltage drop on the at least two third transistors, and the inverted output terminal 412 of the first inverter 410 outputs the high potential. When the inverting input terminal 412 of the first inverter 410 inputs a high potential, the second transistor T2 is turned off, the at least two third transistors are turned on, and the inverting output terminal 412 of the first inverter 410 outputs a low potential. Illustratively, the voltage of the third power signal is VGL, the threshold voltage of the third transistor is Vth, and the voltage of the inverting output terminal of the first inverter 410 is VGL-2 Vth.
When the second transistor T2 is turned on, a voltage drop is generated between the first-stage third transistor T3-1 and the second-stage third transistor T3-2, which are connected in series, and the embodiment of the present invention sets the number of the third transistors to be at least two, which can play a role of voltage division and current limitation, thereby reducing the power consumption of the second transistor T2 and the third transistor.
On the basis of the above embodiments, optionally, the width-to-length ratio of the third transistor is smaller than that of the second transistor T2, that is, the equivalent resistance of the third transistor is larger than that of the second transistor T2. When the second transistor T2 is turned on, the Equivalent Series Resistances (ESR) of the at least two third transistors are relatively large, and the voltage drop is mainly over the ESR, so that the voltage division of the second transistor T2 is relatively small, and the potential of the inverting output terminal 412 of the first inverter 410 is kept at the potential of the second power supply signal. In addition, the ESR of at least two third transistors is larger, which is beneficial to further reducing the power consumption of the third transistors.
With continuing reference to fig. 4, based on the above embodiments, optionally, the second inverter 420 includes: a fourth transistor T4 and at least two fifth transistors (the number of the fifth transistors is exemplarily shown in fig. 4 to be two, namely, a first-stage fifth transistor T5-1 and a second-stage fifth transistor T5-2), a gate of the fourth transistor T4 is used as the inverting input 421 of the second inverter 420, a first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal 202, and gates of the first-stage fifth transistor T5-1 and the second-stage fifth transistor T5-2 are electrically connected to the second terminals thereof. And the first stage fifth transistor T5-1 and the second stage fifth transistor T5-2 are connected in series, the first pole of the first stage fifth transistor T5-1 is shorted with the second pole of the fourth transistor T4 to serve as the inverting output terminal 422 of the second inverter 420, and the second pole of the last stage fifth transistor T5-2 is electrically connected to the third power source terminal 203. The embodiment of the present invention sets the structure of the second phase inverter 420 to be the same as the structure of the first phase inverter 410, which can ensure the structural symmetry of the storage module 400, and is beneficial to the stability of the signals of the storage input end 401 and the storage output end 402; on the other hand, the first inverter 410 and the second inverter 420 can be manufactured in the same process, which is beneficial to reducing the process steps and the manufacturing cost of the pixel circuit.
It should be noted that, in fig. 4, the second transistor T2, the third transistor T4, and the fifth transistor are exemplarily shown to be P-type transistors, which is not a limitation of the present invention, and in other embodiments, the second transistor T2, the third transistor T4, and the fifth transistor may also be N-type transistors, and in practical applications, may be set as needed.
On the basis of the foregoing embodiments, optionally, the pixel circuit further includes a fourth power supply terminal, and the substrates of the second transistor T2, the third transistor T4, and the fifth transistor may be electrically connected to the fourth power supply terminal, so as to enhance the ability of the substrate to absorb minority carriers, accelerate the moving speed of the minority carriers, facilitate the transistors to form a conductive channel quickly, accelerate the conducting speed of each transistor, accelerate the response speed of the memory module 400, and accelerate the transmission speed of the data signal.
Referring to fig. 1 to 4, on the basis of the above embodiments, optionally, the pixel circuit further includes a fifth power supply terminal 205 and a sixth power supply terminal 206, the driving module 500 includes a sixth transistor T6, a gate of the sixth transistor T6 serves as the driving control terminal 501 of the driving module 500, a first pole of the sixth transistor T6 is electrically connected to the fifth power supply terminal 205, a second pole of the sixth transistor T6 is electrically connected to the first pole of the light emitting device LD, and the second pole of the light emitting device LD is electrically connected to the sixth power supply terminal 206. The sixth transistor T6 is turned on in response to the data signal inputted from the control terminal, thereby driving the light emitting device LD to emit light.
On the basis of the foregoing embodiments, optionally, the pixel circuit further includes a seventh power supply terminal, and the substrate of the sixth transistor T6 may be electrically connected to the seventh power supply terminal, so as to enhance the ability of the substrate to absorb minority carriers, accelerate the moving speed of the minority carriers, facilitate the sixth transistor T6 to quickly form a conducting channel, and accelerate the conducting speed of the sixth transistor T6, thereby accelerating the response speed of the driving current and facilitating the reduction of the scanning time.
On the basis of the above embodiments, optionally, the types of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all P-type transistors or all N-type transistors, and the substrate of each transistor is connected to the first power supply terminal. The embodiment of the utility model provides a set up like this, on one hand, set up each transistor as the transistor of same substrate type, can make in same technology and accomplish, be favorable to reducing the cost of manufacture of pixel circuit; on the other hand, by connecting the substrates of the transistors to the same signal line, the number of power source terminals can be reduced, thereby reducing the number of power source signal lines connected to the power source terminals, which is advantageous for wiring of the display panel.
In the above embodiments, the first electrode of each transistor is a source or a drain, and the second electrode of each transistor is a drain or a source, and in the pixel circuit, the transistors have symmetrical structures, and the sources and the drains are not distinguished.
The embodiment of the utility model provides a display panel is still provided. Fig. 5 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Referring to fig. 5, the display panel includes a pixel circuit 10 as provided by any of the embodiments of the present invention. Therefore, the embodiment of the present invention provides a display panel that also has the beneficial effects described in the above embodiments, which is not repeated herein.
With continued reference to fig. 5, the display panel further includes a plurality of scan lines 20, a plurality of data lines 30, and a first power signal line 40, the scan lines 20 and the data lines 30 crossing to define the pixel circuits 10, the scan signal input terminals being electrically connected to the corresponding scan lines 20, the data signal input terminals being electrically connected to the corresponding data lines 30, and the first power supply terminal being electrically connected to the first power signal line 40. Wherein a scanning signal is transmitted to the scanning signal input terminal of the pixel circuit 10 through the scanning line 20, a data signal is transmitted to the data signal input terminal of the pixel circuit 10 through the data line 30, and a first power supply signal is transmitted to the first power supply terminal through the first power supply signal line 40.
Illustratively, the driving method of the display panel is that scanning signals are sequentially transmitted on a plurality of scanning lines 20, the scanning signals sequentially turn on pixel circuits 10 electrically connected with one scanning line 20, and at the same time, each data line 30 transmits a data signal to the turned-on pixel circuit 10, thereby realizing the driving of the light emitting device to emit light. The embodiment of the utility model provides a response speed of pixel circuit 10's transmission gate is very fast, can begin to scan the next line (scanning line 20 is invalid promptly) at scanning line 20, and the pixel circuit 10 of being connected with this scanning line 20 electricity is turn-offs fast, avoids two adjacent pixel circuit 10 of same data line 30 simultaneous drive to be favorable to avoiding adjacent pixel circuit 10's crosstalk.
On the basis of the foregoing embodiments, optionally, the display panel further includes a second power signal line and a third power signal line, the driving module further includes a driving input terminal and a driving output terminal, the driving input terminal is electrically connected to the second power signal line, the first pole of the light emitting device is electrically connected to the driving output terminal, and the second pole of the light emitting device is electrically connected to the third power signal line. The second power supply signal line is multiplexed as the first power supply signal line, or the third power supply signal line is multiplexed as the first power supply signal line.
The driving module and the light emitting device are connected in series between the second power signal line and the third power signal line, and the second power signal line, the driving module, the light emitting device and the third power signal line provide a conduction path of a driving current. The second power supply signal line may be multiplexed as the first power supply signal line if the second power supply signal line has the same potential as the first power supply signal line; similarly, if the third power supply signal on the third power supply signal line has the same potential as the first power supply signal on the first power supply signal line, the third power supply signal line may be multiplexed with the first power supply signal line. The embodiment of the utility model provides a be provided with the quantity that does benefit to and reduce power signal line like this to be favorable to display panel's wiring.
The embodiment of the utility model provides a display device is still provided. Fig. 6 is a schematic structural diagram of a display device according to an embodiment of the present invention. Referring to fig. 6, the display device comprises a display panel 1 as provided by any of the embodiments of the present invention. Therefore, the display device provided by the embodiment of the present invention also has the beneficial effects described in the above embodiments, which are not repeated herein.
With continued reference to fig. 6, the display device further includes: the scanning device comprises a row scanning module 2, a column scanning module 3 and a driving control module 4, wherein the row scanning module 2 comprises a time sequence input end 2-1 and a plurality of scanning output ends 2-2, the time sequence input end 2-1 is electrically connected with the driving control module 4, and the plurality of scanning output ends 2-2 are electrically connected with corresponding scanning lines 20; the column scanning module 3 comprises a data input end 3-1 and a plurality of data output ends 3-2, the data input end 3-1 is electrically connected with the driving control module 4, and the plurality of data output ends 3-2 are electrically connected with the corresponding data lines 30.
The driving control module 4 is configured to send driving control signals to the row scanning module 2 and the column scanning module 3, and the driving control module 4 may include, for example, a data processor 41 and a timing controller 42. Illustratively, the driving method of the display device is that image data is input to the data processor 41, the data processor 41 reconstructs the image data according to a scanning algorithm of the timing controller 42 to obtain data driving signals, and the timing controller 42 generates scanning driving signals; scanning driving signals pass through the line scanning module 2 to generate scanning signals for line gating, and the pixel circuits receive the scanning signals sent by the line scanning module 2 through corresponding scanning lines 20; the data driving signal passes through the column scanning module 3 to generate a data signal, the pixel circuit receives the data signal sent by the column scanning module 3 through the corresponding data line 30, and the display device accordingly achieves a display function. Exemplarily, the display device can be a micro-light emitting diode display device or an organic light emitting diode display device, and the display device can be an electronic device such as a mobile phone, a computer or wearable equipment.
It should be noted that the foregoing is only a preferred embodiment of the present invention and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail with reference to the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the scope of the present invention.
Claims (10)
1. A pixel circuit, comprising: the circuit comprises a scanning signal input end, a data signal input end, a first power supply end, at least two first transistors, a storage module and a driving module;
a gate of the first transistor is electrically connected to the scan signal input terminal, a first electrode of the first transistor is electrically connected to the data signal input terminal, and a substrate of the first transistor is electrically connected to the first power terminal;
the storage module is electrically connected with a second pole of the first transistor and is used for storing a data signal written into the storage module through the conducted first transistor;
the driving module comprises a driving control end, the driving control end is electrically connected with the storage module, and the driving module is used for responding to the data signal to drive the light-emitting device to emit light.
2. The pixel circuit according to claim 1, wherein the at least two first transistors are both P-type transistors or the at least two first transistors are both N-type transistors.
3. The pixel circuit according to claim 1, wherein the storage block comprises a storage input terminal and a storage output terminal, the storage input terminal being electrically connected to the second pole of the first transistor;
the drive control end is electrically connected with the storage input end, or the drive control end is electrically connected with the storage output end.
4. The pixel circuit according to claim 3, wherein the storage module comprises a first inverter and a second inverter;
and the inverted input end of the first phase inverter and the inverted output end of the second phase inverter are short-circuited and then serve as the storage input end of the storage module, and the inverted output end of the first phase inverter and the inverted input end of the second phase inverter are short-circuited and then serve as the storage output end of the storage module.
5. The pixel circuit according to claim 4, further comprising a second power supply terminal and a third power supply terminal;
the first inverter includes: a second transistor and at least two third transistors;
the grid electrode of the second transistor is used as the inverting input end of the first inverter, and the first electrode of the second transistor is electrically connected with the second power supply end;
a gate of the third transistor is electrically connected to a second end thereof; and the at least two third transistors are connected in series, the first pole of the third transistor of the first stage is short-circuited with the second pole of the second transistor and then used as the inverted output end of the first inverter, and the second pole of the third transistor of the last stage is electrically connected with the third power supply end.
6. The pixel circuit according to claim 5, wherein a width-to-length ratio of the third transistor is smaller than a width-to-length ratio of the second transistor.
7. The pixel circuit according to claim 5, wherein the second inverter comprises: a fourth transistor and at least two fifth transistors;
a gate of the fourth transistor is used as an inverting input end of the second inverter, and a first electrode of the fourth transistor is electrically connected with the second power supply end;
the grid electrode of the fifth transistor is electrically connected with the second end of the fifth transistor; and the at least two fifth transistors are connected in series, the first pole of the fifth transistor of the first stage is short-circuited with the second pole of the fourth transistor and then used as the inverted output end of the second inverter, and the second pole of the fifth transistor of the last stage is electrically connected with the third power supply end.
8. A display panel comprising the pixel circuit according to any one of claims 1 to 7;
the display panel further includes a plurality of scan lines, a plurality of data lines, and a first power signal line, the scan lines and the data lines crossing to define the pixel circuits, the scan signal input terminals being electrically connected to the corresponding scan lines, the data signal input terminals being electrically connected to the corresponding data lines, and the first power terminal being electrically connected to the first power signal line.
9. The display panel according to claim 8, further comprising a second power supply signal line and a third power supply signal line;
the driving module further comprises a driving input end and a driving output end, and the driving input end is electrically connected with the second power signal line;
a first pole of the light emitting device is electrically connected with the driving output end, and a second pole of the light emitting device is electrically connected with the third power signal line;
the second power supply signal line is multiplexed as the first power supply signal line, or the third power supply signal line is multiplexed as the first power supply signal line.
10. A display device characterized by comprising the display panel according to claim 8 or 9;
the display device further includes: the device comprises a row scanning module, a column scanning module and a driving control module;
the line scanning module comprises a time sequence input end and a plurality of scanning output ends, the time sequence input end is electrically connected with the driving control module, and the plurality of scanning output ends are electrically connected with the corresponding scanning lines;
the column scanning module comprises a data input end and a plurality of data output ends, the data input end is electrically connected with the driving control module, and the data output ends are electrically connected with the corresponding data lines.
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| CN201921405751.6U CN210142495U (en) | 2019-08-27 | 2019-08-27 | Pixel circuit, display panel and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870764A (en) * | 2020-06-11 | 2021-12-31 | 成都辰显光电有限公司 | Pixel circuit and display panel |
| CN114203103A (en) * | 2021-12-20 | 2022-03-18 | 深圳市华星光电半导体显示技术有限公司 | Light-emitting circuit, backlight module and display panel |
| CN114255689A (en) * | 2020-09-11 | 2022-03-29 | 成都辰显光电有限公司 | Pixel driving circuit, driving method thereof and display panel |
| CN114446225A (en) * | 2022-02-15 | 2022-05-06 | 上海天马微电子有限公司 | Pixel circuit, display panel and display device |
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2019
- 2019-08-27 CN CN201921405751.6U patent/CN210142495U/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113870764A (en) * | 2020-06-11 | 2021-12-31 | 成都辰显光电有限公司 | Pixel circuit and display panel |
| CN114255689A (en) * | 2020-09-11 | 2022-03-29 | 成都辰显光电有限公司 | Pixel driving circuit, driving method thereof and display panel |
| CN114203103A (en) * | 2021-12-20 | 2022-03-18 | 深圳市华星光电半导体显示技术有限公司 | Light-emitting circuit, backlight module and display panel |
| US12087241B2 (en) | 2021-12-20 | 2024-09-10 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Light emitting circuit having bistable circuit module for changing potential of gate of driving transistor, backlight module and display panel |
| CN114446225A (en) * | 2022-02-15 | 2022-05-06 | 上海天马微电子有限公司 | Pixel circuit, display panel and display device |
| CN114446225B (en) * | 2022-02-15 | 2023-09-01 | 上海天马微电子有限公司 | Pixel circuit, display panel and display device |
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