CN114446225A

CN114446225A - Pixel circuit, display panel and display device

Info

Publication number: CN114446225A
Application number: CN202210139252.7A
Authority: CN
Inventors: 东强; 孙晓平; 姬生超
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2022-02-15
Filing date: 2022-02-15
Publication date: 2022-05-06
Anticipated expiration: 2042-02-15
Also published as: CN114446225B

Abstract

The application discloses a pixel circuit, a display panel and a display device. The pixel circuit includes: the device comprises a signal processing module and at least one light emitting module; the signal processing module comprises a parallel network unit and a voltage division unit; the parallel network unit comprises n parallel voltage division elements, the input end of each voltage division element is respectively connected with the gray scale digital signal corresponding to the data signal, and the output end of each voltage division element is connected with the first node; n is an integer greater than 1; the first end of the voltage division unit is connected with the first node, and the second end of the voltage division unit is connected with the reference point; the first end of the light emitting module is connected with the first node, and the second end of the light emitting module is connected with the reference point. Therefore, the gray scale digital signals corresponding to the display signals are converted into gray scale voltages through the parallel network unit and the voltage division unit, so that the gray scale current input to the light emitting module is controlled through the gray scale voltages, and the pixel circuit displays gray scale brightness corresponding to the gray scale voltages.

Description

Pixel circuit, display panel and display device

Technical Field

The present application relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and a display device.

Background

Currently, a mini-led (mini-light emitting diode) or micro-led (micro-light emitting diode) display screen is mostly a direct type sectional backlight, taking the mini-led as an example, which includes a large number of mini-led pixel circuits. The miniLED pixel circuits form a plurality of independent light control subareas, so that accurate light control of a plurality of subareas is realized. The prior passive driving pixel circuit utilizes a driving chip to control each subarea to emit light. However, the control of the partitions by the driving chip cannot accurately display the gray scales of the image. Moreover, the partition driven by one driving chip is limited, thereby causing high manufacturing cost of the display screen.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a pixel circuit, a display panel and a display device, which are capable of accurately displaying gray-scale luminance corresponding to a gray-scale digital signal.

In a first aspect, an embodiment of the present application provides a pixel circuit, including: the device comprises a signal processing module and at least one light emitting module;

the signal processing module comprises a parallel network unit and a voltage division unit; the parallel network unit comprises n parallel voltage division elements, the input end of each voltage division element is respectively connected with the gray scale digital signal corresponding to the data signal, and the output end of each voltage division element is connected with the first node; n is an integer greater than 1;

the first end of the voltage division unit is connected with the first node, and the second end of the voltage division unit is connected with a reference point;

the first end of the light emitting module is connected with the first node, and the second end of the light emitting module is connected with a reference point.

In a second aspect, based on the same inventive concept, embodiments of the present application provide a display panel including the pixel circuit provided in any of the embodiments of the present application.

In a third aspect, based on the same inventive concept, embodiments of the present application provide a display device including the display panel provided in any of the embodiments of the present application.

The pixel circuit, the display panel and the display device provided by the embodiment of the application comprise a signal processing module and a light emitting module. The signal processing module comprises a parallel network unit and a voltage division unit. The parallel network unit comprises n parallel voltage division elements, the input end of each voltage division element is respectively connected with the gray scale digital signal corresponding to the data signal, and the output end of each voltage division element is connected with the first node. And the first end of the voltage division unit is connected with the first node. Therefore, the gray scale digital signals corresponding to the display signals are converted into gray scale voltages through the parallel network unit and the voltage division unit, so that the gray scale current input to the light emitting module is controlled through the gray scale voltages, and the pixel circuit displays gray scale brightness corresponding to the gray scale voltages. Therefore, the current in the pixel circuit can be accurately controlled without an additional compensation circuit or changing the voltage of the input pixel circuit, so as to achieve the accurate control of the gray scale of the display picture. Meanwhile, the driving chip is prevented from being adopted to drive and control each pixel circuit to emit light, so that the cost for manufacturing the display panel is reduced.

Drawings

In order to more clearly refer to the voltage or describe the technical scheme of the embodiment of the present application, the drawings needed to be used in the embodiment of the present application will be briefly described below, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 shows a schematic structural diagram of a row scanning circuit provided in the prior art.

Fig. 2 shows a schematic structural diagram of a pixel circuit according to an embodiment of the present application.

Fig. 3 shows a schematic structural diagram of another pixel circuit provided in an embodiment of the present application.

Fig. 4 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.

Fig. 5 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.

Fig. 6 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.

Fig. 7 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.

Fig. 8 shows a schematic structural diagram of an adjustment subunit provided in an embodiment of the present application.

Fig. 9 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.

Fig. 10 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application.

Fig. 11 shows a schematic structural diagram of a display panel provided in an embodiment of the present application.

Fig. 12 shows a schematic structural diagram of a direct-drive display panel provided in an embodiment of the present application.

Fig. 13 shows a schematic structural diagram of another direct-drive display panel provided in an embodiment of the present application.

Fig. 14 shows a schematic structural diagram of a row-driving display panel according to an embodiment of the present application.

Fig. 15 shows a schematic structural diagram of a column driving display panel according to an embodiment of the present application.

Fig. 16 shows a schematic structural diagram of another row-driving display panel provided in an embodiment of the present application.

Fig. 17 is a schematic structural diagram of a column scanning display panel according to an embodiment of the present application.

Fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

At present, the direct type subarea backlight based on the MiniLED can achieve the technical effect of accurately regulating and controlling the current of each subarea, so that the brightness of a bright-state picture is higher, and the brightness of a dark-state picture can approach to 0. Therefore, the image display quality is improved.

The existing driving methods of the direct type partitioning backlight mainly include Passive Matrix (PM) and Active Matrix (AM).

However, in the PM mode, the LED driving chip is directly used for driving, which results in a limited number of partitions and high cost.

In the AM mode, the current is controlled using a voltage, and the gray scale control is difficult. In addition, in the driving circuit, a thin film transistor is generally used as a driving transistor. Since the thin film transistor has a complicated process and poor device uniformity, resulting in poor uniformity of the display panel, a complicated threshold compensation circuit or an external compensation method is required. In addition, the display panel adopting the AM mode consumes a large amount of power.

In addition, the compatibility of the existing liquid crystal manufacturing process to the MiniLED is insufficient. If a new process is added, poor product consistency may result.

Fig. 1 shows a schematic structural diagram of a row scanning circuit provided in the prior art. As shown in fig. 1, since the micro light emitting diode LED is a current-type driving device, display luminance is related to the magnitude of an electric signal flowing therethrough. Therefore, the current signal flowing through the micro LED LEDs needs to be much larger than the SCAN (SCAN) signal in order to maintain the MiniLED backlight/display panel with corresponding brightness. As such, more complex power supply designs need to be added to the pixel circuits, and heat dissipation needs to be addressed.

In view of this, the pixel circuit, the display panel and the display device provided in the embodiments of the present application can convert the gray-scale digital signal into the corresponding gray-scale voltage through the parallel voltage dividing element, so as to control the gray-scale current input to the light emitting module through the gray-scale voltage, and further achieve the purpose of accurately controlling the gray-scale brightness. Therefore, the purposes of accurately controlling the gray scale brightness and improving the uniformity can be achieved without a complex compensation circuit or changing the voltage of the input pixel circuit. In addition, the product can be manufactured by utilizing the original process, so that the consistency of the product is ensured.

Meanwhile, the pixel circuits are driven to emit light by adopting the digital signals, and the driving chip is prevented from being adopted to drive and control each pixel circuit to emit light, so that the cost for manufacturing the display panel is reduced.

Fig. 2 shows a schematic structural diagram of a pixel circuit according to an embodiment of the present application. As shown in fig. 2, the pixel circuit 10 may include a signal processing module 11 and at least one light emitting module 12.

When the pixel circuit 10 belongs to a row scanning circuit or a column scanning circuit, the pixel circuit 10 may include one signal processing module 11 and a plurality of light emitting modules 12.

When the pixel circuit 10 belongs to a direct drive circuit, the pixel circuit 10 may include a signal processing module 11 and a light emitting module 12.

It should be noted that the pixel circuit 10 belongs to a row scanning circuit or a column scanning circuit, which means that the pixel circuit 10 can drive the light emitting module 12 to emit light by a row scanning or a column scanning manner.

The pixel circuit 10 belongs to a direct drive circuit, which means that the signal processing module 12 in the pixel circuit 10 can directly drive the light emitting module 12 to emit light.

The input end of the signal module 11 is connected to the gray scale digital signal, and the output end of the signal module 11 is connected to the first end of the light emitting module.

The signal processing module 11 includes a parallel network unit 111 and a voltage dividing unit 112. The parallel network unit 111 includes n voltage dividing elements (i.e., a voltage dividing element 1111, a voltage dividing element 1112 to a voltage dividing element 111n) connected in parallel. n is an integer greater than 1.

Here, the parallel network unit 111 may be configured by n voltage dividing elements connected in parallel. The voltage of each voltage dividing element is equal.

The input end of each voltage division element is respectively connected with the gray scale digital signal corresponding to the data signal. The output end of each voltage division element is connected with the first node P.

Here, the first node P may be an output terminal of the signal processing module 11. The data signal may be an a-bit gray scale digital signal. The A digital signals are loaded in parallel to form gray-scale digital signals. Wherein each bit of the gray-scale digital signal is 0 (i.e. corresponding to a logic low level) or 1 (i.e. corresponding to a logic high level). The gray scale digital signal may be used to represent gray scale luminance. For example, when a is 8, the gray-scale digital signal may represent 256 gray-scales. The gray scale digital signal can be 10000000, 11000000, 11100000, etc. 2⁸Any combination thereof.

The input end of each voltage division element is connected with each bit digital signal in the gray scale digital signals. That is, the input terminals of the n voltage dividing elements input digital signals in parallel.

It should be noted that the high level in the grayscale digital signal can drive the light emitting module to emit light. In the embodiment of the present application, the analog high voltage corresponding to the high level may be non-zero volts, and the analog high voltage corresponding to the high level is greater than the threshold voltage of the light emitting module 12. The low level may correspond to an analog low voltage that is below the threshold voltage.

In the implementation of the present application, when the digital signal connected to one voltage dividing element is 1, the parallel branch where the voltage dividing element is located is turned on. When the digital signal connected with one voltage division element is 0, the parallel branch where the voltage division element is located is not conducted.

A first end of the voltage dividing unit 112 is connected to the first node P. A second end of the voltage dividing unit 112 is connected to a reference point.

In embodiments of the present application, the reference point may comprise a ground or reference voltage source. Wherein, the reference voltage of the reference voltage source is fixed. Optionally, the reference voltage is lower than the reverse breakdown voltage of the light emitting module 12.

Here, the voltage dividing unit 112 and each voltage dividing element in the parallel network unit 111 constitute a series voltage dividing circuit. In this way, when the second terminal of the voltage dividing unit 112 is connected to the ground, the sum of the voltage dividing unit 112 and the voltage of each voltage dividing element in the parallel network unit 111 is the logic level of the digital signal correspondingly connected to each voltage dividing element 111 x.

For example, when the high level corresponds to an analog high voltage of 5 volts, the second terminal of the voltage dividing unit 112 is connected to ground, and when the digital signal connected to one voltage dividing element is 1, the parallel branch where the voltage dividing element is located is turned on, and the sum of the voltage across the voltage dividing unit 112 and the voltage across each voltage dividing element 111x in the parallel network unit 111 is 5 volts.

When the second end of the voltage dividing unit 112 is connected to the reference voltage source, the sum of the voltage dividing unit 112 and the voltage of each voltage dividing element in the parallel network unit 111 is the difference between the analog high voltage corresponding to the high level in the digital signal correspondingly connected to each voltage dividing element and the reference voltage of the reference voltage source. Alternatively, the reference voltage of the reference voltage source may be a negative voltage.

For example, when the high level corresponds to an analog high voltage of 5 volts, the second terminal of the voltage dividing unit 112 is connected to a reference voltage source, and the reference voltage is-1 volt, when the digital signal connected to one voltage dividing element is 1, the parallel branch where the voltage dividing element is located is turned on, and the sum of the voltage dividing unit 112 and the voltage of each voltage dividing element in the parallel network unit 111 is 6 volts.

In the embodiment of the present application, the voltage dividing unit 112 and each voltage dividing element in the parallel network unit 111 form a serial voltage dividing circuit. Therefore, the voltage of the first node P can be changed by changing the parameter of the voltage dividing element in the parallel network unit 111 without changing the parameter of the voltage dividing unit.

A first end of the light emitting module 12 is connected to the first node P. The second end of the light module 12 is connected to a reference point.

In the present embodiment, the intensity of the brightness generated by the light emitting module 12 may be related to the current input to the light emitting module 12, and the current input to the light emitting module 12 is related to the voltage of the first node P. In this way, the light emitting module 12 can display corresponding gray-scale luminance according to the output voltage of the parallel network unit 111.

Note that the second terminal of the voltage dividing unit 112 and the second terminal of the light emitting module 12 have the same potential. When the second terminal of the voltage dividing unit 112 is connected to the ground, the second terminal of the light emitting module 12 is connected to the ground. When the second terminal of the voltage dividing unit 112 is connected to the reference voltage source, the second terminal of the light emitting module 12 is connected to the reference voltage source.

In the above embodiment, the parallel network unit and the voltage dividing unit convert the gray scale digital signal corresponding to the display signal into the gray scale voltage, so as to control the gray scale current input to the light emitting module through the gray scale voltage, so that the pixel circuit displays the gray scale brightness corresponding to the gray scale voltage. Therefore, the current in the pixel circuit can be accurately controlled without an additional compensation circuit or changing the voltage of the input pixel circuit, so as to achieve the accurate control of the gray scale of the display picture. Meanwhile, the driving chip is prevented from being adopted to drive and control each pixel circuit to emit light, so that the cost for manufacturing the display panel is reduced.

In some embodiments, as shown in FIG. 2, the voltage dividing element may include a resistor (i.e., resistor R)₁To the resistance R_n)。

In the embodiment of the present application, the parallel network unit 111 has an input resistor R_inComprises the following steps:

wherein D1 to Dn correspond to each bit of logic level 0 or 1 in the gray-scale digital signal. When D1 is 0, it represents the resistance R₁The branch is not conducted, and the resistance R can not be considered when calculating the input resistance of the parallel network unit 11₁. When D1 is 1, it represents the resistance R₁When the branch is conducted and the input resistance of the parallel network unit 11 is calculated, the resistance R is considered₁。

Alternatively, as shown in fig. 2, the voltage dividing unit 112 may include a resistor R_L. Since the parallel network unit is connected in series with the voltage dividing unit, the parallel network unit 111 outputs a voltage V_outComprises the following steps:

wherein, V_inThe analog high voltage corresponds to the high level in the gray scale digital signal.

The current flowing through the light emitting module is I_LEDComprises the following steps:

wherein R is_LEDIs the internal resistance of the light emitting module.

In this way, by adjusting the resistance value in the parallel network unit 111, the output voltage of the parallel network unit 111 can be adjusted, thereby achieving accurate control of the input voltage and current of the light emitting module 12.

Here, each bit of the gray-scale digital signal is input to the input terminal of each parallel branch. N resistors R connected in parallel_xSatisfies a factorial increasing relationship of 2:

R_n＝2¹R_n-1＝.......＝2^n-1R₁ (4)

parallel network unit 111 input resistor R_inCan be expressed as:

the output voltage V of the parallel network unit 111 can be obtained according to the formula (2)_outI.e., the voltage of the first node P, is also the input voltage of the light emitting module 12.

In the embodiment of the present application, the gray scale can be a luminance level relationship and can be represented by a multi-bit binary digital signal. In the pixel circuit, the gray scale digital signals are loaded to the input ends of the voltage division elements in parallel, the n voltage division elements are connected in parallel, and the resistance value relationship between the adjacent voltage division elements is 2 times. Thus, different gray-scale digital signals correspond to different input resistors R of the parallel network unit 111_inThereby making it possible to change the gray scaleThe digital signal is converted into a corresponding gray scale voltage, so that the light emitting module 12 generates a gray scale current according to the gray scale voltage, and the light emitting module 12 can display gray scale brightness corresponding to the gray scale digital signal.

In the embodiment of the present application, the light emitting module 12 can be realized by n voltage dividing elements connected in parallel, and 2 can be realizedⁿAnd displaying the bit gray scale.

Here, the voltage dividing elements with different resistances may correspond to different digital signals in the gray-scale digital signals. For example R₁Corresponding to the 1 st bit digital signal, R, in the gray scale digital signal₂Corresponding to the 2 nd bit digital signal, … …, R in the gray scale digital signal_nCorresponding to the n-th digital signal in the gray scale digital signal.

It can be understood that the resistance R₁To the resistance R_nOne or more resistors may be included. Alternatively, the resistance of the resistor R1 may be 500 ohms.

In the above embodiment, the resistors having resistance values satisfying the factorial relation of 2 are connected in parallel, and each resistor is connected to one bit of the gray scale digital signal, so that the gray scale digital signal can be converted into the corresponding gray scale voltage through the resistor on each parallel branch. The gray scale voltage is input into the light emitting module, and the light emitting module can obtain the gray scale current corresponding to the gray scale digital signal, so that the gray scale brightness can be accurately displayed.

In some embodiments, as shown in FIG. 2, the light module 12 may be a current mode driven light emitting device, such as a micro Light Emitting Diode (LED).

In some embodiments, when the logic high level of the gray-scale digital signal is a negative voltage, since the input terminal of the light emitting module 12 needs to be a positive voltage to normally emit light, the voltage at the output terminal of the parallel network unit 111 may be inverted, so that the light emitting module 12 normally emits light.

Fig. 3 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application. As shown in fig. 3, the signal processing module 11 further includes an inverting unit 113. The output of the parallel network unit 111 is connected to the first node P. The input terminal of the inverting unit 113 is connected to the first node P. The output terminal of the inverting unit 113 is connected to the first terminal of the light emitting module.

In the embodiment of the present application, the inverting unit 113 may be various types of voltage inverting circuits, and in some embodiments, as shown in fig. 3, the inverting unit 113 includes a resistor R_m1Resistance R_m2And a first operational amplifier U1.

The inverting input of the first operational amplifier U1 is connected to the first node P. The inverting input terminal of the first operational amplifier U1 is also connected to a resistor R_m1Are connected to each other. That is, the first terminal of the resistor Rm1 is connected between the inverting input terminal of the first operational amplifier U1 and the first node P.

The output terminal of the first operational amplifier U1 may be connected to the input terminal of the light emitting module 12 and to the resistor R_m1Are connected to each other. That is, the resistance R_m1May be connected between the output of the first operational amplifier U1 and the input of the light module 12.

The non-inverting input terminal of the first operational amplifier U1 and the resistor R_m2Are connected to each other. Resistance R_m2Is connected to ground.

In the embodiment of the present application, the resistor R_m1And a resistance R_m2The resistance values of (a) are equal. In this way, the voltage at the input terminal of the inverting unit 113 is equal to the voltage at the output terminal of the inverting unit 113, and has opposite signs. That is, when the voltage at the input terminal of the inverting unit 113 is a negative voltage, the output terminal of the inverting unit 113 is a positive voltage having the same magnitude as the negative voltage. And since no current flows through the inverting input terminal of the first operational amplifier U1, the input current and the output current of the inverting unit 113 are the same in magnitude and direction.

In the above embodiment, in the pixel circuit, the voltage output by the parallel network unit is inverted by the inverting unit, so that the light emitting module can be driven to emit light when the logic level corresponding to the digital signal is a negative voltage.

In practical applications, the light emitting module 12 may include a current mode driven light emitting device. When no current flows through the light emitting module, the light emitting module is in a light-off state. When the light-emitting module has current, the light-emitting module is in a light-emitting state. Therefore, the light emitting module generates a stroboscopic phenomenon in the whole display period. In addition, when the input voltage of the light emitting module 12 is unstable, the light emitting diode module is also prone to a stroboscopic phenomenon.

In some embodiments, in order to store electric energy in the circuit and avoid the stroboscopic phenomenon, an energy storage module may be added in the pixel circuit. Fig. 4 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application. As shown in fig. 4, the pixel circuit 10 includes a signal processing module 11, a plurality of light emitting modules 12, and at least one energy storage module 13.

When the pixel circuit 10 belongs to a row scanning circuit or a column scanning circuit, the pixel circuit 10 may include a plurality of energy storage blocks 13. And the number of the energy storage modules 13 is the same as that of the light emitting modules 12 in one pixel circuit

When the pixel circuit 10 belongs to a direct drive circuit, the pixel circuit 10 may include an energy storage module 13.

A first end of the energy storage module 13 is connected to an output end of the signal processing module 11. The second end of the energy storage module 13 is connected to a reference point.

The connection relationship of other modules in the pixel circuit is similar to the relationship between the modules of the pixel circuit in the foregoing embodiment, and the description is omitted here.

Here, the output terminal of the signal processing module 11 may include a first node P. The first node P is connected to the parallel network unit 111, to a first terminal of the light emitting module 12, and to a first terminal of the energy storage module 13. In this way, when the first node P has a non-zero voltage, that is, the output voltage of the parallel network unit 111 is non-zero, the energy storage module 13 can store energy normally, and the voltage of the first end of the energy storage module 13 is equal to the output voltage of the parallel network unit 111. Therefore, the voltage at the first end of the light emitting module 12 can be stabilized by the energy storage module 13, so that the light emitting module can stably emit light in the display period, and the stroboscopic phenomenon is avoided.

In the embodiment of the present application, the second terminal of the energy storage module 13 is equal in potential to the second terminal of the light emitting module 12. That is, when the second end of the light emitting module 12 is connected to the ground, the second end of the energy storage module 13 is connected to the ground. When the second terminal of the light emitting module 12 is connected to a reference voltage source, the second terminal of the energy storage module 13 is connected to the reference voltage source.

In some embodiments, as shown in fig. 4, the energy storage module 13 may include a capacitor C. A first terminal of the capacitor C is connected to the output terminal of the signal processing module 11. The second terminal of the capacitor C is connected to a reference point.

In some embodiments, in case the signal processing module 11 comprises the inverting unit 113, the output of the signal processing module 11 comprises the output of the inverting unit 113. A first end of the energy storage module 13 is connected to the signal transmission line between the output end of the inverting unit 113 and the first end of the light emitting module. Therefore, the voltage at the first end of the light emitting module 12 can be stabilized by the energy storage module 13, so that the light emitting module can stably emit light in the display period, and the stroboscopic phenomenon is avoided.

After one display period is finished, the energy storage module 13 may have residual electric energy, which may cause the pixel circuit to display a residual image, and therefore, the energy storage module 13 needs to be discharged, so that the energy storage module 13 is reset.

In some embodiments, fig. 5 illustrates a schematic structural diagram of another pixel circuit provided in an embodiment of the present application. As shown in fig. 5, the pixel circuit 10 includes a signal processing module 11, at least one light emitting module 12, at least one energy storage module 13, and at least one reset module 14.

Here, in one pixel circuit 10, the number of the reset modules 14 is the same as the number of the energy storage modules 13. The control terminal of the reset module 14 is connected to a reset signal RST. A first end of the reset module 14 is connected to a first end of the energy storage module 13. A second end of the reset module 14 is connected to a reference point.

Note that, when a plurality of reset blocks 14 are included in one pixel circuit 10, the pixel circuit 10 belongs to a row reset circuit or a column reset circuit, that is, a plurality of reset blocks in one pixel circuit 10 are reset at the same time.

In the embodiment of the present application, when the reset signal is the enable signal, the internal resistance of the reset module 14 is negligible when the reset module is turned on. Since the first end of the reset module 14 is connected to the first end of the energy storage module 13, the second end of the reset module 14 and the second end of the energy storage module 13 may be respectively connected to a reference point. Therefore, when the energy storage module 13 has the residual capacity, the voltage of the first end of the energy storage module 13 is not equal to the voltage of the reference point. When the reset module 14 is turned on, the voltage of the first end of the reset module 14 is substantially the same as the voltage of the reference point, and the energy storage module 13 discharges, so that the voltage of the first end of the energy storage module 13 is equal to the voltage of the reference point, and the energy storage module 13 resets.

In the embodiment of the present application, when the second end of the energy storage module 13 is connected to the ground, the second end of the reset module 14 is connected to the ground. When the second terminal of the energy storage module 13 is connected to the reference voltage source, the second terminal of the reset module 14 is connected to the reference voltage source.

In the above embodiment, the reset module is added to the pixel circuit, so that the energy storage module can be reset before being charged again, thereby preventing the display of the residual image in the pixel circuit.

In some embodiments, the reset module 14 may include a first transistor T1. As shown in fig. 5, the control terminal of the first transistor T1 is connected to a reset signal. A first terminal of the first transistor T1 is connected to a first terminal of the energy storage module 13. The second terminal of the first transistor T1 is connected to a reference point.

In the embodiment of the present application, the first transistor T1 may be a field effect transistor, or may be combined with other transistors. The type of the first transistor T1 is not limited herein.

In some embodiments, the analog voltage corresponding to the logic level of the digital signal is small in practical application, for example, the analog voltage is 3.3 volts or about 3.7 volts. The current signal output by the signal processing module 11 is not enough to drive the light emitting module to emit light, so that the current signal input to the light emitting module needs to be increased. Fig. 6 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application. As shown in fig. 6, the pixel circuit 10 may include a signal processing module 11, at least one light emitting module 12, and at least one voltage-controlled current source module 15.

In one pixel circuit 10, the voltage-controlled current source modules 15 are the same number as the light emitting modules 12.

A first input terminal of the voltage controlled current source module 15 is connected to an output terminal of the signal processing module 11. A second input terminal of the voltage-controlled current source module 15 is used for receiving the first voltage signal PVDD. The output terminal of the voltage-controlled current source module 15 is connected to the first terminal of the light emitting module 12.

In this pixel circuit 10, the energy provided by the first voltage signal PVDD enables the voltage-controlled current source module 15 to output a stable voltage, and the voltage-controlled current source module 15 can control the variation of the current signal by the voltage, that is, the input voltage of the voltage-controlled current source 15 is proportional to the output current signal.

In addition, the voltage-controlled current source module 15 may belong to a low dropout regulator, and may stabilize the output voltage of the voltage-controlled current source module 15 through voltage feedback adjustment. Thus, the voltage-controlled current source module 15 can adjust the input voltage of the light emitting module when the gray scale voltage is unchanged and the input current of the light emitting module 12 is changed, so that the input current of the light emitting module is recovered to be normal.

It should be noted that the connection relationship of other modules in the pixel circuit 10 is similar to the connection relationship of the modules of the pixel circuit in the foregoing embodiment, and for the sake of brevity, the description is omitted here.

In the above embodiments, on the one hand, the voltage-controlled current source module may make the output voltage of the signal processing module and the current signal flowing into the light emitting module be proportional, the output voltage of the signal processing module may be enough to drive the light emitting module to emit light, and the analog voltage value corresponding to the digital signal may be reduced, so that the pixel circuit is convenient for integration. On the other hand, the voltage-controlled current source module can stabilize the input voltage of the light-emitting module through the output voltage of the signal processing module, so that the input voltage of the light-emitting module is adjusted when the current signal flowing through the light-emitting module changes, the current flowing into the light-emitting module can be accurately controlled according to the gray scale digital signal, and the light-emitting module can display corresponding gray scale brightness according to the gray scale digital signal.

In some embodiments, fig. 7 illustrates a schematic structural diagram of another pixel circuit provided in this application. As shown in fig. 7, the pixel circuit 10 may include a signal processing module 11, at least one light emitting module 12, at least one energy storage module 13, at least one reset module 14, and at least one voltage-controlled current source module 15.

A first input terminal of the voltage-controlled current source module 15 is connected to a first terminal of one of the energy storage modules 13 and to an output terminal of the signal processing module 11. A second input terminal of the voltage-controlled current source module 15 is used for receiving the first voltage signal PVDD. The output terminal of the voltage-controlled current source module 15 is connected to the first terminal of the light emitting module 12.

In the above embodiment, the occurrence of a stroboscopic phenomenon can be reduced by the energy storage module in the pixel circuit, the reset module in the pixel circuit can release the residual electric energy in the energy storage module before the energy storage module is charged next time, and the analog voltage value corresponding to the digital signal can be reduced by the voltage control current source module in the pixel circuit, so that the output voltage of the signal processing module is enough to drive the light-emitting module to emit light, and the current signal flowing into the light-emitting module is accurately controlled, so that the light-emitting module can display the corresponding gray scale brightness according to the gray scale digital signal.

In some embodiments, as shown in fig. 6 and 7, the voltage-controlled current source module 15 includes an error amplifying subunit 151 and an adjusting subunit 152;

a first input of the error amplification subunit 151 is connected to an output of the signal processing module 11.

A second input terminal of the detection subunit 151 is connected to a signal transmission line between the first terminal of the adjustment subunit 152 and the first terminal of the light emitting module 12. That is, the second input terminal of the detection subunit 151 is connected to the first terminal of the adjustment subunit 152, and is also connected to the first terminal of the light emitting module 12.

The output of the detection subunit 151 is connected to the control terminal of the adjustment subunit 152. The second terminal of the adjusting subunit 152 is used for accessing the first voltage signal PVDD.

Here, the voltage-controlled current source module 15 may stabilize the current input to the light emitting module 12 in a voltage feedback manner. In the embodiment of the present application, the detection subunit 151 may include an error comparator for comparing the output voltage of the signal processing module 11 with the input voltage of the light emitting module 12, obtaining a voltage error between the output voltage and the input voltage, and amplifying the voltage error. The adjusting subunit 152 is configured to adjust the input voltage flowing into the light emitting module 12 according to the amplified voltage error output by the detecting subunit 151, so as to stabilize the input current of the light emitting module 12.

In the above embodiment, the voltage error between the output voltage of the signal processing module 11 and the input voltage of the light emitting module 12 is detected by the detecting sub-unit 151, and the input voltage of the light emitting module 12 is precisely adjusted by the adjusting sub-unit 152 according to the output voltage error of the detecting sub-unit 151, so as to precisely control the input current of the light emitting module, so that the light emitting module 12 displays the gray-scale luminance corresponding to the gray-scale digital signal.

In some embodiments, as shown in fig. 6 and 7, the detection sub-unit 151 may include a second operational amplifier U2, and the adjustment sub-unit 152 may include a second transistor T2.

The non-inverting input of the second operational amplifier U2 is connected to the output of the signal processing module 11.

An inverting input terminal of the second operational amplifier U2 is connected to a signal transmission line between the first terminal of the second transistor T2 and the first terminal of the light emitting module 12. That is, the inverting input terminal of the second operational amplifier U2 is connected to the drain of the second transistor T2 and also to the first terminal of the light emitting module 12.

The output terminal of the second operational amplifier U2 is connected to the control terminal of the second transistor T2. A second terminal of the second transistor T2 is used for receiving the first voltage signal PVDD.

Here, the first voltage signal PVDD is used to drive the second transistor T2 to turn on. The second transistor T2 may be a field effect transistor, but may also be another type of transistor. In the embodiment of the present application, the type of the second transistor T2 is not limited. In the case that the second transistor T2 may be a field effect transistor, the control terminal may be a gate, the first terminal may be a source, and the second terminal may be a drain. Alternatively, the second terminal may be a source and the first terminal may be a drain.

It should be noted that, in the embodiment of the present application, the output voltage of the second operational amplifier U2 is smaller than the saturation region voltage corresponding to the second transistor T2. The maximum voltage of the variable resistance region corresponding to the second transistor T2 is not greater than the analog voltage corresponding to the grayscale digital signal.

The magnitude of the first voltage signal PVDD is related to an internal structure of the light emitting module, for example, in a case that the light emitting module is a light emitting diode, the magnitude of the first voltage signal PVDD is related to the number of serially connected wicks in the light emitting diode.

In the embodiment of the present application, when the second transistor T2 is in the variable resistance region, the current signal I of the light emitting module_LEDCan be expressed as:

wherein, beta₁Is the current amplification factor of the second transistor T2. U is the output voltage of the second operational amplifier U2.

Due to beta₁Is sufficiently large that, as a result,

thereby the current signal I_LEDIs not affected by the first voltage signal PVDD, and the current signal I_LEDIs related to the output voltage of the second operational amplifier U2 so that different currents can be obtained from different voltages.

In some embodiments, the adjusting subunit 152 may include a plurality of transistors, and thus, the precise control of the current signal is facilitated by the combination of the plurality of transistors. Fig. 8 shows a schematic structural diagram of an adjustment subunit provided in an embodiment of the present application. As shown in fig. 8, the internal structure of the adjusting sub-unit 152 is illustrated by taking the example that the adjusting sub-unit 152 includes the second transistor T2 and the third transistor T3.

A control terminal of the second transistor T2 is connected to an output terminal of the second operational amplifier U2. A second terminal of the second transistor T2 is coupled to a control terminal of the third transistor T3. A second terminal of the second transistor T2 is used for receiving the first voltage signal PVDD.

A second terminal of the third transistor T3 is for receiving the first voltage signal PVDD. A first terminal of the third transistor T3 is connected to the signal transmission line between the inverting input terminal of the second operational amplifier U2 and the first terminal of the light emitting module 12. That is, the third terminal of the third transistor T3 is connected to the inverting input terminal of the second operational amplifier U2 and also connected to the first terminal of the light emitting module 12.

By analogy, when the adjusting subunit 152 includes H transistors, and H is an integer greater than 1, the second terminal of the H-th transistor is used for accessing the first voltage signal PVDD. The first terminal of the H-th transistor is connected to the signal transmission line between the inverting input terminal of the second operational amplifier U2 and the first terminal of the light emitting module 12. The control terminal of the H-th transistor is connected to the first terminal of the H-1 th transistor.

In the embodiment of the present application, the current signal I of the light emitting module is when the second transistor T2 and the third transistor T3 are in the variable resistance region_LEDCan be expressed as:

wherein, beta₁Is the current amplification factor, beta, of the second transistor T2₂Is a current amplification factor of the third transistor T3. U is the output voltage signal of the second operational amplifier U2.

Due to beta₁And beta₂Is sufficiently large that, as a result,

thereby current signal I_LEDIs not affected by the first voltage signal PVDD, and the current signal I_LEDIs related to the output voltage of the second operational amplifier U2 so that different current signals can be obtained according to different voltages.

In some embodiments, in order to enable the display device formed by the pixel circuits to realize row scanning or column scanning, a scanning gate switch is added in the pixel circuits. Fig. 9 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application. As shown in fig. 9, the pixel circuit 10 includes a signal processing module 11, at least one light emitting module 12, and at least one first gate control module 16.

In the pixel circuit 10, the first gate control modules 16 are the same as the light emitting modules 12 in number

The control terminal of the first gating control module 16 is connected to the control signal. A first end of the first gating control module 16 is connected to an output end of the signal processing module 11. A second terminal of the first gating control module 16 is connected to a first terminal of the light emitting module 12.

Here, when the control signal is the enable signal, the first gate control module 16 is turned on, and the current signal output by the signal processing module flows into the light emitting module 12 through the first gate control module 16, so that the light emitting module 12 emits light.

When the control signal is an off signal, the first gating control module 16 is not turned on, the current signal output by the signal processing module is disconnected from the light emitting module 12, and the light emitting module 12 cannot emit light.

In the embodiment of the present application, the control signal may be provided by the scan line. A plurality of pixel circuits may be connected to one scan line.

In the above embodiment, the scan signal accessed by the first gate control module can control the operating state of the pixel circuit, so that the pixel circuit can implement row scanning or column scanning.

In some embodiments, in order to avoid strobing of the pixel circuits, the display device formed by the pixel circuits may implement row scanning or column scanning, and a scan gating switch and an energy storage module may be added to the pixel circuits. As shown in fig. 9, the pixel circuit 10 may further include at least one energy storage module 13.

The control terminal of the first gating control module 16 is connected to the control signal. A first end of the first gating control module 16 is connected to an output end of the signal processing module 11.

The second end of the first gating control module 16 is connected to the signal transmission line between the first end of the light emitting module 12 and the first end of the energy storage module 13. That is, the second terminal of the first gating control module 16 is connected to the first terminal of the light emitting module 12 and also connected to the first terminal of the energy storage module 13.

In the embodiment of the present application, the connection relationship of other modules in the pixel circuit is similar to that of the pixel circuit in the previous embodiment, and for brevity, the description is omitted here.

In some embodiments, as shown in fig. 9, the pixel circuit 10 may further include at least one reset module 14. Thus, the display device formed by the pixel circuits can realize row scanning or column scanning, and row resetting or column resetting.

Here, the connection relationship between the reset module and the energy storage module is similar to that in the foregoing embodiment, and for the sake of brevity, the description is omitted here.

In some embodiments, in order to enable the display device formed by the pixel circuit to realize row scanning or column scanning and further accurately control the current flowing through the light-emitting module, a scanning gating switch and a voltage-controlled current source module can be added in the pixel circuit. Fig. 10 shows a schematic structural diagram of another pixel circuit provided in the embodiment of the present application. As shown in fig. 10, the pixel circuit 10 may include one signal processing module 11, a plurality of light emitting modules 12, and at least one voltage-controlled current source module 15 and at least one first gate control module 16.

The control terminal of the first gating control module 16 is connected to the control signal. A first end of the first gating control module 16 is connected to an output end of the signal processing module 11. A second terminal of the first gating control module 16 is connected to a first input terminal of the voltage controlled current source module 15.

Here, when the control signal is the enable signal, the first gate control module 16 is turned on, and the current signal output by the signal processing module flows into the light emitting module 12 through the first gate control module 16 and the voltage-controlled current source module 15, so that the light emitting module 12 emits light.

When the control signal is an off signal, the first gating control module 16 is not turned on, the signal processing module is disconnected from the voltage-controlled current source module 15, the voltage-controlled current source module 15 is not turned on, and the light-emitting module 12 cannot emit light.

In some embodiments, as shown in fig. 10, the pixel circuit 10 may further include at least one reset module 14 and an energy storage module 13. Therefore, stroboflash and afterimage of the pixel circuit can be avoided. As shown in fig. 10, the control terminal of the first gating control module 16 is connected to the control signal. A first end of the first gating control module 16 is connected to an output end of the signal processing module 11.

The second end of the first gating control module 16 is connected to a signal transmission line between the first input end of the voltage-controlled current source and the first end of the energy storage module 13. That is, the second terminal of the first gating control module 16 is connected to the first terminal of the light emitting module 12 and also connected to the first terminal of the energy storage module 13.

In some embodiments, as shown in fig. 9 to 10, the first gate control module 16 may include a fourth transistor T4.

In the embodiment of the present application, the fourth transistor T4 may be a field effect transistor, or another type of transistor. The type of the fourth transistor is not limited here.

Based on the pixel circuit, the embodiment of the application also provides a display panel. Fig. 11 shows a schematic structural diagram of a display panel provided in an embodiment of the present application. As shown in fig. 11, the display panel 1200 includes a plurality of pixel circuits 1201. The pixel circuit 1201 is a pixel circuit 10 provided in any embodiment of the present application.

In some embodiments, when the driving mode of the pixel circuit is a direct driving mode, the pixel circuit may include a signal processing module and a light emitting module. Fig. 12 shows a schematic structural diagram of a direct-drive display panel provided in an embodiment of the present application. As shown in fig. 12, in the case where the pixel circuit 1201 includes one signal processing module 12011 and one light emitting module 12012, a plurality of pixel circuits form an X row and Y column pixel circuit array, X being a positive integer, and Y being a positive integer.

The signal processing module 12011 is the same as the signal processing module provided in any of the embodiments of the present application.

The input end of the signal processing module 12011 is connected to the gray-scale digital signal, and the output end of the signal processing module 12011 is connected to the first end of the light emitting module 12012. A first end of the light emitting module 12012 is connected to a reference point.

In the above embodiment, the signal processing module may convert the gray scale digital signal corresponding to the display signal into a gray scale voltage, so as to control a gray scale current input to the light emitting module through the gray scale voltage, so that the pixel circuit displays gray scale luminance corresponding to the gray scale voltage. Therefore, the current in the pixel circuit can be accurately controlled without an additional compensation circuit or changing the voltage of the input pixel circuit, so as to achieve the accurate control of the gray scale of the display picture. Meanwhile, the driving chip is prevented from being adopted to drive and control each pixel circuit to emit light, so that the cost for manufacturing the display panel is reduced.

In some embodiments, to avoid strobing and image sticking of the display panel, the pixel circuit 1201 may further include a storage module 12013 and a reset module 12014. As shown in fig. 12, in the case where the pixel circuit includes one signal processing module 12011, one light emitting module 12012, one reset module 12014, and one energy storage module 12013, the display panel 1200 further includes X reset signal lines (i.e., RST1 to RSTX) extending in the row direction and arranged in the column direction. The control terminal of the reset module 12014 in each pixel circuit row is connected to the output terminal of the reset signal line in the row. The input end of the reset signal line is used for accessing a reset signal.

Here, a first end of the energy storage module 12013 is connected to the signal processing module 12011. A second end of the energy storage module 12013 is connected to a reference point.

A first terminal of the reset module 12014 is connected to a first terminal of the energy storage module 12013. A second terminal of the reset module 12014 is connected to a reference point.

In the above embodiments, the display panel can simultaneously reset the pixel circuits of each row through a plurality of reset signal lines.

In some embodiments, fig. 13 illustrates a schematic structural diagram of another direct-drive display panel provided in an embodiment of the present application. As shown in fig. 13, in the case where the pixel circuit 1201 includes one signal processing module 12011, one light emitting module 12012, one reset module 12014, and one energy storage module 12013, the display panel 1200 further includes Y reset signal lines (i.e., RST1 to RSTY) extending in the column direction and arranged in the row direction. The control terminal of the reset module 12014 in each pixel circuit 1201 in each pixel circuit column is connected to the output terminal of the reset signal line of the column. The input end of the reset signal line is used for accessing a reset signal.

A first end of the energy storage module 12013 is connected to the signal processing module 12011. A second end of the energy storage module 12013 is connected to a reference point.

In the above embodiments, the display panel can simultaneously reset the pixel circuits of each column through a plurality of reset signal lines.

In some embodiments, as shown in fig. 12 and 13, the pixel circuit 1201 may further include a voltage controlled current source module 12015.

A first input terminal of the voltage-controlled current source module 12015 is connected to a first terminal of an energy storage module 12013, and is further connected to an output terminal of the signal processing module 12011. A second input terminal of the voltage-controlled current source module 12015 is configured to receive the first voltage signal PVDD. The output terminal of the voltage-controlled current source module 12015 is connected to the first terminal of the light emitting module 12012.

In some embodiments, when the driving manner of the pixel circuit is line scan driving, the pixel circuit includes one signal processing module 12011 and a plurality of light emitting modules 12012. Fig. 14 shows a schematic structural diagram of a row-driving display panel according to an embodiment of the present application. As shown in fig. 14, in the case where the pixel circuit 1201 includes one signal processing module 12011 and a plurality of light emitting modules 12012, the plurality of light emitting modules 12012 are arranged in P rows, and the plurality of pixel circuits 1201 form L pixel circuit columns, L being a positive integer, and P being an integer greater than 1.

Each column of pixel circuits includes P first gate control modules 12016, and one first gate control module 12016 corresponds to one light emitting module 12012.

The display panel 1200 further includes L data lines (i.e., data1 through dataL) extending in the column direction and arranged in the row direction and P SCAN lines (i.e., SCAN1 through SCANP) extending in the row direction and arranged in the column direction.

The control terminals of the first gate control modules 12016 in the same row are connected to the signal output terminals of the scan lines corresponding to the row. The second terminal of the first gating control module 12016 is connected to the first terminal of the light emitting module 12012, and the signal input terminal of the scan line is used for receiving a scan signal.

The first end of the first gating control module 12016 in the same column is connected to the signal output end of the data line corresponding to the column. The signal input end of the data line is connected with the output end of the signal processing module 1201.

In the above embodiments, the display panel can be line scan driven to light up through the data lines and the scan lines.

In some embodiments, when the driving manner of the pixel circuit is column scan driving, the pixel circuit includes one signal processing module 12011 and a plurality of light emitting modules 12012. Fig. 15 shows a schematic structural diagram of a column driving display panel according to an embodiment of the present application. As shown in fig. 15, in the case where the pixel circuit 1201 includes one signal processing module 12011 and a plurality of light emitting modules 12012, the plurality of light emitting modules 12012 are arranged in P rows, and the plurality of pixel circuits 1201 form L pixel circuit columns, L being a positive integer, and P being an integer greater than 1.

Each column of the pixel circuits includes P first gate control modules 12016. One first gate control module 12016 corresponds to one light emitting module 12012.

The display panel 1200 further includes L data lines (i.e., data1 to dataL) extending in the column direction and arranged in the row direction and L SCAN lines (i.e., SCAN1 to scall) extending in the column direction and arranged in the row direction.

The control terminal of the first gate control module 12016 in the same column is connected to the signal output terminal of the scan line corresponding to the column. A second terminal of the first gating control module 12016 is connected to a first terminal of the light emitting module 12012.

The first end of the first gate control module 12016 in the same column is connected to the signal output end of the data line corresponding to the column. And the signal input end of the data line is connected with the output end of the signal processing module.

In the above embodiments, the display panel can be lit by column scanning driving through the data lines and the scanning lines.

In some embodiments, when the driving manner of the pixel circuit is line scan driving, the pixel circuit includes one signal processing module 12011 and a plurality of light emitting modules 12012. Fig. 16 shows a schematic structural diagram of another row-driving display panel provided in an embodiment of the present application. As shown in fig. 16, in the case where the pixel circuit 1201 includes one signal processing module 12011 and a plurality of light emitting modules 12012, the plurality of light emitting modules 12012 are arranged in L columns, and the plurality of pixel circuits 1201 form P pixel circuit rows, L being a positive integer, and P being an integer greater than 1.

The display panel 1200 further includes P data lines (i.e., data1 to dataP) extending in the row direction and arranged in the column direction and P SCAN lines (SCAN1 to SCANP) extending in the row direction and arranged in the column direction.

The control terminals of the first gate control modules 12016 in the same row are connected to the signal output terminals of the scan lines corresponding to the row. A second terminal of the first gating control module 12016 is connected to a first terminal of the light emitting module 12012.

The first end of the first gating control module 12016 in the same row is connected to the signal output end of the data line corresponding to the row. And the signal input end of the data line is connected with the output end of the signal processing module.

In some embodiments, when the driving manner of the pixel circuit is column scan driving, the pixel circuit includes one signal processing module 12011 and a plurality of light emitting modules 12012. Fig. 17 is a schematic structural diagram of a column scanning display panel according to an embodiment of the present application. As shown in fig. 17, in the case where the pixel circuit 1201 includes one signal processing module 12011 and a plurality of light emitting modules 12012, the plurality of light emitting modules 12012 are arranged in L columns, and the plurality of pixel circuits 1201 form P pixel circuit columns, L being a positive integer, and P being an integer greater than 1.

Each column of the pixel circuit 1201 includes P first gate control modules 12016, and one first gate control module 12016 corresponds to one light emitting module 12012.

The display panel 1200 further includes P data lines (i.e., data1 to dataP) extending in the row direction and arranged in the column direction and L SCAN lines (i.e., SCAN1 to scall) extending in the column direction and arranged in the row direction.

The control terminal of the first gate control module 12016 in the same column is connected to the signal output terminal of the scan line corresponding to the column. The second terminal of the first gating control module 12016 is connected to the first terminal of the light emitting module 12012 corresponding to the row where the first gating control module is located.

The first end of the first gating control module 12016 in the same row is connected to the signal output end of the data line corresponding to the row. The signal input end of the data line is connected to the output end of the signal processing module 12011.

In some embodiments, to avoid strobing and image sticking on the display surface, as shown in fig. 14 to 17, the pixel circuit 1201 further includes P reset modules 12014 and P energy storage modules 12013.

One reset module 12014 corresponds to one light emitting module 12012, and one energy storage module 12013 corresponds to one light emitting module 12012.

A first terminal of the energy storage module 12013 is connected to a second terminal of the first gating control module 12016. A second end of the energy storage module 12013 is connected to a reference point.

Here, the display panel 1200 further includes P reset signal lines (i.e., RST1 to RSTP) extending in the row direction and arranged in the column direction. The control terminal of the reset module 12014 in each row is connected to the signal output terminal of the reset signal line in the row. The signal input end of the reset signal line is used for accessing a reset signal.

Or, the display panel 1200 further includes L reset signal lines extending in the column direction and arranged in the row direction, and the control terminal of the reset module 12014 in each column is connected to the signal output terminal of the reset signal line in the column.

In the above embodiments, the reset module and the energy storage module are added to the pixel circuit, so that the stroboscopic and image sticking phenomena of the display panel can be avoided.

In some embodiments, in order to reduce the output voltage of the signal processing module, as shown in fig. 14 to 17, the pixel circuit 1201 may further include P voltage-controlled current source modules 12015.

A first input terminal of the voltage-controlled current source module 12015 is connected to a second terminal of a first gating control module 12016. A second input terminal of the voltage-controlled current source module 12015 is configured to receive the first voltage signal PVDD. The output terminal of the voltage-controlled current source module 12015 is connected to the first terminal of the light emitting module 12.

Alternatively, the first input terminal of the voltage-controlled current source module 12015 is connected to a signal transmission line between the second terminal of a first gating control module 12016 and the first terminal of the energy storage module 12013. A second input terminal of the voltage-controlled current source module 12015 is configured to receive the first voltage signal PVDD. The output terminal of the voltage-controlled current source module 12015 is connected to the first terminal of the light emitting module 12.

In the above embodiment, by adding the voltage-controlled current source module to the pixel circuit, the output voltage of the signal processing module can be reduced when the display panel scans in rows or columns, and the current flowing into the light-emitting module can be further accurately controlled, so that the gray scale brightness displayed by the light-emitting module according to the gray scale digital signal is more accurate.

Based on the display panel, the embodiment of the application also provides a display device. Fig. 18 is a schematic structural diagram of a display device according to an embodiment of the present application. As shown in fig. 18, the display device 1800 includes any one of the display panels 1801 provided in the embodiments of the present application. For an embodiment of the display device, reference may be made to the above-mentioned embodiment of the display panel, and repeated descriptions are omitted.

In a specific implementation, the display device may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are understood by those skilled in the art, and are not described herein in detail, nor should they be construed as limiting the present invention.

While the present application has been described with reference to the above embodiments, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the present application, and in particular, features described in the various embodiments may be combined in any manner as long as there is no structural conflict. The present application is not intended to be limited to the particular embodiments disclosed herein but is to cover all embodiments that may fall within the scope of the appended claims.

It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.

As mentioned above, only the specific embodiments of the present application are described, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered within the scope of the present application.

Claims

1. A pixel circuit, comprising: the device comprises a signal processing module and at least one light emitting module;

the signal processing module comprises a parallel network unit and a voltage division unit; the parallel network unit comprises n parallel voltage division elements, the input end of each voltage division element is respectively connected with a gray scale digital signal corresponding to a data signal, and the output end of each voltage division element is connected with a first node; n is an integer greater than 1;

the first end of the voltage dividing unit is connected with the first node, and the second end of the voltage dividing unit is connected with a reference point;

2. The pixel circuit according to claim 1, wherein the voltage dividing element comprises resistors, and the resistance relationship of n parallel resistors satisfies a factorial increasing relationship of 2.

3. The pixel circuit according to claim 1, wherein the signal processing module further comprises an inverting unit;

the input end of the inverting unit is connected with the first node, the output end of the parallel network unit is connected with the first node, and the output end of the inverting unit is connected with the first end of the light-emitting module.

4. The pixel circuit according to claim 1, further comprising at least one energy storage module, wherein a first terminal of the energy storage module is connected to the output terminal of the signal processing module, and a second terminal of the energy storage module is connected to a reference point.

5. The pixel circuit according to claim 4, further comprising at least one reset module, wherein a control terminal of the reset module is connected to a reset signal, a first terminal of the reset module is connected to a first terminal of the energy storage module, and a second terminal of the reset module is connected to a reference point.

6. The pixel circuit of claim 1, further comprising at least one voltage controlled current source module;

the first input end of the voltage-controlled current source module is connected with the output end of the signal processing module, the second input end of the voltage-controlled current source module is used for accessing a first voltage signal, and the output end of the voltage-controlled current source module is connected with the first end of the light-emitting module.

7. The pixel circuit of claim 6, wherein the voltage-controlled current source module comprises a detection subunit and an adjustment subunit;

a first input end of the detection subunit is connected with the first node, a second input end of the detection subunit is connected with a signal transmission line between a first end of the adjustment subunit and a first end of the light-emitting module, and an output end of the detection subunit is connected with a control end of the adjustment subunit;

and the second end of the adjusting subunit is used for accessing a first voltage signal.

8. The pixel circuit according to any of claims 1 to 7, further comprising at least one first gate control module;

the control end of the first gating control module is connected with a control signal, the first end of the first gating control module is connected with the output end of the signal processing module, and the second end of the first gating control module is connected with the first end of the light emitting module.

9. A display panel comprising a plurality of pixel circuits, wherein the pixel circuits are the pixel circuits according to any one of claims 1 to 8.

10. The display panel according to claim 9, wherein in a case where the pixel circuit includes one signal processing module and one light emitting module, the plurality of pixel circuits form an X row and Y column pixel circuit array, X being a positive integer, and Y being a positive integer.

11. The display panel according to claim 10, wherein in a case where the pixel circuit includes one reset module and one energy storage module, the display panel further includes X reset signal lines extending in a row direction and arranged in a column direction, a control terminal of the reset module in each pixel circuit row is connected to an output terminal of the reset signal line in the row, and an input terminal of the reset signal line is used for receiving a reset signal;

or the display panel further comprises Y reset signal lines extending along the column direction and arranged along the row direction, the control end of the reset module in each pixel circuit column is connected with the output end of the reset signal line in the column, and the input end of the reset signal line is used for accessing a reset signal;

the first end of the energy storage module is connected to the output end of the signal processing module, and the second end of the energy storage module is connected with a reference point;

the first end of the reset module is connected with the first end of the energy storage module, and the second end of the reset module is connected with a reference point.

12. The display panel according to claim 9, wherein in a case where the pixel circuit includes one signal processing module and a plurality of light emitting modules, the plurality of light emitting modules are arranged in P rows, and the plurality of pixel circuits form L pixel circuit columns, L being a positive integer, and P being an integer greater than 1;

each column of the pixel circuits comprises P first gating control modules, and one first gating control module corresponds to one light emitting module;

the display panel further comprises L data lines extending along the column direction and arranged along the row direction and P scanning lines extending along the row direction and arranged along the column direction, the control end of the first gating control module positioned in the same row is connected with the signal output end of the scanning line corresponding to the row where the first gating control module is positioned, the second end of the first gating control module is connected with the first end of the light emitting module, and the signal input end of the scanning line is used for accessing a scanning signal;

the first end of the first gating control module positioned in the same column is connected with the signal output end of the data line corresponding to the column, and the signal input end of the data line is connected with the output end of the signal processing module.

13. The display panel according to claim 9,

in the case where the pixel circuit includes one signal processing module and a plurality of light emitting modules, the plurality of light emitting modules are arranged in P rows, and the plurality of pixel circuits form L pixel circuit columns, L being a positive integer, and P being an integer greater than 1;

each column of the pixel circuits comprises P first gating control modules, and one first gating control module corresponds to one light-emitting module;

the display panel also comprises L data lines extending along the column direction and arranged along the row direction and L scanning lines extending along the column direction and arranged along the row direction, the control end of the first gating control module positioned in the same column is connected with the signal output end of the scanning line corresponding to the column where the first gating control module is positioned, and the second end of the first gating control module is connected with the first end of the light-emitting module;

14. The display panel according to claim 9,

in the case where the pixel circuit includes one signal processing module and a plurality of light emitting modules, the plurality of light emitting modules are arranged in L columns, and the plurality of pixel circuits form P pixel circuit rows, L being a positive integer, P being an integer greater than 1;

the display panel also comprises P data lines extending along the row direction and arranged along the column direction and P scanning lines extending along the row direction and arranged along the column direction, the control end of the first gating control module positioned in the same row is connected with the signal output end of the scanning line corresponding to the row where the first gating control module is positioned, and the second end of the first gating control module is connected with the first end of the light-emitting module;

the first end of the first gating control module positioned on the same row is connected with the signal output end of the data line corresponding to the row, and the signal input end of the data line is connected with the output end of the signal processing module.

15. The display panel according to claim 9,

the display panel also comprises P data lines extending along the row direction and arranged along the column direction and L scanning lines extending along the column direction and arranged along the row direction, the control end of the first gating control module positioned in the same column is connected with the signal output end of the scanning line corresponding to the column where the first gating control module is positioned, and the second end of the first gating control module is connected with the first end of the light-emitting module;

16. The display panel according to any one of claims 12 to 15, wherein the pixel circuit further comprises P reset modules and P energy storage modules, and one reset module corresponds to one light emitting module and one energy storage module corresponds to one light emitting module;

the first end of the energy storage module is connected with the second end of the first gating control module, and the second end of the energy storage module is connected with a reference point;

the first end of the reset module is connected with the first end of the energy storage module, and the second end of the reset module is connected with a reference point;

the display panel also comprises P reset signal lines which extend along the row direction and are arranged along the column direction, the control end of the reset module positioned in each row is connected with the signal output end of the reset signal line of the row, and the signal input end of the reset signal line is used for accessing a reset signal;

or the display panel further comprises L reset signal lines extending along the column direction and arranged along the row direction, and the control end of the reset module positioned in each column is connected with the signal output end of the reset signal line in the column.

17. A display device characterized in that it comprises a display panel according to any one of claims 9 to 16.