CN210119692U - Calibration and power supply control circuit capable of eliminating power-on risk - Google Patents
Calibration and power supply control circuit capable of eliminating power-on risk Download PDFInfo
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- CN210119692U CN210119692U CN201921181263.1U CN201921181263U CN210119692U CN 210119692 U CN210119692 U CN 210119692U CN 201921181263 U CN201921181263 U CN 201921181263U CN 210119692 U CN210119692 U CN 210119692U
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Abstract
The utility model relates to a can eliminate scaling and power control circuit of power-on risk has solved and has exported the unsteady state when scaling and power control circuit exist latch chip power-on in the current hyperspectral imager system controller to lead to the inside OC instruction execution channel of relay driver chip to switch on, cause the problem that the malfunction appears in follow-up circuit. The circuit comprises 3 power chips, a latch chip, a relay driving chip and two relays; the MR pin of the latch chip is connected with an RC circuit; the CP pin of the latch chip is connected with the OR gate chip; a750 ohm resistor is connected in series between each output pin of the latch chip and each input pin of the relay drive chip, and is connected with a 510 ohm resistor in a grounding mode.
Description
Technical Field
The utility model belongs to the technical field of electricity, concretely relates to can eliminate scaling and power control circuit of power-on risk.
Background
The hyperspectral imager system is used for acquiring hyperspectral image data in a global target area, supporting business work such as national environment monitoring, disaster prevention and reduction and the like, and simultaneously providing satellite data resource support and business application service for a plurality of fields such as national resources, water conservancy, agriculture, forestry, earthquakes and the like.
The hyperspectral imager system is divided into 3 single machines which are respectively a main body, a signal processor and a controller. The main body realizes photoelectric conversion of visible-wave infrared two-channel spectral imaging information; the single signal processor comprises 2 compression circuits, 1 infrared signal processing circuit, 1 refrigerator driving circuit and 1 group of secondary power supply modules (providing secondary power supplies of visible, infrared, compression and refrigeration circuits); the controller realizes system operation control and telemetering amount acquisition.
The spectrometer controller is an important component of a hyperspectral imager system and mainly completes the following functions:
and receiving a bus remote control command and a remote measurement command issued by the satellite data management system.
And receiving an indirect control command issued by the satellite data management system.
Receiving the power supply voltage of the main and standby power supplies of +30.5V from a satellite power supply system.
And outputting direct telemetering information of the satellite data management system.
Responding to the bus remote control command and forwarding the bus to the parameter setting command and the control command of the visible light imaging circuit, the infrared light imaging circuit and the compression coding circuit.
And responding to the bus calibration remote control command and setting calibration work.
Collecting the working voltages of the visible light imaging circuit, the infrared light imaging circuit and the compression coding circuit.
And receiving the internal working state information of the visible light imaging circuit, the infrared light imaging circuit and the compression coding circuit through an internal bus.
The communication with the satellite number pipe subsystem adopts a CAN bus, and the communication speed is 307.2 kbps.
The internal bus adopts an RS485 bus, the communication speed is 57600bps, two bidirectional RS485 buses and two unidirectional output RS485 buses are respectively designed on the main backup, and an FPGA is adopted between the RS485 buses and the CPU for serial-parallel conversion.
The hyperspectral imager systems all need a controller for control, and the existing controller mainly comprises an analog quantity telemetering circuit, a lower computer control circuit, a calibration and power supply control circuit, a swing mirror drive control circuit, a relay control circuit and a secondary power supply module; the calibration power supply and the control circuit mainly perform the following steps in the control process:
1. the spectrum calibration on visible light and infrared stars is driven by a power-on and power-off instruction, and the calibration power is converted;
2. the visible light imaging circuit is powered on or off, the compression coding circuit is powered on or off, the instruction execution function is realized, and a secondary power supply enabling signal is output to a secondary power supply module in the signal processor;
3. the infrared focal plane +10V is driven by a power-on/off instruction, and an OC control signal is output to the signal processor;
4. and the second pulse signal receiving, monitoring and forwarding functions.
The existing calibration and power control circuit mainly comprises a circuit block diagram as shown in the following figure 1, and comprises 3 MSK5130 power chips, wherein a driving control signal of a calibration control relay is generated by a lower computer circuit, is latched by a 54HC573 latch chip and then is driven and output by an LB8169 relay driving chip to generate driving so as to control the attraction of the relay. However, when the latch 54HC573 of the conventional scaling and power control circuit is powered on, an unstable state is output, and when the output is 1, the OC instruction execution channel inside the subsequent LB8169 relay driver chip is turned on, which causes a malfunction of the relay coil, which results in effective enabling of the secondary power module and generation of load current.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a can eliminate scaling and power control circuit of power-on risk has solved and has exported the indefinite state when scaling and power control circuit exist latch chip power-on in the current hyperspectral imager system controller to lead to relay driver chip inside OC instruction execution channel to switch on, cause the problem that the malfunction appears in follow-up circuit.
The utility model discloses a concrete technical scheme is:
the utility model provides a calibration and power supply control circuit capable of eliminating power-on risks, which comprises 3 power supply chips, a latch chip, a relay driving chip and two relays;
the improvement is as follows: the MR pin of the latch chip is connected with an RC circuit; the CP pin of the latch chip is connected with the OR gate chip;
a750 ohm resistor is connected in series between each output pin of the latch chip and each input pin of the relay drive chip, and is connected with a 510 ohm resistor in a grounding mode.
Further, the model number of the latch chip is 54AC273 or 74AC273, and the model number of the or gate chip is 54HC32 or 74HC 32.
Further, the model of the relay driving chip is LB 8169.
Further, the relay driving chip is provided with four input pins.
The utility model has the advantages that:
the utility model discloses a latch chip and or a chip have been changed with power control circuit in current calibration, add the RC circuit on the latch chip simultaneously, divider resistance and ground resistance have concatenated between latch chip and relay driver chip, thereby calibration and power control circuit exist latch chip on the time output unsteady state in having solved current hyperspectral imager system controller, thereby lead to the inside OC instruction execution channel of relay driver chip to switch on, cause the problem of malfunction to appear in follow-up circuit, make calibration and power control circuit safer, reliable use.
Drawings
FIG. 1 is a schematic block diagram of a prior art scaling power supply and control circuit;
fig. 2 is a schematic block diagram of a calibration power supply and a control circuit provided by the present invention;
fig. 3 is a schematic structural diagram of the calibration power supply and the control circuit provided by the present invention;
fig. 4 is an internal schematic diagram of a relay driver chip LB 8169;
FIG. 5 shows the latch chip 54 with AC273VCC power supply terminals and Q0A voltage change curve graph of the power-on process of the output end;
fig. 6 is a graph of input voltage and load current of a relay driver chip LB 8169;
fig. 7 is a waveform chart of the output signal of the latch chip 54AC273 and the reset signal of the lower circuit one-chip microcomputer 80C 32.
Detailed Description
To make the objects, advantages and features of the present invention clearer, the following description of the present invention will be made in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more fully apparent from the following description and appended claims. It should be noted that: the drawings are in a very simplified form and are not to precise scale, and are provided solely for the purpose of facilitating and distinctly aiding in the description of the embodiments of the present invention; secondly, the structures shown in the drawings are often part of the actual structure; again, the drawings may require different emphasis, sometimes on different proportions.
Based on the problem that current calibration and power control circuit appear, the utility model provides a can eliminate calibration and power control circuit's of power-on risk concrete embodiment, as shown in fig. 2 and 3:
the circuit comprises 3 power chips (the model of each of the three power chips in the embodiment is MSK5130), a latch chip (the model of the latch chip can be 54AC273 or 74AC273, and in the embodiment, 54AC273 is adopted), a relay driving chip (the model of the relay driving chip in the embodiment is LB8169) and two relays; wherein, the MR pin of the AC273 of the latch chip 54 is connected with the RC circuit; the CP pin of the latch chip 54AC273 is connected to an or gate chip (or gate chip type 54HC32 or 74HC32, in this embodiment, the type of the latch chip 54AC273 or gate chip is 54HC 32); a750 ohm resistor is connected in series between each output pin of the latch chip and each input pin of the relay drive chip, and is connected with a 510 ohm resistor in a grounding mode.
More specifically: the driving chip LB8169 of the present embodiment has four input pins INA1, INB1, INC1 and IND1, and the corresponding output pins of the corresponding latch chip 54AC273 are Q0、Q1、Q2、Q3(ii) a Wherein, an output pin Q0And an input pin INA1, and an output pin Q1And an input pin INB1, and an output pin Q2And an input pin INC1, an output pin Q3A 750 Ω resistor (R74, R76, R78, R80 in fig. 3) is connected in series with the input pin IND 1.
Based on the above description of the circuit structure, the following detailed analysis is made to illustrate the key points in the present embodiment:
selection of latch chip and relay driving chip
Table 1 is a truth table for the AC273 latch chip 54, with the output signal held low when the RESET signal is low; latch input D on rising edge of CLK signal when RESET signal is highnSignal to output QnAnd (4) an end. When the RESET is connected with the RC circuit, the low level is firstly set when the power-on is realized, and the high level is set after the capacitor charging (the latch chip 74AC273 is consistent with the latch chip 54AC273), so that the latch chip 54AC273 or the latch chip 74AC273 is enabled when the power-on is realized273 output is low, which will not cause the malfunction of the subsequent relay, and the charging is set to high level, which can make 54AC273 or 74AC273 output generate high level or low level required by the system under the action of CLOCK signal, and drive or not drive.
TABLE 1 truth table for latch chip 54AC273 or latch chip 74AC273
[ note ]: l represents a low level, H represents a high level, X represents an arbitrary state, ≈
Since the latch chip 54HC573 latches the signal at the falling edge of the input LE signal, and the latch chip 54AC273 or the latch chip 74AC273 latches the signal at the rising edge of the input LE signal, the nor chip 54HC02 needs to be replaced with the or chip 54HC32 when the latch chip 54AC273 is used, and similarly, the nor chip 54HC02 needs to be replaced with the or chip 74HC32 when the latch chip 74AC273 is used.
The principle of the relay driving chip LB8169 is shown IN fig. 4, the chip is a 4-path NPN type dual-redundancy decoding output driving circuit, each 1-path decoding circuit has two input control ends IN1 and IN2, and the driving circuit is turned on when IN1 and IN2 are both at high level. IN the hyperspectral camera controller, the IN1 and IN2 signals are combined and controlled by one output signal of the 54HC 573.
When an input signal of the relay driving chip LB8169 reaches 5V, the internal triode works in a saturation region and is in an on-off state, and the output driving capacity reaches 200 mA; if the input signal is lower than 5V, the internal triode works in an amplification region or a shallow saturation region, and the output driving capability is less than 200 mA.
The longest action time of the selected relay is 5ms, the resistance of the 3 paths of relays connected in parallel is 1.3k when the relay is actually used, and the maximum attracting current is 23 mA.
According to the actual measurement result, the relay driving chip LB8169 may be turned on when the signal of the input end is more than 1.3V. In order to avoid the malfunction of the relay caused by the conduction of the relay driving chip LB8169 when the latch chip 54AC273 outputs an indeterminate state (which may be a high level and is consistent with the chip power supply voltage) before the RESET circuit inside the chip 54AC273 operates during power-on. Before a ground resistor is divided between the output end of the latch chip 54AC273 and the input end of the relay driving chip LB8169 to ensure that the RESET initial value setting function of the latch chip 54AC273 is effective during power-on, an input signal of the relay driving chip LB8169 is lower than a conduction voltage, and no misoperation is generated.
In the power-on process of the latch chip 54AC273, after the power supply voltage VCC rises to a certain voltage, the internal logic starts to work, and before that, the RESET function of the clear terminal is not effective, and the output signal is the internal indeterminate logic. FIG. 5 shows the latch chip 54 with AC273VCC power supply terminals and Q0The voltage profile of the power-up process at the output terminal shows the latch chip 54AC273Q during power-up0The output terminal goes through the process of first rising to about 0.9V and then being set to 0 by the RESET signal RC. After a plurality of times, the voltage value of the output signal before zero clearing is not more than 0.9V.
Second, determination of voltage dividing resistance between latch chip and relay driving chip
Under the current working condition of the relay driving chip LB8169, the maximum V corresponding to the cut-off stateinValue and minimum V corresponding to saturationinThe value is obtained. These two voltage values are rated as 0.6V and 1.8V, taking into account the actual maximum operating conditions of the plant.
The principle of the resistor evaluation is that when the latch chip 54AC273 is powered on and outputs the maximum voltage of 0.9V, the divided voltage value of the resistor is not greater than 0.6V, and when the latch chip 54AC273 outputs the logic "1" in a steady state, the divided voltage value is not less than 1.8V, then the maximum load current (± 50mA) at the output end of the latch chip 54AC273 and the input current (100uA) at the input end of the relay driver chip LB8169 are considered, and the resistance values are 750 Ω and 510 Ω respectively. Thus, at the moment of power-on, the maximum voltage at the input end of the relay driver chip LB8169 is 0.36V, which ensures turn-off, and when the latch chip 54AC273 outputs logic "1" in a steady state, the voltage at the input end of the relay driver chip LB8169 is 1.367V, which ensures saturation, as shown in fig. 6.
The following are experimental verifications of the latch chip 54AC273 in the calibration and power control circuit provided in this implementation at several different stages of use:
first, output waveform verification during power-up of latch chip 54AC273
Latch chip 54AC273VCC power supply terminal and Q in this embodiment0The voltage curve of the output end in the power-on process is shown in fig. 5, after power-on, the output signal rises along with the power voltage, and after the RESET function is effective, the output signal is set to 0.
The waveform at B in FIG. 5 is the latch chip 54AC273 output signal pin waveform (Q)0Output terminal) of the relay driver chip LB8169, the maximum value of which is 0.9V, after voltage division by the subsequent circuit, the maximum voltage at the input terminal of the relay driver chip LB8169 is 0.36V, and the relay driver chip LB8169 is stably in a cut-off state according to an input characteristic curve.
Output waveform verification of latch chip 54AC273 during reset of second and lower computers
Fig. 7 shows the comparison result of the reset signal reset of the controller lower-level circuit mcu 80C32 and the output waveform of the latch chip 54AC 273. In fig. 7, the waveform at C is the lower circuit reset signal, the pulse width is 200ms (MAX813 generated), and the waveform at D is the output signal of the latch chip 54AC 273. As can be seen from the figure, the output signal of the latch chip 54AC273 is stable during the reset of the single chip microcomputer by the present embodiment, and no abnormal high level occurs; and after multiple tests, the result is stable.
Test verification during normal operation of the three-latch chip 54AC273
After power-on, when the controller CPU sends a relay switching instruction through the bus, the latch chip 54AC273 corresponding to the address latches data on the port at the upper edge of the write signal, and is driven by the subsequent relay driving chip LB8169, so that the relay performs a specified switching action.
Based on the experiment verification, the calibration power supply and control panel circuit provided in the implementation effectively solves the problem that the calibration and power supply control panel in the existing hyperspectral imager system controller has the power-on output unsteady state of the latch 54HC573 chip, so that the hyperspectral imager system is abnormally powered on.
Finally, it should be noted that the above description is only for the description of the preferred embodiments of the present invention, and not for any limitation on the scope of the present invention, and that any changes and modifications made by those skilled in the art according to the above disclosure are all within the scope of the appended claims.
Claims (4)
1. A calibration and power control circuit capable of eliminating power-on risk,
the circuit comprises 3 power chips, a latch chip, a relay driving chip and two relays;
the method is characterized in that: the MR pin of the latch chip is connected with an RC circuit; the CP pin of the latch chip is connected with the OR gate chip;
a750 ohm resistor is connected in series between each output pin of the latch chip and each input pin of the relay drive chip, and is connected with a 510 ohm resistor in a grounding mode.
2. The scaling and power control circuit capable of eliminating power-on risk according to claim 1, wherein: the latch chip model is 54AC273 or 74AC273, and the or gate chip model is 54HC32 or 74HC32, respectively.
3. The scaling and power control circuit capable of eliminating power-on risk according to claim 1, wherein: the model of the relay driving chip is LB 8169.
4. The scaling and power control circuit capable of eliminating power-on risk according to claim 1, wherein: the relay driving chip is provided with four input pins.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201921181263.1U CN210119692U (en) | 2019-07-25 | 2019-07-25 | Calibration and power supply control circuit capable of eliminating power-on risk |
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| CN201921181263.1U CN210119692U (en) | 2019-07-25 | 2019-07-25 | Calibration and power supply control circuit capable of eliminating power-on risk |
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| CN210119692U true CN210119692U (en) | 2020-02-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110389552A (en) * | 2019-07-25 | 2019-10-29 | 中国科学院西安光学精密机械研究所 | A kind of calibration that can eliminate risk and power control circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110389552A (en) * | 2019-07-25 | 2019-10-29 | 中国科学院西安光学精密机械研究所 | A kind of calibration that can eliminate risk and power control circuit |
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