CN217238764U - A CPU and FPGA automatic control startup circuit - Google Patents

Abstract

The utility model belongs to the field of smart grid control, in particular to a CPU and FPGA automatic control startup circuit. The utility model comprises a power supply system, a logic gate module, a control switch module, a CPU system and an FPGA system. The output signal of the logic gate is used to control the opening and closing of the control switch module, thereby realizing the power-off or power-on of the control CPU system. When the power supply system is turned on, when the FPGA system is powered on to complete the configuration, the signal output from the logic gate module controls the power-on of the CPU system to realize the self-starting of the CPU system. The utility model does not need to use hardware delay to realize, and does not need to modify the delay time of the hardware, No matter how long the FPGA system is configured, only after the FPGA system configuration is completed, the control switch module is powered on through the logic gate module, thus removing the time limit of hardware delay and improving the adaptability of the FPGA system and the CPU system when they work together. .

Description

A CPU and FPGA automatic control startup circuit

technical field

The utility model belongs to the field of smart grid control, in particular to a CPU and FPGA automatic control startup circuit.

Background technique

With the rapid development of digitization and intelligence in my country's smart grid, a large number of smart devices used in smart grids require powerful data processing capabilities and low-latency mass data communication capabilities. Therefore, the designed and manufactured smart devices often require CPU PCIE interfaces and FPGA for high-speed data exchange.

In a system where the CPU and FPGA work together, especially in a system where PCI/PCIE bus communication is used between the two, the FPGA needs to be loaded and configured with its PCI/PCIE function before the CPU enters the BIOS, otherwise the CPU will be initialized in the hardware. failed. With the increasing demand for smart grid functions, the FPGA configuration program is getting larger and larger, resulting in a long configuration time (more than 100ms), and the PCIE slave device has not been configured when the CPU is started, which causes the CPU to fail to recognize it correctly and causes the entire system to fail to initialize.

At present, in a system where the CPU and FPGA work together, usually after the system power is started normally, the hardware delays a certain period of time, so that the FPGA first completes the configuration process, thereby ensuring the normal startup of the CPU. Although this method enables the system to be initialized normally, the hardware delay time is fixed and cannot be easily modified.

SUMMARY OF THE INVENTION

In order to solve the above-mentioned problems, the utility model provides a CPU and FPGA automatic control startup circuit, and the specific technical scheme is as follows:

A CPU and FPGA automatic control startup circuit, comprising a power supply system, a logic gate module, a control switch module, a CPU system, and an FPGA system; the output end of the power supply system is respectively connected with the input end of the logic gate module, the input end of the FPGA system, The input end of the control switch module is electrically connected; the output end of the FPGA system is electrically connected with the input end of the logic gate module; the input end of the logic gate module is connected with the input end of the control switch module; the control switch module The output terminal is electrically connected with the input terminal of the CPU system;

The power supply system is used to provide working power to the CPU system and the FPGA system;

The logic gate module is used to collect the output signals of the power supply system and the FPGA system respectively, and to process and output the control signal to the control switch module; the control switch module is used to control the switch to disconnect or disconnect according to the control signal output by the logic gate module closed, so as to realize the disconnection or normal connection between the power supply system and the CPU system.

Preferably, the logic gate module includes an AND gate.

Preferably, the control switch module includes a pull-down resistor R4, a transistor Q2, a pull-up resistor R3, and a PMOS transistor Q1; the output ends of the logic gate module are respectively connected to one end of the pull-down resistor R4 and the base of the transistor Q2; the The other end of the pull-down resistor R4 and the emitter of the triode Q2 are grounded respectively; the collector of the triode Q2 is respectively connected to the gate of the PMOS transistor Q1 and one end of the pull-up resistor R3; the other end of the pull-up resistor is respectively It is connected to the output terminal of the power supply system and the drain of the PMOS transistor Q1; the source of the PMOS transistor Q1 is connected to the power supply terminal of the CPU system.

Preferably, the transistor Q2 is an NPN transistor.

Preferably, the power supply system includes an AC-DC module and a voltage divider module; the input end of the AC-DC module is AC connected to the mains 220; the output end of the AC-DC module is respectively connected to the voltage divider module and the FPGA system. is connected with the input end of the control switch module; the output end of the voltage dividing module is connected with the input end of the logic gate module;

The AC-DC module is used to convert the alternating current of the mains 220 into 12V direct current; the voltage divider module is used to divide the voltage of the 12V direct current output by the AC-DC module, and output the divided signal to the logic gate module the input terminal.

Preferably, the voltage dividing module includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2; one end of the first voltage dividing resistor R1 is connected to the output end of the AC-DC module; the first voltage dividing resistor R1 is connected to the output end of the AC-DC module; The other end of the piezoresistor R1 is connected to one end of the second piezoresistor R2 and the input end of the logic gate module; the other end of the second piezoresistor R2 is grounded.

Preferably, the AC-DC module includes an XD308H chip.

The beneficial effects of the utility model are as follows: The utility model provides a CPU and FPGA automatic control startup circuit, which includes a power supply system, a logic gate module, a control switch module, a CPU system and an FPGA system. The output signal of the logic gate is used to control the opening and closing of the control switch module, thereby realizing the power-off or power-on of the control CPU system. When the power supply system is turned on, when the FPGA system is powered on to complete the configuration, the signal output by the logic gate module controls the power-on of the CPU system to realize the self-starting of the CPU system. The utility model does not need to adopt hardware delay to realize, and does not need to modify the delay time of the hardware, No matter how long the FPGA system is configured, only after the configuration of the FPGA system is completed, the control switch module is powered on through the logic gate module, thus removing the time limit of hardware delay and improving the adaptability of the FPGA system and the CPU system when they work together. . The utility model adopts the AND gate to realize, and the structure principle of the AND gate is simple and easy to realize. Only when the output signal after the configuration of the power supply system and the FPGA is a high-level signal, the power-on control signal is output, which is convenient to control whether the control switch is turned on.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings required for the description of the specific embodiments or the prior art. Similar elements or parts are generally identified by similar reference numerals throughout the drawings. In the drawings, each element or section is not necessarily drawn to actual scale.

Fig. 1 is the structural principle diagram of the present utility model;

Fig. 3 is the truth table of logic gate module;

FIG. 2 is a schematic diagram of the power supply system of the present invention.

Detailed ways

The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are part of the embodiments of the present utility model, not all of the embodiments. . Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

It is to be understood that, when used in this specification and the appended claims, the terms "comprising" and "comprising" indicate the presence of the described features, integers, steps, operations, elements and/or components, but do not exclude one or The presence or addition of a number of other features, integers, steps, operations, elements, components, and/or sets thereof.

It should also be understood that the terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly dictates otherwise.

It should also be further understood that, as used in this specification and the appended claims, the term "and/or" refers to any and all possible combinations of one or more of the associated listed items, and including these combination.

As shown in Figure 1, a specific embodiment of the present utility model provides a CPU and FPGA automatic control startup circuit, including a power supply system, a logic gate module, a control switch module, a CPU system, and an FPGA system;

The output end of the power supply system is respectively electrically connected with the input end of the logic gate module, the input end of the FPGA system, and the input end of the control switch module; the output end of the FPGA system is electrically connected with the input end of the logic gate module; The input end of the logic gate module is connected with the input end of the control switch module; the output end of the control switch module is electrically connected with the input end of the CPU system;

The power supply system is used to provide working power to the CPU system and the FPGA system;

The logic gate module is used to collect the output signals of the power supply system and the FPGA system respectively, and to process and output the control signal to the control switch module; the control switch module is used to control the switch to disconnect or disconnect according to the control signal output by the logic gate module closed, so as to realize the disconnection or normal connection between the power supply system and the CPU system.

The logic gate module includes an AND gate, and the truth table is shown in Figure 2.

The control switch module includes a pull-down resistor R4, a transistor Q2, a pull-up resistor R3, and a PMOS transistor Q1; the output end of the logic gate module is respectively connected with one end of the pull-down resistor R4 and the base of the transistor Q2; the other end of the pull-down resistor R4 is connected. One end and the emitter of the transistor Q2 are grounded respectively; the collector of the transistor Q2 is respectively connected to the gate of the PMOS transistor Q1 and one end of the pull-up resistor R3; the other end of the pull-up resistor is respectively connected to the output of the power supply system The terminal is connected to the drain of the PMOS transistor Q1; the source of the PMOS transistor Q1 is connected to the power supply terminal of the CPU system. The transistor Q2 is an NPN transistor.

As shown in FIG. 3 , the power supply system includes an AC-DC module and a voltage divider module; the input end of the AC-DC module is AC connected to the mains 220; the output end of the AC-DC module is respectively connected to the voltage divider module, the FPGA The system is connected with the input end of the control switch module; the output end of the voltage dividing module is connected with the input end of the logic gate module;

The AC-DC module is used to convert the alternating current of the mains 220 into 12V direct current; the voltage divider module is used to divide the voltage of the 12V direct current output by the AC-DC module, and output the divided signal to the logic gate module the input terminal.

The voltage dividing module includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2; one end of the first voltage dividing resistor R1 is connected to the output end of the AC-DC module; the first voltage dividing resistor R1 The other end of the second voltage dividing resistor R2 is connected to one end of the second voltage dividing resistor R2 and the input end of the logic gate module; the other end of the second voltage dividing resistor R2 is grounded. Specifically, the AC-DC module includes an XD308H chip.

The working principle of the utility model is as follows: the connection between the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is used as the output signal POW_GOOD1 of the power supply system, and the output POW_GOOD1 signal of the power supply system is connected to the input end of the logic gate module U1, and the output signal of the FPGA system is connected to the input end of the logic gate module U1. The output CONF_DONE signal is connected to the other input terminal of the logic gate module U1, and the output POW_GOOD2 signal of the logic gate module U1 is connected to the base of the transistor Q2 and one end of the pull-down resistor R4. The power signal VCC12 output by the power system is respectively connected to the input end of the FPGA system and the input end of the control switch module.

When the power system is not started, the power system has no normal output, the POW_GOOD1 signal output is low, and the entire system does not work.

When the power supply system starts normally, the power supply system provides the power supply signal VCC12 for the entire system, and the output signal POW_GOOD1 obtained through the first voltage dividing resistor R1 and the second voltage dividing resistor R2 is at a high level.

After the power system starts normally, when the FPGA system has not completed the system configuration, the signal POW_GOOD1 input by the power system to the logic gate module U1 is high level, and the signal CONF_DONE output by the FPGA system to the gate module U1 is low level, according to Figure 2 At this time, the signal POW_GOOD2 output by the logic gate module U1 is low level, and the signal POW_GOOD2 output by the logic gate module U1 cannot drive the normal conduction of the transistor Q2 when the signal POW_GOOD2 signal is low level, so it cannot drive the PMOS transistor Q1. Normal conduction, at this time, the control switch module is equivalent to disconnection and no power supply, the power supply system cannot supply power to the CPU system normally, and the CPU system cannot complete initialization.

When the power system starts normally and the FPGA system completes the system configuration, the signal POW_GOOD1 input by the power system to the logic gate module U1 and the signal CONF_DONE output by the FPGA system to the gate module U1 are both high levels. According to the truth table in Figure 2 , at this time, the signal POW_GOOD2 output by the logic gate module U1 is high level, when the signal POW_GOOD2 output by the logic gate module U1 is high level, it can drive the transistor Q2 to conduct, and the conduction of the transistor Q2 enables the PMOS tube to be turned on normally. When the control switch module is closed, the power supply system provides power for the CPU system, and the CPU starts to perform system power-on self-test (POST), scans all hardware devices, and completes the normal startup of the device.

In summary, the designed circuit can ensure that the FPGA system has been loaded and completed all configuration tasks before the CPU system starts normally, thus avoiding the failure of the CPU during hardware initialization, and there is no time limit, and the circuit can effectively adapt to The loading of FPGA systems of various scales ensures the normal startup of the CPU system and the FPGA system.

Those of ordinary skill in the art can realize that the units of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the interchangeability of hardware and software In the above description, the composition of each example has been described generally in terms of function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may implement the described functionality using different methods for each particular application, but such implementations should not be considered beyond the scope of the present invention.

In the embodiments provided in this application, it should be understood that the division of units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units may be combined into one unit, and one unit may be detached. Divided into multiple units, or some features can be ignored, etc.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present utility model, but not to limit them; although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that : it can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements to some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the various embodiments of the present utility model The scope of the technical solution should be covered by the scope of the claims and description of the present invention.

Claims (7)

1. a CPU and FPGA automatic control startup circuit, it is characterized in that: comprise power supply system, logic gate module, control switch module, CPU system, FPGA system; The output end of described power supply system is respectively with the input end of logic gate module, The input end of the FPGA system and the input end of the control switch module are electrically connected; the output end of the FPGA system is electrically connected with the input end of the logic gate module; the input end of the logic gate module is connected with the input end of the control switch module ; The output end of the control switch module is electrically connected with the input end of the CPU system; The power supply system is used to provide working power to the CPU system and the FPGA system; The logic gate module is used to collect the output signals of the power supply system and the FPGA system respectively, and to process and output the control signal to the control switch module; the control switch module is used to control the switch to disconnect or disconnect according to the control signal output by the logic gate module closed, so as to realize the disconnection or normal connection between the power supply system and the CPU system. 2 . The automatic control startup circuit of a CPU and FPGA according to claim 1 , wherein the logic gate module comprises an AND gate. 3 . 3. A CPU and FPGA automatic control startup circuit according to claim 1 or 2, wherein the control switch module comprises a pull-down resistor R4, a triode Q2, a pull-up resistor R3, and a PMOS tube Q1; the logic The output end of the gate module is respectively connected to one end of the pull-down resistor R4 and the base of the triode Q2; the other end of the pull-down resistor R4 and the emitter of the triode Q2 are grounded respectively; the collector of the triode Q2 is respectively connected to the PMOS The gate of the tube Q1 and one end of the pull-up resistor R3; the other end of the pull-up resistor is respectively connected to the output end of the power supply system and the drain of the PMOS tube Q1; the source of the PMOS tube Q1 is connected to the power supply of the CPU system end connection. 4 . The automatic control startup circuit of a CPU and FPGA according to claim 3 , wherein the transistor Q2 is an NPN transistor. 5 . 5. The automatic control startup circuit of a CPU and FPGA according to claim 1, wherein the power supply system comprises an AC-DC module and a voltage divider module; the input end of the AC-DC module is connected to the mains 220 AC connection; the output end of the AC-DC module is respectively connected with the input end of the voltage divider module, the FPGA system and the control switch module; the output end of the voltage divider module is connected with the input end of the logic gate module; The AC-DC module is used to convert the alternating current of the mains 220 into 12V direct current; the voltage divider module is used to divide the voltage of the 12V direct current output by the AC-DC module, and output the divided signal to the logic gate module the input terminal. 6. A CPU and FPGA automatic control startup circuit according to claim 5, characterized in that: the voltage dividing module comprises a first voltage dividing resistor R1 and a second voltage dividing resistor R2; the first voltage dividing resistor One end of R1 is connected to the output end of the AC-DC module; the other end of the first voltage dividing resistor R1 is connected to one end of the second voltage dividing resistor R2 and the input end of the logic gate module; the second voltage dividing resistor is connected to the input end of the logic gate module; The other end of resistor R2 is connected to ground. 7 . The CPU and FPGA automatic control startup circuit according to claim 5 , wherein the AC-DC module comprises an XD308H chip. 8 .

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