CN217238764U - CPU and FPGA automatic control starting circuit - Google Patents

CPU and FPGA automatic control starting circuit Download PDF

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Publication number
CN217238764U
CN217238764U CN202220074611.0U CN202220074611U CN217238764U CN 217238764 U CN217238764 U CN 217238764U CN 202220074611 U CN202220074611 U CN 202220074611U CN 217238764 U CN217238764 U CN 217238764U
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module
cpu
fpga
logic gate
power supply
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CN202220074611.0U
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周柯
王晓明
林翔宇
李肖博
宋益
习伟
李文伟
彭博雅
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Electric Power Research Institute of Guangxi Power Grid Co Ltd
Southern Power Grid Digital Grid Research Institute Co Ltd
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Electric Power Research Institute of Guangxi Power Grid Co Ltd
Southern Power Grid Digital Grid Research Institute Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The utility model belongs to smart power grids control field, concretely relates to CPU and FPGA automatic control starting circuit. The utility model discloses a electrical power generating system, logic gate module, control switch module, CPU system, FPGA system. The output signal of the logic gate is adopted to control the on and off of the control switch module, so as to control the power-off or power-on of the CPU system. Open electrical power generating system, when the configuration was accomplished to the electricity on the FPGA system, the signal of logic gate module output just controlled the circular telegram of CPU system and then realized the CPU system self-starting, the utility model discloses need not to adopt the hardware time delay to realize to the delay time of hardware need not to be modified, no matter how long time of FPGA system configuration, only just through the circular telegram of logic gate module control switch module after FPGA system configuration is accomplished, therefore removed the time limit of hardware time delay, improved the adaptability of FPGA system with the CPU system during collaborative work.

Description

CPU and FPGA automatic control starting circuit
Technical Field
The utility model belongs to smart power grids control field, concretely relates to CPU and FPGA automatic control starting circuit.
Background
With the high-speed development of digitization and intellectualization of the smart grid in China, a large number of smart devices applied to the smart grid need strong data processing capability and low-delay mass data communication capability, so that the designed and manufactured smart devices often need a PCIE interface of a CPU (Central processing element interface) and an FPGA (field programmable gate array) to perform high-speed data exchange.
In a system in which a CPU and an FPGA cooperatively operate, particularly, in a system in which PCI/PCIE bus communication is employed between the CPU and the FPGA, the FPGA is required to load and configure its PCI/PCIE function before the CPU enters the BIOS, or otherwise the CPU fails when hardware is initialized. With the increasing function requirements of the smart grid, the FPGA configuration program is larger and larger, which results in an excessively long configuration time (more than 100 ms), and a PCIE slave device is not configured yet when the CPU is started, which results in that the CPU cannot correctly identify, and the initialization of the entire system fails.
At present, in a system with a CPU and an FPGA working cooperatively, after a system power supply is normally started, the FPGA is allowed to preferentially complete a configuration process by delaying hardware for a certain time, so as to ensure normal start of the CPU. Although this method can initialize the system normally, the hardware delay time is fixed and is not easy to modify.
Disclosure of Invention
In order to solve the problem, the utility model provides a CPU and FPGA automatic control starting circuit, concrete technical scheme is as follows:
a CPU and FPGA automatic control starting circuit comprises a power supply system, a logic gate module, a control switch module, a CPU system and an FPGA system; the output end of the power supply system is electrically connected with the input end of the logic gate module, the input end of the FPGA system and the input end of the control switch module respectively; the output end of the FPGA system is electrically connected with the input end of the logic gate module; the input end of the logic gate module is connected with the input end of the control switch module; the output end of the control switch module is electrically connected with the input end of the CPU system;
the power supply system is used for providing working power supply for the CPU system and the FPGA system;
the logic gate module is used for respectively acquiring output signals of the power supply system and the FPGA system, processing the output signals and outputting control signals to the control switch module; the control switch module is used for controlling the switch to be switched on or switched off according to the control signal output by the logic gate module, so that the power supply system and the CPU system are disconnected or normally connected.
Preferably, the logic gate module comprises an and gate.
Preferably, the control switch module comprises a pull-down resistor R4, a triode Q2, a pull-up resistor R3 and a PMOS tube Q1; the output end of the logic gate module is respectively connected with one end of a pull-down resistor R4 and the base electrode of a triode Q2; the other end of the pull-down resistor R4 and the emitter of the triode Q2 are respectively grounded; the collector of the triode Q2 is respectively connected to the grid of the PMOS tube Q1 and one end of a pull-up resistor R3; the other end of the pull-up resistor is respectively connected with the output end of the power supply system and the drain electrode of the PMOS tube Q1; and the source electrode of the PMOS pipe Q1 is connected with the power supply end of the CPU system.
Preferably, the transistor Q2 is an NPN transistor.
Preferably, the power supply system comprises an AC-DC module and a voltage division module; the input end of the AC-DC module is in alternating current connection with a mains supply 220; the output end of the AC-DC module is respectively connected with the input ends of the voltage division module, the FPGA system and the control switch module; the output end of the voltage division module is connected with the input end of the logic gate module;
the AC-DC module is used for converting commercial power 220 alternating current into 12V direct current; the voltage division module is used for dividing the 12V direct current output by the AC-DC module and outputting the divided signal to the input end of the logic gate module.
Preferably, the voltage dividing module comprises a first voltage dividing resistor R1 and a second voltage dividing resistor R2; one end of the first voltage dividing resistor R1 is connected with the output end of the AC-DC module; the other end of the first voltage-dividing resistor R1 is connected with one end of a second voltage-dividing resistor R2 and the input end of the logic gate module; the other end of the second voltage-dividing resistor R2 is grounded.
Preferably, the AC-DC module includes an XD308H chip.
The utility model has the advantages that: the utility model provides a CPU and FPGA automatic control starting circuit, including electrical power generating system, logic gate module, control switch module, CPU system, FPGA system. The output signal of the logic gate is adopted to control the on and off of the control switch module, so as to control the power-off or power-on of the CPU system. Open electrical power generating system, when the configuration was accomplished to the electricity on the FPGA system, the signal of logic gate module output just controlled the circular telegram of CPU system and then realized the CPU system self-starting, the utility model discloses need not to adopt the hardware time delay to realize to the delay time of hardware need not to be modified, no matter how long time of FPGA system configuration, only just through the circular telegram of logic gate module control switch module after FPGA system configuration is accomplished, therefore removed the time limit of hardware time delay, improved the adaptability of FPGA system with the CPU system during collaborative work. The utility model discloses a AND gate realizes, and the AND gate structure principle is simple easily to be realized, only when electrical power generating system and FPGA configuration accomplish the signal of output just export the control signal of circular telegram when high level signal, makes things convenient for control switch whether to switch on.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 3 is a truth table for a logic gate module;
fig. 2 is a schematic diagram of the power supply system of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
As shown in fig. 1, a specific embodiment of the present invention provides an automatic control starting circuit for a CPU and an FPGA, which includes a power supply system, a logic gate module, a control switch module, a CPU system, and an FPGA system;
the output end of the power supply system is electrically connected with the input end of the logic gate module, the input end of the FPGA system and the input end of the control switch module respectively; the output end of the FPGA system is electrically connected with the input end of the logic gate module; the input end of the logic gate module is connected with the input end of the control switch module; the output end of the control switch module is electrically connected with the input end of the CPU system;
the power supply system is used for providing working power supply for the CPU system and the FPGA system;
the logic gate module is used for respectively acquiring output signals of the power supply system and the FPGA system, processing the output signals and outputting control signals to the control switch module; the control switch module is used for controlling the switch to be switched on or off according to the control signal output by the logic gate module, so that the power supply system and the CPU system are disconnected or normally connected.
The logic gate module comprises an AND gate, and the truth table is shown in FIG. 2.
The control switch module comprises a pull-down resistor R4, a triode Q2, a pull-up resistor R3 and a PMOS tube Q1; the output end of the logic gate module is respectively connected with one end of a pull-down resistor R4 and the base electrode of a triode Q2; the other end of the pull-down resistor R4 and the emitter of the triode Q2 are respectively grounded; the collector of the triode Q2 is respectively connected to the grid of a PMOS tube Q1 and one end of a pull-up resistor R3; the other end of the pull-up resistor is respectively connected with the output end of the power supply system and the drain electrode of the PMOS tube Q1; and the source electrode of the PMOS pipe Q1 is connected with the power supply end of the CPU system. The transistor Q2 is an NPN transistor.
As shown in fig. 3, the power supply system includes an AC-DC module, a voltage dividing module; the input end of the AC-DC module is in alternating current connection with a mains supply 220; the output end of the AC-DC module is respectively connected with the input ends of the voltage division module, the FPGA system and the control switch module; the output end of the voltage division module is connected with the input end of the logic gate module;
the AC-DC module is used for converting commercial power 220 alternating current into 12V direct current; the voltage division module is used for dividing the 12V direct current output by the AC-DC module and outputting the divided signal to the input end of the logic gate module.
The voltage dividing module comprises a first voltage dividing resistor R1 and a second voltage dividing resistor R2; one end of the first voltage dividing resistor R1 is connected with the output end of the AC-DC module; the other end of the first voltage-dividing resistor R1 is connected with one end of a second voltage-dividing resistor R2 and the input end of the logic gate module; the other end of the second voltage-dividing resistor R2 is grounded. Specifically, the AC-DC module includes an XD308H chip.
The utility model discloses a theory of operation does: the junction of the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 is used as an output signal POW _ GOOD1 of the power supply system, an output POW _ GOOD1 signal of the power supply system is connected to an input end of the logic gate module U1, an output CONF _ DONE signal of the FPGA system is connected to the other input end of the logic gate module U1, and an output POW _ GOOD2 signal of the logic gate module U1 is connected to the base of the transistor Q2 and one end of the pull-down resistor R4. And a power supply signal VCC12 output by the power supply system is respectively connected to the input end of the FPGA system and the input end of the control switch module.
When the power system is not started, the power system does not normally output, the POW _ GOOD1 signal is output as low level, and the whole system does not work.
When the power supply system is normally started, the power supply system provides a power supply signal VCC12 for the whole system, and an output signal POW _ GOOD1 obtained through the first voltage-dividing resistor R1 and the second voltage-dividing resistor R2 is at a high level.
When the power system is normally started and the FPGA system does not complete system configuration, a signal POW _ GOOD1 input by the power system to the logic gate module U1 is at a high level, a signal CONF _ DONE output by the FPGA system to the gate module U1 is at a low level, according to the truth table of fig. 2, at this time, the signal POW _ GOOD2 output by the logic gate module U1 is at a low level, the signal POW _ GOOD2 output by the logic gate module U1 cannot drive the normal conduction of the transistor Q2, that is, the PMOS transistor Q1 cannot be driven to be normally conducted, at this time, the control switch module is equivalent to turn off and not conduct power, the power system cannot normally supply power the CPU system, and the CPU system cannot complete initialization.
When the power system is normally started and the FPGA system completes system configuration, a signal POW _ GOOD1 input by the power system to the logic gate module U1 and a signal CONF _ DONE output by the FPGA system to the gate editing module U1 are both high levels, according to the truth table of fig. 2, at this time, a signal POW _ GOOD2 output by the logic gate module U1 is high level, a signal POW _ GOOD2 output by the logic gate module U1 is high level, the transistor Q2 can be driven to conduct, the transistor Q2 is conducted so that the PMOS transistor can also conduct normally, at this time, the switch module is controlled to be closed, the power system provides power for the CPU system, and the CPU starts system power-on self-test (POST) to scan all hardware devices, thereby completing normal start of the devices.
In summary, the design circuit can ensure that the FPGA system has loaded and completed all configuration tasks before the CPU system is normally started, thereby avoiding the failure of the CPU in hardware initialization, having no time limit, and the circuit can effectively adapt to the loading of the FPGA systems of various scales, and ensuring the normal starting of the CPU system and the FPGA system.
Those of ordinary skill in the art will appreciate that the elements of the examples described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components of the examples have been described above generally in terms of their functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present application, it should be understood that the division of a unit is only one logical function division, and in actual implementation, there may be another division manner, for example, multiple units may be combined into one unit, one unit may be split into multiple units, or some features may be omitted.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the scope of the embodiments of the present invention, and are intended to be covered by the claims and the specification.

Claims (7)

1. The utility model provides a CPU and FPGA automatic control start circuit which characterized in that: the intelligent control system comprises a power supply system, a logic gate module, a control switch module, a CPU system and an FPGA system; the output end of the power supply system is electrically connected with the input end of the logic gate module, the input end of the FPGA system and the input end of the control switch module respectively; the output end of the FPGA system is electrically connected with the input end of the logic gate module; the input end of the logic gate module is connected with the input end of the control switch module; the output end of the control switch module is electrically connected with the input end of the CPU system;
the power supply system is used for providing working power supply for the CPU system and the FPGA system;
the logic gate module is used for respectively acquiring output signals of the power supply system and the FPGA system, processing the output signals and outputting control signals to the control switch module; the control switch module is used for controlling the switch to be switched on or off according to the control signal output by the logic gate module, so that the power supply system and the CPU system are disconnected or normally connected.
2. The CPU and FPGA automatic control starting circuit according to claim 1, characterized in that: the logic gate module comprises an AND gate.
3. The CPU and FPGA automatic control starting circuit according to claim 1 or 2, characterized in that: the control switch module comprises a pull-down resistor R4, a triode Q2, a pull-up resistor R3 and a PMOS tube Q1; the output end of the logic gate module is respectively connected with one end of a pull-down resistor R4 and the base electrode of a triode Q2; the other end of the pull-down resistor R4 and the emitter of the triode Q2 are respectively grounded; the collector of the triode Q2 is respectively connected to the grid of a PMOS tube Q1 and one end of a pull-up resistor R3; the other end of the pull-up resistor is respectively connected with the output end of the power supply system and the drain electrode of the PMOS tube Q1; and the source electrode of the PMOS pipe Q1 is connected with the power supply end of the CPU system.
4. The CPU and FPGA automatic control starting circuit according to claim 3, characterized in that: the transistor Q2 is an NPN transistor.
5. The CPU and FPGA automatic control starting circuit according to claim 1, characterized in that: the power supply system comprises an AC-DC module and a voltage division module; the input end of the AC-DC module is in alternating current connection with a mains supply 220; the output end of the AC-DC module is respectively connected with the input ends of the voltage division module, the FPGA system and the control switch module; the output end of the voltage division module is connected with the input end of the logic gate module;
the AC-DC module is used for converting commercial power 220 alternating current into 12V direct current; the voltage division module is used for dividing the 12V direct current output by the AC-DC module and outputting the divided signal to the input end of the logic gate module.
6. The CPU and FPGA automatic control starting circuit according to claim 5, characterized in that: the voltage division module comprises a first voltage division resistor R1 and a second voltage division resistor R2; one end of the first voltage dividing resistor R1 is connected with the output end of the AC-DC module; the other end of the first voltage-dividing resistor R1 is connected with one end of a second voltage-dividing resistor R2 and the input end of the logic gate module; the other end of the second voltage-dividing resistor R2 is grounded.
7. The CPU and FPGA automatic control starting circuit according to claim 5, wherein: the AC-DC module includes an XD308H chip.
CN202220074611.0U 2022-01-12 2022-01-12 CPU and FPGA automatic control starting circuit Active CN217238764U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202220074611.0U CN217238764U (en) 2022-01-12 2022-01-12 CPU and FPGA automatic control starting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202220074611.0U CN217238764U (en) 2022-01-12 2022-01-12 CPU and FPGA automatic control starting circuit

Publications (1)

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CN217238764U true CN217238764U (en) 2022-08-19

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