CN209979798U

CN209979798U - Test fixture

Info

Publication number: CN209979798U
Application number: CN201920739598.4U
Authority: CN
Inventors: 陈浩铭
Original assignee: Shenzhen Mipi Technology Co Ltd
Current assignee: Shenzhen Mipi Technology Co Ltd
Priority date: 2019-05-21
Filing date: 2019-05-21
Publication date: 2020-01-21
Anticipated expiration: 2029-05-21

Abstract

The utility model discloses a test fixture relates to circuit board detection technology field, including PCB mainboard (1) and connector (2), its characterized in that: be equipped with chip connection district (11) and connector connection district (12) on PCB mainboard (1), connector connection district (12) include that a plurality of connects subregion (121), connect the pad of subregion (121) with the pad of chip connection district (11) corresponds electric connection, connector (2) with connect the corresponding fixed connection of subregion (121). The utility model has the characteristics of easy operation, with low costs and strong adaptability etc, use a test socket compatible polytypic chip simultaneously, greatly reduced purchase test socket's cost and measuring accuracy height, connect subregion department and all be equipped with wiring differentiation mark, distinguish the wiring during convenient test.

Description

Test fixture

Technical Field

The utility model relates to a circuit board detects technical field, in particular to test fixture.

Background

In the chip burning and testing process, as BGA memory chips have a plurality of packaging types, test sockets with different packages need to be purchased, and output interfaces of programmers (burners) of different manufacturers are different, so that the unified standard is not available. For example, the EMMC stores BGAs divided into 0.5MM pitches, which include BGAs 162 to 186, B153 to 169, 221, 136, 168, 254, 529, (BGA 1000.5 × 2 is 1.0MM pitch). The 0.5MM pitch UFS memory chip has BGA153BGA254 because BGA pin definitions are different for different packages. The user would need to purchase 10 different models of test sockets. The design can be compatible with various types of chips by using only one test seat. Greatly reducing the cost of purchasing the test socket.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the problem and providing a test fixture.

In order to solve the above problem, the utility model provides a technical scheme: the utility model provides a test fixture, includes PCB mainboard and connector, its characterized in that: the PCB is characterized in that a chip connection area and a connector connection area are arranged on the PCB main board, the connector connection area comprises a plurality of connection partitions, pads of the connection partitions are electrically connected with corresponding pads of the chip connection area, and the connector is fixedly connected with the connection partitions correspondingly.

Preferably, the number of the connection partitions and the number of the connectors are both 8.

Preferably, the connection subareas are provided with wiring subarea marks.

Preferably, the connector connection area is disposed on the front or back surface of the PCB main board or on the side surface of the PCB main board.

Preferably, the connector is soldered to the connection section.

Preferably, the test fixture further comprises a chip test seat, the chip test seat is fixed on the chip connection area, and pins of the chip test seat are electrically connected with the bonding pads of the chip connection area correspondingly.

Preferably, the chip test socket is screwed on the PCB main board by screws.

Preferably, a chip is clamped on the chip test seat, pins of the chip test seat are correspondingly connected with pins of the chip, and the chip test seat is provided with a positioning mark matched with the initial pin point of the chip.

Preferably, the pitch of pins of the connector is equal to the pitch of pins of the chip connection region.

The utility model has the advantages that: the utility model has the characteristics of easy operation, with low costs and strong adaptability etc, use a test socket compatible polytypic chip simultaneously, greatly reduced purchase test socket's cost and measuring accuracy height, connect subregion department and all be equipped with wiring differentiation mark, distinguish the wiring during convenient test.

Drawings

For ease of illustration, the invention is described in detail by the following detailed description and accompanying drawings.

Fig. 1 is a schematic structural diagram of the present invention.

Fig. 2 is a schematic diagram of the PCB main board of the present invention.

1-a PCB mainboard; 11-a die attach region; 12-a connector connection region; 121-linking partitions; 2-a connector; 3-chip test seat; 4-a screw; 5-chip.

Detailed Description

As shown in fig. 1 to fig. 2, the specific embodiment of the present invention adopts the following technical solutions: the utility model provides a test fixture, includes PCB mainboard 1 and connector 2, its characterized in that: the PCB is characterized in that a chip connection area 11 and a connector connection area 12 are arranged on the PCB main board 1, the connector connection area 12 comprises a plurality of connection partitions 121, bonding pads of the connection partitions 121 are electrically connected with bonding pads of the chip connection area 11 correspondingly, and the connector 2 is fixedly connected with the connection partitions 121 correspondingly.

Wherein the number of the connection partitions 121 and the number of the connectors 2 are 8.

Wherein, the connection subareas 121 are provided with wiring subarea marks.

The connector connection area 12 is disposed on the front side or the back side of the PCB main board 1 or on the side of the PCB main board 1.

Wherein the connector 2 is soldered to the connection section 121.

The test fixture further comprises a chip test seat 3, the chip test seat 3 is fixed on the chip connection area 11, and pins of the chip test seat 3 are electrically connected with bonding pads of the chip connection area 11 correspondingly.

The chip testing seat 3 is screwed on the PCB mainboard 1 through a screw 4.

The chip testing seat 3 is connected with a chip 5 in a clamping manner, pins of the chip testing seat 3 are correspondingly connected with pins of the chip 5, and the chip testing seat 3 is provided with a positioning mark matched with an initial pin point of the chip 5.

Wherein the pin pitch of the connector 2 is equal to the pin pitch of the chip connection region 11.

The specific implementation mode is as follows: the design process comprises the following steps: 1. and manufacturing a PCB mainboard package of 8 BGA chips, positioning a positioning mark on the PCB mainboard to facilitate the alignment and positioning of the chips and the PCB mainboard, and deleting unnecessary pins according to the PDF chip datasheet to reserve at least 14 points which need to be defined, such as D0D 1D 2D 3D 4D 5D 6D 7 CLK CMD VCCVCCQ VDDI GND defined by EMMC interface standard. The UFS interface standard is defined as TXP0 TXN0 TXP1 TXN1 RXN0 RXP0 RXN1 RXP1 recilkrstout VDDIQ2VCCQ 2VCC GND.

2. An 8 connector package is designed and several connectors are required for several BGAs. The connector can be soldered on the back of the BGA, can be soldered on the four sides of the PCB mainboard, and can be positioned on the same side of the BGA.

3. And (3) according to the initial pin points of the BGA, completely overlapping the initial pin points of 8 or 10 packaged 0.5MM chips on the same PCB, leading out the corresponding definition groups of the BGA to the connectors respectively, leading out N connectors from N BGA, and connecting the connectors with the programmer through the adapter plate.

The type of the chip test seat 3 is 0.5mm interval, and the chip test seat 3 is screwed on the chip connection area of the PCB board through a screw 4.

8 kinds of test sockets need to be bought for original 8 kinds of BGA, only need a test socket can compatible 8 kinds of BGA, even more BGA through the PCB design now.

The present invention has been shown and described above the basic principle and the main features of the present invention and the advantages of the present invention, and it should be understood by those skilled in the art that the present invention is not limited by the above embodiments, and the description in the above embodiments and the description is only illustrative of the principles of the present invention, without departing from the spirit and scope of the present invention, the present invention can also have various changes and improvements, and these changes and improvements all fall into the scope of the present invention, which is defined by the appended claims and their equivalents.

Claims

1. The utility model provides a test fixture, includes PCB mainboard (1) and connector (2), its characterized in that: be equipped with chip connection district (11) and connector connection district (12) on PCB mainboard (1), connector connection district (12) include that a plurality of connects subregion (121), connect the pad of subregion (121) with the pad of chip connection district (11) corresponds electric connection, connector (2) with connect the corresponding fixed connection of subregion (121).

2. The testing fixture of claim 1, wherein: the number of the connection partitions (121) and the number of the connectors (2) are both 8.

3. The testing fixture of claim 2, wherein: and wiring distinguishing marks are arranged at the connecting subareas (121).

4. The testing fixture of claim 1, wherein: the connector connecting area (12) is arranged on the front surface or the back surface of the PCB mainboard (1) or on the side surface of the PCB mainboard (1).

5. The testing fixture of claim 1, wherein: the connector (2) is welded to the connection section (121).

6. The testing fixture of claim 1, wherein: the chip testing device is characterized by further comprising a chip testing seat (3), wherein the chip testing seat (3) is fixed on the chip connecting area (11), and pins of the chip testing seat (3) are electrically connected with bonding pads of the chip connecting area (11) correspondingly.

7. The testing fixture of claim 6, wherein: the chip testing seat (3) is connected to the PCB mainboard (1) in a screwing mode through screws (4).

8. The testing fixture of claim 7, wherein: the chip testing device is characterized in that a chip (5) is clamped on the chip testing seat (3), pins of the chip testing seat (3) are correspondingly connected with pins of the chip (5), and positioning marks matched with initial pin points of the chip (5) are arranged on the chip testing seat (3).

9. The testing fixture of claim 1, wherein: the pin pitch of the connector (2) is equal to the pin pitch of the chip connection region (11).