CN209912734U - Capacitor with a capacitor element - Google Patents
Capacitor with a capacitor element Download PDFInfo
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- CN209912734U CN209912734U CN201920737026.2U CN201920737026U CN209912734U CN 209912734 U CN209912734 U CN 209912734U CN 201920737026 U CN201920737026 U CN 201920737026U CN 209912734 U CN209912734 U CN 209912734U
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Abstract
The present application relates to a capacitor. The capacitor comprises a first electrode, a second electrode, a first outer insulating layer, a second outer insulating layer and a dielectric layer; the second electrode is arranged opposite to the first electrode; two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode; two sides of the second outer insulating layer are respectively connected with the other end of the first electrode and the other end of the second electrode; the first electrode, the first outer layer insulating layer, the second electrode and the second outer layer insulating layer jointly enclose an accommodating cavity; the dielectric layer is filled in the accommodating cavity and comprises a prepreg layer and two dielectric layer bodies. Each first integrated circuit layer is electrically connected with the first electrode, and each second integrated circuit layer is electrically connected with the second electrode, so that the first electrode and the second electrode have larger opposite areas, the problem that the capacitor is limited by the size of the integrated circuit under a certain volume condition is solved, and the capacitance value of the capacitor of the integrated circuit is larger.
Description
Technical Field
The present application relates to the field of circuit devices, and more particularly, to a capacitor.
Background
A capacitor is an electronic device having a layer of insulating material sandwiched between two electrodes, which are typically flat plates of different shapes, profiles and sizes. When a voltage difference exists between the two electrodes, an electric field is generated between the two electrodes to enable the capacitor to store electrical energy. When a given voltage is applied across the two electrodes, the energy stored in the capacitor is referred to as its capacitance. The capacitance value is generally related to the dielectric constant k of the dielectric layer of an electrode and is proportional to the area of the opposing electrode and inversely proportional to the distance between the electrodes.
If two or more capacitors are connected in parallel, the total capacitance value after parallel connection is the sum of the capacitance values of all the capacitors. If two or more capacitors are connected in series, the overall capacitance after series connection is less than the capacitance of any one capacitor. When capacitors in series are used for high voltages, the capacitors in series divide the high voltage. For the conventional capacitor, the capacitance value of the capacitor of the integrated circuit is small due to the limitation of the size of the integrated circuit.
SUMMERY OF THE UTILITY MODEL
In view of this, it is necessary to provide a capacitor for solving the problem of a small capacitance value of a capacitor of an integrated circuit.
A capacitor, comprising:
a first electrode;
a second electrode disposed opposite the first electrode;
the two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode;
two sides of the second outer insulating layer are respectively connected with the other end of the first electrode and the other end of the second electrode; the first electrode, the first outer insulating layer, the second electrode and the second outer insulating layer jointly enclose a containing cavity;
the dielectric layer is filled in the accommodating cavity and comprises a prepreg layer and two dielectric layer bodies, the two dielectric layer bodies are respectively positioned on two sides of the prepreg layer, one side of any one of the dielectric layer bodies, which is adjacent to the prepreg layer, is provided with a plurality of first integrated circuit layers and a plurality of second integrated circuit layers, the first integrated circuit layers and the second integrated circuit layers are mutually spaced, the two first integrated circuit layers, which are respectively positioned on different dielectric layer bodies, in the cross section direction perpendicular to the extension direction of the first outer insulating layer are oppositely arranged, each first integrated circuit layer and each second integrated circuit layer are in a bent shape, each first integrated circuit layer is electrically connected with the first electrode, and each second integrated circuit layer is electrically connected with the second electrode.
In one embodiment, the first integrated circuit layer and the second integrated circuit layer are stacked and do not contact with each other, so that the capacitor has a compact structure and a large capacitance.
In one embodiment, the first integrated circuit layer and the second integrated circuit layer are S-shaped.
In one embodiment, the first integrated circuit layers and the second integrated circuit layers which are positioned on the same dielectric layer body are arranged at intervals, so that the electricity storage performance of the capacitor is further improved.
In one embodiment, the first integrated circuit layer and the second integrated circuit layer which are adjacent to the same dielectric layer body are arranged in a staggered mode, so that the area of the integrated circuit layers in the capacitor is increased, and the electricity storage performance of the capacitor is improved.
In one embodiment, two first integrated circuit layers respectively located on different dielectric layer bodies along a cross section direction perpendicular to the extending direction of the first outer insulating layer are oppositely arranged.
In one embodiment, the first integrated circuit layers on the two sides of the prepreg layer are conducted through the via holes of the prepreg layer, so that the first integrated circuit layers on the two sides of the prepreg layer are conducted.
In one embodiment, the second integrated circuit layers on the two sides of the prepreg layer are conducted through the via holes of the prepreg layer, so that the second integrated circuit layers on the two sides of the prepreg layer are conducted.
In one embodiment, the line width precision of any line of the first integrated circuit layer is ± 0.02mm, so that the line width of the first integrated circuit layer is relatively uniform, and the first integrated circuit layer is ensured to have better power storage performance.
In one embodiment, the line width precision of any line of the second integrated circuit layer is +/-0.02 mm, so that the line width of the second integrated circuit layer is relatively uniform, and the second integrated circuit layer is ensured to have relatively good power storage performance.
In one embodiment, the first electrode includes a first electrode base layer and a first cover layer, the first cover layer covers the first electrode base layer, two ends of the first cover layer are respectively connected with the first outer insulating layer and the second outer insulating layer, and each of the first integrated circuit layers is connected with the first electrode base layer, so that any one of the first integrated circuit layers is electrically connected with the first electrode.
In one embodiment, the second electrode includes a second electrode base layer and a second cover layer, the second cover layer covers the second electrode base layer, two ends of the second cover layer are respectively connected to the first outer insulating layer and the second outer insulating layer, and each of the second integrated circuit layers is connected to the second electrode base layer, so that any one of the second integrated circuit layers is electrically connected to the second electrode.
In the capacitor, the first electrode and the second electrode are oppositely arranged, and two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode, so that the first outer insulating layer separates and insulates one end of the first electrode from one end of the second electrode; similarly, the second outer insulating layer separates and insulates the other end of the first electrode from the other end of the second electrode; thus, the first outer insulating layer and the second outer insulating layer jointly separate the first electrode and the second electrode; because the dielectric layer is filled in a containing cavity which is defined by the first electrode, the first outer insulating layer, the second electrode and the second outer insulating layer together, and the dielectric layer comprises the prepreg layer and two dielectric layer bodies which are respectively positioned at two sides of the prepreg layer, one side of any one dielectric layer body adjacent to the prepreg layer is provided with a plurality of first integrated circuit layers and a plurality of second integrated circuit layers, and two first integrated circuit layers which are respectively positioned at different dielectric layer bodies along the cross section direction which is vertical to the extending direction of the first outer insulating layer are arranged oppositely, the capacitor can better store energy, and because each first integrated circuit layer and each second integrated circuit layer are bent, each first integrated circuit layer and each second integrated circuit layer have larger areas, and each first integrated circuit layer is electrically connected with the first electrode, each second integrated circuit layer is electrically connected with the second electrode, so that the first electrode and the second electrode have larger opposite areas, the problem that the capacitor is limited by the size of the integrated circuit under a certain volume condition is solved, and the capacitance value of the capacitor of the integrated circuit is larger.
Drawings
FIG. 1 is a schematic diagram of a capacitor according to an embodiment;
FIG. 2 is a cross-sectional view of the capacitor shown in FIG. 1;
FIG. 3 is a schematic diagram of a first integrated circuit layer and a second integrated circuit layer of any dielectric layer body of the capacitor of FIG. 1;
FIG. 4 is a cross-sectional view of a first capping layer of a first electrode of the capacitor shown in FIG. 1;
fig. 5 is a cross-sectional view of a second capping layer of a second electrode of the capacitor shown in fig. 1.
Detailed Description
To facilitate an understanding of the present application, the capacitor will be described more fully below with reference to the associated drawings. Preferred embodiments of the capacitor are shown in the drawings. However, the capacitor may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only and do not represent the only embodiments.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the capacitors herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In one embodiment, a capacitor includes a first electrode, a second electrode, a first outer insulating layer, a second outer insulating layer, and a dielectric layer; the second electrode is arranged opposite to the first electrode; two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode; two sides of the second outer insulating layer are respectively connected with the other end of the first electrode and the other end of the second electrode; the first electrode, the first outer insulating layer, the second electrode and the second outer insulating layer jointly enclose a containing cavity; the dielectric layer is filled in the accommodating cavity and comprises a prepreg layer and two dielectric layer bodies, the two dielectric layer bodies are respectively positioned at two sides of the prepreg layer, one side of any one of the dielectric layer bodies, which is adjacent to the prepreg layer, is provided with a plurality of first integrated circuit layers and a plurality of second integrated circuit layers, each first integrated circuit layer and each second integrated circuit layer are mutually spaced, the two first integrated circuit layers which are respectively positioned on different dielectric layer bodies in the cross section direction perpendicular to the extension direction of the first outer insulating layer are oppositely arranged, each first integrated circuit layer and each second integrated circuit layer are in a bent shape, each first integrated circuit layer is electrically connected with the first electrode, and each second integrated circuit layer is electrically connected with the second electrode.
As shown in fig. 1, a capacitor 10 according to an embodiment includes a first electrode 100, a second electrode 200, a first outer insulating layer 300, a second outer insulating layer 400, and a dielectric layer 500. The second electrode is disposed opposite the first electrode. And two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode. And two sides of the second outer insulating layer are respectively connected with the other end of the first electrode and the other end of the second electrode. Referring also to fig. 2, the first electrode, the first outer insulating layer, the second electrode and the second outer insulating layer together enclose a receiving cavity 10 a.
In one embodiment, as shown in fig. 2, the dielectric layer is filled in the accommodating cavity. The dielectric layer 500 includes a prepreg layer 510 and two dielectric layer bodies 520, which are respectively located at two sides of the prepreg layer. The two dielectric layer bodies are a first dielectric layer body 520A and a second dielectric layer body 520B, respectively. The first dielectric layer body, the prepreg layer and the second dielectric layer body are arranged in a stacked mode to form a dielectric layer. Because the dielectric layer is of a multilayer structure, the capacitor has better electrical storage performance under the condition that the volume of the accommodating cavity is certain.
As shown in fig. 2 and fig. 3, in one embodiment, at least one first integrated circuit layer 522 and at least one second integrated circuit layer 524 are disposed on one side of any one of the dielectric layer bodies 520 adjacent to the prepreg layer 510. In this embodiment, a plurality of the first integrated circuit layers and a plurality of the second integrated circuit layers are disposed on one side of any one of the dielectric layer bodies, which is adjacent to the prepreg layer. Each of the first integrated circuit layers and each of the second integrated circuit layers are spaced apart from each other. Each first integrated circuit layer and each second integrated circuit layer are bent, so that each first integrated circuit layer and each second integrated circuit layer have larger areas. Each of the first integrated circuit layers is electrically connected to the first electrode. Each of the second integrated circuit layers is electrically connected to the second electrode. Like this, in the holding intracavity of certain volume, the dead area between first electrode and the second electrode is great, makes the accumulate performance of capacitor more stable, even the capacitance value of capacitor is bigger.
In one embodiment, as shown in fig. 2, two first integrated circuit layers, which are respectively located on different dielectric layer bodies, in a cross-sectional direction perpendicular to the extending direction of the first outer insulating layer are arranged opposite to each other, so that the capacitor can better store energy. In the present embodiment, the cross-sectional direction is perpendicular to both the extending directions of the first and second outer insulating layers. In one embodiment, two second integrated circuit layers respectively located on different dielectric layer bodies in a cross-sectional direction perpendicular to the extending direction of the first outer insulating layer are oppositely arranged so that the capacitor can better store energy. In one embodiment, the first integrated circuit layer and the second integrated circuit layer are both S-shaped, so that the first integrated circuit layer and the second integrated circuit layer are large in area and easy to manufacture.
In order to make the capacitor have a compact structure and a large capacitance, in one embodiment, the first integrated circuit layer and the second integrated circuit layer are stacked and do not contact with each other, that is, a plane in which the extending direction of the first integrated circuit layer is located and a plane in which the extending direction of the second integrated circuit layer is located are parallel to each other, so that the capacitor has a compact structure and a large capacitance.
In one embodiment, a plurality of the first integrated circuit layers and a plurality of the second integrated circuit layers are disposed on one side of any one of the dielectric layer bodies, which is adjacent to the prepreg layer, that is, the number of the first integrated circuit layers and the number of the second integrated circuit layers which are disposed on the same dielectric layer body are both multiple. The first integrated circuit layers and the second integrated circuit layers which are positioned on the same dielectric layer body are arranged at intervals, so that the electricity storage performance of the capacitor is further improved. In this embodiment, a plurality of first integrated circuit layers and a plurality of second integrated circuit layers are disposed on one side of each dielectric layer body adjacent to the prepreg layer, and the plurality of first integrated circuit layers and the plurality of second integrated circuit layers located on the same dielectric layer body are distributed at intervals, that is, two adjacent first integrated circuit layers located on the same dielectric layer body are separated by one second integrated circuit layer. In order to further improve the electricity storage performance of the capacitor, in one embodiment, the distance between any adjacent first integrated circuit layer and the second integrated circuit layer is equal, so that the capacitor has better electricity storage performance.
As shown in fig. 3, in one embodiment, the first integrated circuit layer 522 and the second integrated circuit layer 524 adjacent to the same dielectric body are partially staggered, that is, the portion of any first integrated circuit layer and the portion of any second integrated circuit layer in the same dielectric body do not correspond to each other, so that the area of the integrated circuit layers in the capacitor is increased, and the power storage performance of the capacitor is further improved.
As shown in fig. 2, in order to conduct the first integrated circuit layers on both sides of the prepreg layer, in one embodiment, the first integrated circuit layers on both sides of the prepreg layer are conducted through the via 512 of the prepreg layer 510, so that the first integrated circuit layers on both sides of the prepreg layer are conducted.
In order to enable the second integrated circuit layers on the two sides of the prepreg layer to be conducted, in one embodiment, the second integrated circuit layers on the two sides of the prepreg layer are conducted through the via holes of the prepreg layer, so that the second integrated circuit layers on the two sides of the prepreg layer are conducted.
In one embodiment, the line width precision of any line of the first integrated circuit layer is +/-0.02 mm, so that the line width deviation of the first integrated circuit layer is small, even if the line width of the first integrated circuit layer is uniform, and the first integrated circuit layer is ensured to have better power storage performance. In one embodiment, the line width precision of any line of the second integrated circuit layer is ± 0.02mm, so that the line width deviation of the second integrated circuit layer is small, even if the line width of the second integrated circuit layer is relatively uniform, and the difference between the line width precision of the line of the second integrated circuit layer and the line width precision of the first integrated circuit layer is small, thereby ensuring that the second integrated circuit layer has better power storage performance. In one embodiment, the range of the surface copper thickness of any first integrated circuit layer is less than or equal to 3 μm, so that the surface copper thickness deviation of the first integrated circuit layer is small, and the overall structure is smooth. In one embodiment, the range of the surface copper thickness of any second integrated circuit layer is less than or equal to 3 μm, so that the surface copper thickness deviation of the second integrated circuit layer is small, and the overall structure is smooth.
As shown in fig. 1, in one embodiment, the first electrode 100 includes a first electrode base layer 110 and a first cover layer 120. The first covering layer covers the first electrode base layer, namely the first covering layer is positioned on the outer side of the first electrode base layer. And two ends of the first covering layer are respectively connected with the first outer layer insulating layer and the second outer layer insulating layer. Each first integrated circuit layer is connected with the first electrode base layer, so that any first integrated circuit layer is electrically connected with the first electrode. In this embodiment, the first electrode base layer is a copper layer. In one embodiment, the first covering layer comprises at least one of a nickel-gold layer, a nickel-palladium-gold layer or a nickel-silver layer, so that the first electrode has better conductivity.
As shown in fig. 1, in one embodiment, the second electrode 200 includes a second electrode base layer 210 and a second cover layer 220, the second cover layer covers the second electrode base layer, two ends of the second cover layer are respectively connected to the first outer insulating layer and the second outer insulating layer, and each of the second integrated circuit layers is connected to the second electrode base layer, so that any one of the second integrated circuit layers is electrically connected to the second electrode. In this embodiment, the second electrode base layer is a copper layer. In one embodiment, the second covering layer comprises at least one of a nickel-gold layer, a nickel-palladium-gold layer or a nickel-silver layer, so that the second electrode has better conductivity.
In one embodiment, the first covering layer covers the first electrode base layer, and the first covering layer is separated from the first electrode base layer and the first outer insulating layer respectively, so that the first outer insulating layer is prevented from entering between the first electrode base layer and the dielectric layer to influence the connection strength of the first electrode base layer and the dielectric layer. In one embodiment, the first cover layer and the first electrode base layer are bent. As shown in fig. 4, in the present embodiment, the first cover layer 120 includes a first top portion 122, a first vertical surface portion 124, and a first bottom portion 126, which are connected in this order, and are symmetrically disposed with respect to the first vertical surface portion. In one embodiment, the roughness of the first vertical surface portion is less than or equal to 3.5 μm, making the first vertical surface portion smoother. In one embodiment, the roughness of the first top portion, the first vertical face portion and the first bottom portion is less than or equal to 3 μm, so that the first cover layer is in good contact with the first electrode base layer. In one embodiment, the roughness of the dielectric layer in contact with the first electrode base layer is less than or equal to 10 μm, allowing for better contact connection of the first electrode base layer with the dielectric layer.
In one embodiment, the second covering layer covers the second electrode base layer, and the second covering layer is separated from the second electrode base layer and the second outer insulating layer respectively, so that the second outer insulating layer is prevented from entering between the second electrode base layer and the dielectric layer to influence the connection strength of the second electrode base layer and the dielectric layer. In one embodiment, the second cover layer and the second electrode base layer are bent. As shown in fig. 5, in the present embodiment, the second cover layer 220 includes a second top portion 222, a second vertical surface portion 224, and a second bottom portion 226, which are connected in this order, and are symmetrically disposed with respect to the second vertical surface portion. In one embodiment, the roughness of the second vertical surface portion is less than or equal to 3.5 μm, making the second vertical surface portion smoother. In one embodiment, the roughness of the second top portion, the second vertical face portion and the second bottom portion is less than or equal to 3 μm, so that the second cover layer is in good contact with the second electrode base layer. In one embodiment, the roughness of the dielectric layer with the second electrode base layer is less than or equal to 10 μm, so that the second electrode base layer is in good contact connection with the dielectric layer.
In one embodiment, the first outer insulating layer includes at least one of a thermosetting epoxy ink or a photosensitive epoxy ink, so that the first outer insulating layer has a better insulating property. In this embodiment, the first outer insulating layer is a thermosetting epoxy resin ink. In one embodiment, the thickness of the first outer insulating layer is 10 μm to 20 μm. In this embodiment, the thickness of the first outer insulating layer is 15 μm.
In one embodiment, the second outer insulating layer includes at least one of a thermosetting epoxy ink or a photosensitive epoxy ink, so that the second outer insulating layer has a better insulating property. In this embodiment, the second outer insulating layer is a thermosetting epoxy resin ink. In one embodiment, the second outer insulating layer has a thickness of 10 μm to 20 μm. In this embodiment, the thickness of the second outer insulating layer is 15 μm.
In one embodiment, each of the dielectric layer bodies includes at least one of an epoxy layer or a fiberglass layer. In this embodiment, each of the dielectric layer bodies is an epoxy resin layer. In other embodiments, each of the dielectric layer bodies may also be a combination of an epoxy layer and a glass fiber layer.
In one embodiment, the prepreg layer includes at least one of an epoxy layer or an acrylic layer. In this embodiment, the prepreg layer is an epoxy resin layer.
The method for manufacturing a capacitor according to any one of the above embodiments includes some or all of the following steps.
And providing a prepreg layer and two dielectric layer bodies. In this example, one epoxy prepreg and two epoxy boards were taken. The epoxy resin prepreg is a prepreg layer, and the epoxy resin plate is a dielectric layer body. Specifically, two 0.25mm thick 18 x 24 inch epoxy boards and one 0.2mm thick epoxy prepreg were taken. The copper thickness of each epoxy board was H/H. In other embodiments, the epoxy prepregs may be replaced with acrylic prepregs. The epoxy resin board can also be replaced by an epoxy resin and glass fiber composite board.
And forming a first bending integrated circuit layer and a second bending integrated circuit layer on one side of each dielectric layer body. And forming a first bent integrated circuit layer and a second bent integrated circuit layer on one side of each dielectric layer body through a PCB (printed Circuit Board) process so as to form the first bent integrated circuit layer and the second bent integrated circuit layer on one copper foil of the dielectric layer of the 0.25mm epoxy resin plate. In the present embodiment, the PCB process includes a circuit process, an etching process, a film stripping process and an inspection process. In one embodiment, the first integrated circuit layer and the second integrated circuit layer are both S-shaped, so that the first integrated circuit layer and the second integrated circuit layer are large in area and easy to manufacture.
And pressing the prepreg layer and the two dielectric layer bodies together to form a substrate of the capacitor, so that the first integrated circuit layer and the second integrated circuit layer formed by each dielectric layer body are adjacent to the prepreg layer. In one embodiment, the prepreg layer and the two dielectric layer bodies are laminated together by a copper-clad plate laminating machine under the heating and pressing conditions. In this example, a 0.2mm epoxy prepreg and two 0.25mm epoxy boards were pressed together under heat and pressure, and each 0.25mm epoxy board had the first integrated circuit layer in a bent shape and the second integrated circuit layer in a bent shape facing inward, and the first integrated circuit layer in a non-bent shape and the second integrated circuit layer in a bent shape facing outward, to form a substrate of an integrated circuit capacitor 1.0mm thick.
And respectively processing a first penetrating surface and a second penetrating surface on two sides of the substrate. The first penetrating surface penetrates through the first dielectric layer body, the prepreg layer and the second dielectric layer body respectively, so that the first integrated circuit layer is exposed on the first penetrating surface. The second penetrating surface penetrates through the first dielectric layer body, the prepreg layer and the second dielectric layer body respectively, so that the second integrated circuit layer is exposed on the second penetrating surface.
In one embodiment, the substrate is drilled through on both sides to form a first through surface and a second through surface. Specifically, the laser processing technology is adopted to drill through the two sides of the substrate, and the flatness of the first penetrating surface and the second penetrating surface is ensured.
In one embodiment, after the step of processing the first penetrating surface and the second penetrating surface on the two sides of the substrate respectively, the manufacturing method further includes the steps of: and removing the glue stain at the first integrated circuit layer on the first penetrating surface and removing the glue stain at the second integrated circuit layer on the second penetrating surface. Further, adopt plasma to remove gluey technology and get rid of on the face of running through first integrated circuit layer with the glue stain of second integrated circuit layer department to the glue stain of first integrated circuit layer and second integrated circuit layer department on will running through the face gets rid of totally, ensures the connection requirement of the hookup location of first integrated circuit layer and the hookup location of second integrated circuit layer, makes the hookup location of first integrated circuit layer and the hookup location of second integrated circuit layer expose clean copper layer, and the roughness on first electrode surface is less than or equal to 10 μm.
And forming a first electrode base layer electrically connected with the first integrated circuit layer on the first penetrating surface, and forming a second electrode base layer electrically connected with the second integrated circuit layer on the second penetrating surface. And forming a first electrode base layer electrically connected with the first integrated circuit layer on the first penetrating surface through a copper deposition process or a copper electroplating process, and forming a second electrode base layer electrically connected with the second integrated circuit layer on the second penetrating surface so as to form uniform copper layers on the first penetrating surface and the second penetrating surface. In one embodiment, the first electrode and the second electrode have a thickness of 15 μm to 20 μm. In one embodiment, the first electrode and the second electrode are both copper layers, so that the first electrode and the first integrated circuit layer, and the second electrode and the second integrated circuit layer have better conductivity. In one embodiment, the surface roughness of the first electrode and the second electrode is less than or equal to 3.5 μm, so that the first electrode and the second electrode are relatively flat.
And forming a first outer-layer insulating layer on one side of one of the dielectric layer bodies, which is far away from the prepreg layer, and forming a second outer-layer insulating layer on one side of the other dielectric layer body, which is far away from the prepreg layer. In one embodiment, the first outer insulating layer and the second outer insulating layer are formed by a printing process. In this embodiment, the first outer insulating layer and the second outer insulating layer are both thermosetting epoxy resin ink. In one embodiment, the first outer insulating layer and the second outer insulating layer each have a thickness of 10 to 20 μm.
In one embodiment, after the step of forming the first outer insulating layer on the side of one of the dielectric layer bodies facing away from the prepreg layer and forming the second outer insulating layer on the side of the other of the dielectric layer bodies facing away from the prepreg layer, the manufacturing method further includes: and forming a first covering layer on the outer wall of the first electrode, and forming a second covering layer on the outer wall of the second electrode. The first covering layer and the second covering layer are both nickel layers, so that the conductivity of the first electrode and the second electrode is improved. Wherein the thickness of the nickel layer is 2.5-4.0 μm, and the thickness of the gold layer is 0.025 μm. In other embodiments, the nickel layer may be replaced with a silver layer.
In one embodiment, after the steps of forming the first cover layer on the first electrode outer wall and forming the second cover layer on the second electrode outer wall, the manufacturing method further includes: the capacitor is subjected to laser dicing processing to form a plurality of multilayer integrated circuit capacitors.
In the capacitor, the first electrode and the second electrode are oppositely arranged, and two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode, so that the first outer insulating layer separates and insulates one end of the first electrode from one end of the second electrode; similarly, the second outer insulating layer separates and insulates the other end of the first electrode from the other end of the second electrode; thus, the first outer insulating layer and the second outer insulating layer jointly separate the first electrode and the second electrode; because the dielectric layer is filled in a containing cavity which is defined by the first electrode, the first outer insulating layer, the second electrode and the second outer insulating layer together, and the dielectric layer comprises the prepreg layer and two dielectric layer bodies which are respectively positioned at two sides of the prepreg layer, one side of any one dielectric layer body adjacent to the prepreg layer is provided with a plurality of first integrated circuit layers and a plurality of second integrated circuit layers, and two first integrated circuit layers which are respectively positioned at different dielectric layer bodies along the cross section direction which is vertical to the extending direction of the first outer insulating layer are arranged oppositely, the capacitor can better store energy, and because each first integrated circuit layer and each second integrated circuit layer are bent, each first integrated circuit layer and each second integrated circuit layer have larger areas, and each first integrated circuit layer is electrically connected with the first electrode, each second integrated circuit layer is electrically connected with the second electrode, so that the first electrode and the second electrode have larger opposite areas, the problem that the capacitor is limited by the size of the integrated circuit under a certain volume condition is solved, and the capacitance value of the capacitor of the integrated circuit is larger.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.
Claims (10)
1. A capacitor, comprising:
a first electrode;
a second electrode disposed opposite the first electrode;
the two sides of the first outer insulating layer are respectively connected with one end of the first electrode and one end of the second electrode;
two sides of the second outer insulating layer are respectively connected with the other end of the first electrode and the other end of the second electrode; the first electrode, the first outer insulating layer, the second electrode and the second outer insulating layer jointly enclose a containing cavity;
the dielectric layer is filled in the accommodating cavity and comprises a prepreg layer and two dielectric layer bodies, the two dielectric layer bodies are respectively positioned on two sides of the prepreg layer, one side of any one of the dielectric layer bodies, which is adjacent to the prepreg layer, is provided with a plurality of first integrated circuit layers and a plurality of second integrated circuit layers, the first integrated circuit layers and the second integrated circuit layers are mutually spaced, the two first integrated circuit layers, which are respectively positioned on different dielectric layer bodies, in the cross section direction perpendicular to the extension direction of the first outer insulating layer are oppositely arranged, each first integrated circuit layer and each second integrated circuit layer are in a bent shape, each first integrated circuit layer is electrically connected with the first electrode, and each second integrated circuit layer is electrically connected with the second electrode.
2. The capacitor of claim 1, wherein the first integrated circuit layer and the second integrated circuit layer are stacked and do not contact each other.
3. The capacitor of claim 1, wherein the first integrated circuit layer and the second integrated circuit layer are each S-shaped.
4. The capacitor of any of claims 1-3, wherein a plurality of the first integrated circuit layers and a plurality of the second integrated circuit layers are spaced apart in a same dielectric layer body.
5. The capacitor of claim 4, wherein adjacent portions of said first integrated circuit layer and said second integrated circuit layer on the same dielectric layer body are staggered.
6. The capacitor according to any one of claims 1 to 3, wherein the first integrated circuit layers on both sides of the prepreg layer are conducted through the via of the prepreg layer.
7. The capacitor according to any one of claims 1 to 3, wherein the second integrated circuit layers on both sides of the prepreg layer are conducted through the via of the prepreg layer.
8. The capacitor according to any one of claims 1 to 3, wherein a line width precision of any of the lines of the first integrated circuit layer is ± 0.02 mm; the line width precision of the line of any one second integrated circuit layer is +/-0.02 mm.
9. The capacitor according to any one of claims 1 to 3, wherein the first electrode comprises a first electrode base layer and a first cover layer, the first cover layer covers the first electrode base layer, both ends of the first cover layer are connected to the first outer insulating layer and the second outer insulating layer, respectively, and each of the first integrated circuit layers is connected to the first electrode base layer.
10. The capacitor of claim 9, wherein the second electrode comprises a second electrode base layer and a second cover layer, the second cover layer covers the second electrode base layer, two ends of the second cover layer are respectively connected to the first outer insulating layer and the second outer insulating layer, and each of the second integrated circuit layers is connected to the second electrode base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201920737026.2U CN209912734U (en) | 2019-05-22 | 2019-05-22 | Capacitor with a capacitor element |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114783998A (en) * | 2022-06-16 | 2022-07-22 | 合肥晶合集成电路股份有限公司 | Integrated circuit and forming method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114783998A (en) * | 2022-06-16 | 2022-07-22 | 合肥晶合集成电路股份有限公司 | Integrated circuit and forming method thereof |
| CN114783998B (en) * | 2022-06-16 | 2022-09-02 | 合肥晶合集成电路股份有限公司 | Integrated circuit and forming method thereof |
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