CN114783998A - Integrated circuit and forming method thereof - Google Patents
Integrated circuit and forming method thereof Download PDFInfo
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- CN114783998A CN114783998A CN202210677361.4A CN202210677361A CN114783998A CN 114783998 A CN114783998 A CN 114783998A CN 202210677361 A CN202210677361 A CN 202210677361A CN 114783998 A CN114783998 A CN 114783998A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
The invention provides an integrated circuit. In the integrated circuit, a substrate comprises a first capacitor area and a second capacitor area, and an interlayer dielectric layer is formed on the upper surface of the substrate; at least two first polar plates are arranged on the interlayer dielectric layer of the first capacitor area at intervals, and the side walls of two adjacent first polar plates are opposite to each other and form the side surface of the first groove; at least two second polar plates are arranged on the interlayer dielectric layer of the second capacitor area at intervals, and the side walls of two adjacent second polar plates are opposite to each other and form the side surface of the second groove; a dielectric layer covering the inner surfaces of the first and second trenches; the first capacitor comprises two adjacent first plates and a dielectric layer between the two adjacent first plates, the second capacitor comprises two adjacent second plates and a dielectric layer between the two adjacent second plates, and the longitudinal section shapes of the first plates and the second plates are different, so that different first capacitors and second capacitors can be formed on one substrate, and the diversity of integrated circuits can be improved. The invention also provides a forming method of the integrated circuit.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to an integrated circuit and a method for forming the same.
Background
With the continuous advancement of technology in the semiconductor industry, integrated circuits are now provided which include a large number of circuit elements, such as transistors and the like. In addition to transistor elements for controlling voltage and/or current within a semiconductor device, which are typically provided in the form of digital and/or analog components, there is a trend to integrate additional functionality into a single semiconductor device, forming even a complete system on a single chip-a system on a chip (SoC). Therefore, in addition to commonly used resistors, passive circuit elements, particularly capacitors and the like, must be provided in many types of integrated circuits.
In a 3D FinFET (Fin-Field-Effect Transistor) semiconductor process, an integrated circuit is formed that typically includes a plurality of coupled capacitors. FIG. 1 is a cross-sectional diagram of an integrated circuit. As shown in fig. 1, the fin plates 101a of each capacitor are formed on the interlayer dielectric layer 102 on the upper surface of the substrate 100, the longitudinal cross-section (perpendicular to the upper surface of the substrate 100) of each fin plate 101a has the same shape, and the dielectric layer 108 between two adjacent fin plates 101a is usually only a silicon oxide layer. Therefore, the diversification of the integrated circuit is limited, and the function of the integrated circuit is not favorably improved.
Disclosure of Invention
The invention provides an integrated circuit and a forming method thereof, which can improve the diversification of the integrated circuit and enhance the function of the integrated circuit.
One aspect of the invention provides an integrated circuit. The integrated circuit includes:
the capacitor comprises a substrate, a first capacitor and a second capacitor, wherein the substrate comprises a first capacitor area used for forming a first capacitor and a second capacitor area used for forming a second capacitor, and an interlayer dielectric layer is formed on the upper surface of the substrate;
the at least two first polar plates are arranged on the interlayer dielectric layer of the first capacitor area at intervals, and the side walls of the two adjacent first polar plates are opposite to each other and form the side surface of the first groove;
at least two second polar plates which are arranged on the interlayer dielectric layer of the second capacitor area at intervals, and the side walls of two adjacent second polar plates are opposite to each other and form the side surface of a second groove;
a dielectric layer filled in the first trench and the second trench and covering inner surfaces of the first trench and the second trench;
the first polar plate and the second polar plate have different longitudinal section shapes, and the longitudinal sections are in a plane vertical to the upper surface of the substrate; the first capacitor comprises two adjacent first polar plates and a dielectric layer between the two adjacent first polar plates; the second capacitor comprises two adjacent second polar plates and a dielectric layer between the two adjacent second polar plates.
Optionally, the longitudinal cross section of the first polar plate is one of an hourglass shape with large upper and lower ends and small middle, a figure formed by splicing a rectangle and a regular trapezoid up and down, a rectangle and a regular trapezoid, and the longitudinal cross section of the second polar plate is the other of the hourglass shape with large upper and lower ends and small middle, the figure formed by splicing a rectangle and a regular trapezoid up and down, a rectangle and a regular trapezoid.
Optionally, the dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer is filled in the lower end portions of the first trench and the second trench, and the second dielectric layer covers the upper surface of the first dielectric layer and covers the sidewalls of the upper end portions of the first trench and the second trench.
Optionally, the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.
Optionally, the dielectric layer is recessed into the first trench and the second trench, and a groove is defined in each of the first trench and the second trench; the first capacitor and the second capacitor both comprise third polar plates which are conformally covered on the inner surfaces of the grooves.
Optionally, the material of the first plate and the second plate is the same as the material of the substrate; the third polar plate is made of metal.
Optionally, the first capacitor region and the second capacitor region are adjacent to each other, a sidewall of the first plate of the first capacitor region near the edge of the second capacitor region is opposite to a sidewall of the second plate of the second capacitor region near the edge of the first capacitor region, and the opposite sidewalls form a side surface of the third trench; the dielectric layer is also filled in the third groove and covers the inner surface of the third groove; the integrated circuit comprises a third capacitor, wherein the third capacitor comprises a dielectric layer in the third groove, and a first polar plate and a second polar plate which are positioned on two sides of the third groove.
Another aspect of the invention provides a method of forming an integrated circuit. The forming method comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, an interlayer dielectric layer and an epitaxial layer which are sequentially stacked from bottom to top, and the substrate comprises a first capacitor area for forming a first capacitor and a second capacitor area for forming a second capacitor;
patterning the epitaxial layer, forming at least two first polar plates which are arranged at intervals on the first capacitor area, and forming at least two second polar plates which are arranged at intervals on the second capacitor area; the first polar plate and the second polar plate have different longitudinal section shapes, and the longitudinal sections are in a plane vertical to the upper surface of the substrate; the side walls of two adjacent first polar plates are opposite and form the side surface of the first groove; the side walls of two adjacent second polar plates are opposite and form the side surface of a second groove;
filling a dielectric layer in the first trench and the second trench, wherein the dielectric layer covers the inner surfaces of the first trench and the second trench;
the first capacitor comprises two adjacent first polar plates and a dielectric layer between the two adjacent first polar plates; the second capacitor comprises two adjacent second polar plates and a dielectric layer between the two adjacent second polar plates.
Optionally, the method for performing patterning processing on the epitaxial layer includes:
forming a patterned first mask layer on the epitaxial layer;
performing a first etching process by using the patterned first mask layer as a mask, etching the epitaxial layer on the first capacitor region and stopping on the interlayer dielectric layer, wherein the residual epitaxial layer on the first capacitor region is used as the at least two first electrode plates;
removing the first mask layer, and forming a patterned second mask layer on the epitaxial layer and the substrate;
performing a second etching process by taking the patterned second mask layer as a mask, etching the epitaxial layer on the second capacitor region and stopping on the interlayer dielectric layer, wherein the residual epitaxial layer on the second capacitor region is taken as the at least two second plates;
wherein the first etching process and the second etching process have different process conditions.
Optionally, the providing a semiconductor structure includes:
providing the substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer at least covers the upper surface of the substrate of the first capacitor area and the second capacitor area;
and performing ion implantation to form the interlayer dielectric layer on the interface of the substrate and the epitaxial layer.
In the integrated circuit and the forming method thereof, at least two first polar plates and at least two second polar plates are respectively formed on a first capacitor area and a second capacitor area of a substrate, the longitudinal section shapes of the first polar plates and the second polar plates are different, the side walls of two adjacent first polar plates are opposite and form the side surface of a first groove, the side walls of two adjacent second polar plates are opposite and form the side surface of a second groove, and a dielectric layer is filled in the first groove and the second groove and covers the inner surfaces of the first groove and the second groove, so that a first capacitor can be formed on the first capacitor area, and a second capacitor can be formed on the second capacitor area. Because the longitudinal section shapes of the first polar plate and the second polar plate are different, the first capacitor and the second capacitor have different performances, so that two capacitors with different performances can be integrated in an integrated circuit, the diversity of the integrated circuit is improved, and the function of the integrated circuit is enhanced.
Drawings
FIG. 1 is a cross-sectional diagram of an integrated circuit.
Fig. 2 is a cross-sectional view of an interlayer dielectric layer and an epitaxial layer formed on a substrate in accordance with an embodiment of the present invention.
Fig. 3 is a cross-sectional view after forming a first plate on the first capacitor region according to an embodiment of the invention.
Fig. 4 is a cross-sectional view of a second plate formed on the second capacitor region according to an embodiment of the invention.
Fig. 5 is a cross-sectional view after forming a first dielectric layer on a substrate in an embodiment of the invention.
Fig. 6 is a cross-sectional view after forming a second dielectric layer on a substrate in an embodiment of the invention.
Fig. 7 is a cross-sectional view after forming a third plate on a substrate in an embodiment of the invention.
Fig. 8 is a cross-sectional view of an integrated circuit according to an embodiment of the invention.
Description of reference numerals:
100-a substrate; 100 a-a first capacitive region; 100 b-a second capacitive region; 101-an epitaxial layer; 101 a-fin plate; 102-an interlayer dielectric layer; 103-a first plate; 104-a first trench; 105-a second plate; 106-second trenches; 107-third trenches; 108-a dielectric layer; 108 a-a first dielectric layer; 108 b-a second dielectric layer; 109-grooves; 110-a third polar plate; 111-a third dielectric layer; 112-a first capacitance; 113-a second capacitance; 114-third capacitance.
Detailed Description
The integrated circuit and the forming method thereof according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to increase the diversification of the integrated circuit and enhance the function of the integrated circuit, the embodiment provides an integrated circuit. The integrated circuit includes a substrate, at least two first plates, at least two second plates, and a dielectric layer. The substrate comprises a first capacitor area used for forming a first capacitor and a second capacitor area used for forming a second capacitor, and an interlayer dielectric layer is formed on the upper surface of the substrate. At least two first polar plates are arranged on the interlayer dielectric layer of the first capacitor area at intervals, and the side walls of two adjacent first polar plates are opposite to each other and form the side surface of the first groove. At least two second electrode plates are arranged on the interlayer dielectric layer of the second capacitor area at intervals, and the side walls of two adjacent second electrode plates are opposite to each other and form the side surface of the second groove. The dielectric layer is filled in the first groove and the second groove and covers the inner surfaces of the first groove and the second groove. Wherein, in a plane perpendicular to the upper surface of the substrate, the longitudinal section shapes of the first polar plate and the second polar plate are different; the first capacitor comprises two adjacent first polar plates and a dielectric layer between the two adjacent first polar plates; the second capacitor comprises two adjacent second polar plates and a dielectric layer between the two adjacent second polar plates.
The integrated circuit of this embodiment will be described below with reference to fig. 8.
In this embodiment, the substrate 100 includes a first capacitor region 100a for forming the first capacitor 112 and a second capacitor region 100b for forming the second capacitor 113. Alternatively, the first capacitor 112 is disposed on the first capacitor area 100a, and the second capacitor 113 is disposed on the second capacitor area 100 b. The substrate 100 may be a silicon substrate. But is not limited thereto, the substrate 100 may also be a germanium substrate or a silicon germanium substrate.
An interlayer dielectric layer 102 is formed on the upper surface of the substrate 100, and the interlayer dielectric layer 102 at least covers the upper surfaces of the first capacitor region 100a and the second capacitor region 100b to isolate the plates (the first plate 103 and the second plate 105) on the interlayer dielectric layer 102 from the substrate 100 under the interlayer dielectric layer 102. In one embodiment, the interlayer dielectric layer 102 may cover the entire upper surface of the substrate 100.
At least two first plates 103 are arranged on the interlayer dielectric layer 102 of the first capacitor region 100a at intervals, sidewalls of two adjacent first plates 103 are opposite, and the opposite sidewalls of two adjacent first plates 103 form side surfaces of the first trench 104. At least two second plates 105 are disposed on the interlayer dielectric layer 102 of the second capacitor region 100b at intervals, sidewalls of two adjacent second plates 105 are opposite, and the opposite sidewalls of two adjacent second plates 105 form side surfaces of the second trench 106. The first plate 103 and the second plate 105 have different longitudinal cross-sectional shapes, and the longitudinal cross-section is in a plane perpendicular to the upper surface of the substrate 100. It should be noted that the "longitudinal section" described later can be understood as being in a plane perpendicular to the upper surface of the substrate 100.
Since the first and second plates 103 and 105 have different longitudinal sectional shapes, the first trench 104 defined by adjacent two first plates 103 has a different longitudinal sectional shape from the second trench 106 defined by adjacent two second plates 105.
In this embodiment, as shown in fig. 8, the first electrode plate 103 has an hourglass shape with a large upper end and a small middle end, and the second electrode plate 105 has a rectangular and trapezoidal vertical cross-section. But not limited thereto, the shape of the longitudinal section of the first polar plate 103 may also be one of a pattern formed by splicing a rectangle and a regular trapezoid up and down, a rectangle, a regular trapezoid and the like; the second plate 105 may have one of an hourglass shape, a rectangular shape, and a trapezoidal shape, which have large upper and lower ends and a small middle, but the first plate 103 and the second plate 105 have different longitudinal cross-sectional shapes.
The dielectric layer 108 is filled in the first trench 104 and the second trench 106, and covers the inner surfaces of the first trench 104 and the second trench 106 to isolate the two adjacent plates.
In this embodiment, as shown in fig. 8, the dielectric layer 108 may include a first dielectric layer 108a and a second dielectric layer 108b, the first dielectric layer 108a is filled in the lower end portions of the first trench 104 and the second trench 106, and the second dielectric layer 108b covers the upper surface of the first dielectric layer 108a and covers the sidewalls of the upper end portions of the first trench 104 and the second trench 106 that are not filled with the first dielectric layer 108 a.
In order to increase the capacitance of the first and second capacitors 112 and 113, the dielectric constant of the second dielectric layer 108b may be greater than that of the first dielectric layer 108 a. In this embodiment, the material of the first dielectric layer 108a may be silicon oxide; the second dielectric layer108b may be a high dielectric constant material, for example, the material of the second dielectric layer 108b includes hafnium oxide (HfO)2) Silicon oxynitride (SiON), lanthanum oxide (La)2O3) And silicon nitride (Si)3N4) And the like. The second dielectric layer 108b may have a single-layer structure including a single material, or a multi-layer structure including stacked layers of different materials. But not limited thereto, in another embodiment, the dielectric layer 108 may include only a silicon oxide layer.
As shown in fig. 8, the first capacitor 112 includes two adjacent first plates 103 and a dielectric layer between two adjacent first plates 103 (i.e., the dielectric layer 108 in the first trench 104 between two adjacent first plates 103). The second capacitor 113 includes two adjacent second plates 105 and a dielectric layer between two adjacent second plates 105 (i.e., the dielectric layer 108 in the second trench 106 between two adjacent second plates 105). Because the longitudinal section shapes of the first plate 103 and the second plate 105 are different, the distance and the space between the two first plates 103 of the first capacitor 112 are different from the distance and the space between the two second plates 105 of the second capacitor 113, so that the performances (electrical performances) of the first capacitor 112 and the second capacitor 113 are different, two capacitors with different performances can be integrated in an integrated circuit, the integration of the two capacitors is facilitated, and the functions of the integrated circuit are enhanced.
With continued reference to fig. 8, the dielectric layer 108 may be recessed into the first trench 104 and the second trench 106 and define a recess 109 in the first trench 104 and the second trench 106, respectively, and the first capacitor 112 and the second capacitor 113 may each include a third plate 110, and the third plate 110 conformally covers the inner surface of the recess 109, that is, the third plate 110 covers the inner surface of the recess 109 and allows the shape of the recess 109 to be maintained. In the first capacitor 112, the third plate 110 and the two first plates 103 on two sides thereof may form two sub-capacitors, respectively; in the second capacitor 113, the third plate 110 and the two second plates 105 on two sides thereof may form two sub-capacitors, respectively; moreover, each sub-capacitor can be independently controlled, so that the diversity of the capacitors in the integrated circuit can be provided, and the performance of the integrated circuit can be improved.
In this embodiment, the material of the first plate 103 and the second plate 105 may be the same as the material of the substrate 100, that is, the first plate 103 and the second plate 105 may be formed by using an epitaxial layer on the substrate 100. The material of the third electrode plate 110 may be a metal, for example, the material of the third electrode plate 110 may include at least one of titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium compound (TiAl), tungsten (W), and the like. The third plate 110 may have a single-layer structure including a single material, or a multi-layer structure in which different material layers are stacked.
To further increase the diversification of the integrated circuit, the integrated circuit may further comprise a third capacitor 114, as shown in fig. 8.
Specifically, the first capacitor region 100a and the second capacitor region 100b may be adjacent to each other, and a sidewall of the first plate 103 of the first capacitor region 100a near the edge of the second capacitor region 100b is opposite to a sidewall of the second plate 105 of the second capacitor region 100b near the edge of the first capacitor region 100a, and the opposite sidewall forms a side surface of the third trench 107. The dielectric layer 108 may also fill the third trench 107 and cover the inner surface of the third trench 107. The third capacitor 114 comprises a dielectric layer 108 in the third trench 107 and a first plate 103 and a second plate 105 located at both sides of the third trench 107.
Due to the different longitudinal cross-sectional shapes of the first plate 103 and the second plate 105, the longitudinal cross-sectional shape of the third trench 107 defined by the sidewalls of the first plate 103 opposite to the second plate 105 is different from the longitudinal cross-sectional shape of the first trench 104 and the second trench 106, so that the third capacitor 114 has different electrical properties from the first capacitor 112 and the second capacitor 113.
In this embodiment, the first dielectric layer 108a, the second dielectric layer 108b and the third plate 110 may not fill the first trench 104, the second trench 106 and the third trench 107, so that the first trench 104, the second trench 106 and the third trench 107 are all filled with the third dielectric layer 111, and the third dielectric layer 111 is located on the third plate 110 and fills the first trench 104, the second trench 106 and the third trench 107. However, when the first dielectric layer 108a, the second dielectric layer 108b and the third plate 110 fill the first trench 104, the second trench 106 and the third trench 107, the third dielectric layer 111 is not required; alternatively, only one of the first trench 104, the second trench 106, and the third trench 107 may be filled with the third dielectric layer 111.
In this embodiment, the integrated circuit further includes a plurality of capacitor contacts (not shown), which are respectively connected to the first plate 103, the second plate 105 and the third plate 110, so as to apply a voltage to the first plate 103, the second plate 105 and the third plate 110.
The present embodiment also provides a method for forming an integrated circuit, which can be used to form the integrated circuit. However, the integrated circuit may be formed by other methods.
The forming method of the integrated circuit comprises the following steps:
s1, providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, an interlayer dielectric layer and an epitaxial layer which are sequentially stacked from bottom to top, and the substrate comprises a first capacitor area for forming a first capacitor and a second capacitor area for forming a second capacitor;
s2, carrying out patterning treatment on the epitaxial layer, forming at least two first polar plates which are arranged at intervals on the first capacitor area, and forming at least two second polar plates which are arranged at intervals on the second capacitor area; the first polar plate and the second polar plate have different longitudinal section shapes, and the longitudinal sections are in a plane vertical to the upper surface of the substrate; the side walls of two adjacent first polar plates are opposite to each other and form the side surface of the first groove; the side walls of two adjacent second polar plates are opposite to each other and form the side surface of a second groove;
s3, filling a dielectric layer in the first trench and the second trench, wherein the dielectric layer covers inner surfaces of the first trench and the second trench;
the first capacitor comprises two adjacent first polar plates and a dielectric layer between the two adjacent first polar plates; the second capacitor comprises two adjacent second polar plates and a dielectric layer between the two adjacent second polar plates.
The method of forming the integrated circuit of the present embodiment will be described below with reference to fig. 2 to 8.
As shown in fig. 2, the semiconductor structure includes a substrate 100, an interlayer dielectric layer 102, and an epitaxial layer 101 stacked in sequence from bottom to top, where the substrate 100 includes a first capacitor region 100a for forming a first capacitor and a second capacitor region 100b for forming a second capacitor.
In step S1, the method for providing a semiconductor structure may include: providing the substrate 100; forming an epitaxial layer 101 on the substrate 100, wherein the epitaxial layer 101 at least covers the upper surface of the substrate of the first capacitor region 100a and the second capacitor region 100 b; and performing ion implantation to form the interlayer dielectric layer 102 on the interface between the substrate 100 and the epitaxial layer 101. In one embodiment, epitaxial layer 101 may cover the upper surface of substrate 100. The implantation dopant for the ion implantation may be oxygen, and the material of the interlayer dielectric layer 102 may be an oxide, for example, when the substrate 100 is a silicon substrate, the interlayer dielectric layer 102 is silicon oxide.
In step S2, the patterning process on the epitaxial layer 101 to form at least two first plates 103 arranged at intervals on the first capacitor area 100a and at least two second plates 105 arranged at intervals on the second capacitor area 100b includes the following sub-steps.
S21, a patterned first mask layer (not shown) is formed on the epitaxial layer 101, wherein the patterned first mask layer covers the second capacitor region 100b and exposes a portion of the epitaxial layer 101 on the first capacitor region 100 a.
S22, as shown in fig. 3, with the patterned first mask layer as a mask, performing a first etching process to etch the epitaxial layer 101 on the first capacitor area 100a and stop on the interlayer dielectric layer 102, where the remaining epitaxial layer on the first capacitor area 100a is used as the at least two first electrode plates 103, and sidewalls of two adjacent first electrode plates 103 are opposite to each other and form a side surface of the first trench 104.
S23, removing the first mask layer, and forming a patterned second mask layer (not shown) on the epitaxial layer 101 and the substrate 100, wherein the patterned second mask layer covers the first capacitor region 100a and exposes a portion of the epitaxial layer 101 on the second capacitor region 100 b.
S24, using the patterned second mask layer as a mask, as shown in fig. 4, performing a second etching process to etch the epitaxial layer on the second capacitor region 100b and stop on the interlayer dielectric layer 102, where the remaining epitaxial layer on the second capacitor region 100b is used as the at least two second plates 105, and sidewalls of two adjacent second plates 105 are opposite to each other and form a side surface of the second trench 106.
It should be noted that the first etching process and the second etching process have different process conditions, so that the first trench 104 etched and formed by the first etching process and the second trench 106 etched and formed by the second etching process have different longitudinal cross-sectional shapes, and thus the first electrode plate 103 and the second electrode plate 105 having different longitudinal cross-sectional shapes can be formed.
The first polar plate 103 may have a vertical cross-sectional shape of one of an hourglass shape with large upper and lower ends and a small middle, a figure formed by vertically splicing a rectangle and a regular trapezoid, a rectangle, and a regular trapezoid, and the second polar plate 105 may have a vertical cross-sectional shape of another one of an hourglass shape with large upper and lower ends and a small middle, a figure formed by vertically splicing a rectangle and a regular trapezoid, a rectangle, and a regular trapezoid. For example, the etching gas (including Cl) is adjusted during the first etching process and the second etching process2HBr and CF4) The ratio (c) may form the first plate 103 and the second plate 105 in the above-described longitudinal sectional shape.
As shown in fig. 4, the first capacitor region 100a and the second capacitor region 100b may be adjacent to each other, and a sidewall of the first plate 103 of the first capacitor region 100a near the edge of the second capacitor region 100b is opposite to and opposite to a sidewall of the second plate 105 of the second capacitor region 100b near the edge of the first capacitor region 100a, and the opposite sidewall forms a side surface of the third trench 107. The third trench 107 has a longitudinal sectional shape different from the longitudinal sectional shapes of the first trench 104 and the second trench 106.
Next, step S3 is executed, as shown in fig. 5 and fig. 6, a dielectric layer 108 is filled in the first trench 104 and the second trench 106. The dielectric layer 108 may include a first dielectric layer 108a and a second dielectric layer 108 b.
Specifically, as shown in fig. 5, a first dielectric layer is formed, and the first dielectric layer is filled in the first trench 104, the second trench 106, and the third trench 107 from bottom to top; performing an etch-back process to remove a portion of the first dielectric layer, and filling the remaining first dielectric layer 108a in the lower end portions of the first trench 104, the second trench 106, and the third trench 107; as shown in fig. 6, a second dielectric layer 108b is formed, the second dielectric layer 108b covering the upper surface of the first dielectric layer 108a and covering sidewalls of the upper end portions of the first trench 104, the second trench 106, and the third trench 107.
As shown in fig. 6, in the present embodiment, the dielectric layer 108 is recessed into the first trench 104, the second trench 106 and the third trench 107, and a recess 109 is defined in each of the first trench 104, the second trench 106 and the third trench 107.
The method of forming the integrated circuit may further include: as shown in fig. 7, a third plate 110 is formed in the recess 109 in the first trench 104, the second trench 106 and the third trench 107, and the third plate 110 may conformally cover the inner surface of the recess 109; as shown in fig. 8, the third dielectric layer 111 is filled in the portion of the recess 109 that is not filled.
Referring to fig. 8, in the present embodiment, the first capacitor 112 may include two adjacent first plates 103, a dielectric layer 108 between two adjacent first plates 103 (i.e., the dielectric layer 108 in the first trench 104 between two adjacent first plates 103), a third plate 110 in the first trench 104, and a third dielectric layer 111. The second capacitor 113 may include two adjacent second plates 105, a dielectric layer 108 between two adjacent second plates 105 (i.e., the dielectric layer 108 in the second trench 106 between two adjacent second plates 105), a third plate 110 in the second trench 106, and a third dielectric layer 111. The third capacitor 114 may include adjacent first and second plates 103 and 105, a dielectric layer 108 in a third trench 107 between the adjacent first and second plates 103 and 105, and a third plate 110 and a third dielectric layer 111 in the third trench 107.
In this embodiment, the integrated circuit may further include a fin field effect transistor (not shown). The fin field effect transistor may include a fin formed on a substrate, and a high dielectric layer number dielectric layer and a metal gate sequentially covering the fin. In order to save mask and shorten the process flow, the second dielectric layer 108b may be formed simultaneously with the high-k dielectric layer, and the third plate 110 may be formed simultaneously with the metal gate. Alternatively, the second dielectric layer 108b and the third plate 110 may be formed in a replacement metal gate process (RMG).
By using the method for forming an integrated device of this embodiment, the first capacitor 112, the second capacitor 113, and the third capacitor 114 with different properties can be formed on one substrate at the same time, so that an integrated circuit in which the first capacitor 112, the second capacitor 113, and the third capacitor 114 are integrated at the same time can be formed, which is helpful for improving the diversity of the integrated circuit and enhancing the functions of the integrated circuit.
It should be noted that the embodiments of the present application are described in a progressive manner, and the forming method of the integrated circuit described later mainly focuses on differences from the integrated circuit described earlier, and the same and similar parts may be referred to each other. For the method for forming the integrated circuit disclosed in the embodiment, the description is relatively simple because the method corresponds to the integrated circuit disclosed in the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art may make possible variations and modifications of the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modifications, equivalent changes and modifications of the above embodiments according to the technical essence of the present invention shall fall within the protection scope of the technical solution of the present invention.
Claims (10)
1. An integrated circuit, comprising:
the capacitor comprises a substrate, a first capacitor and a second capacitor, wherein the substrate comprises a first capacitor area for forming a first capacitor and a second capacitor area for forming a second capacitor;
the at least two first polar plates are arranged on the interlayer dielectric layer of the first capacitor area at intervals, and the side walls of the two adjacent first polar plates are opposite to each other and form the side surface of the first groove;
the at least two second polar plates are arranged on the interlayer dielectric layer of the second capacitor area at intervals, and the side walls of the two adjacent second polar plates are opposite to each other and form the side surface of the second groove;
a dielectric layer filled in the first trench and the second trench and covering inner surfaces of the first trench and the second trench;
the first polar plate and the second polar plate have different longitudinal section shapes, and the longitudinal sections are in a plane vertical to the upper surface of the substrate; the first capacitor comprises two adjacent first polar plates and a dielectric layer between the two adjacent first polar plates; the second capacitor comprises two adjacent second polar plates and a dielectric layer between the two adjacent second polar plates.
2. The integrated circuit of claim 1, wherein the first plate has a longitudinal cross-sectional shape of one of an hourglass shape with a large upper end and a small middle end, a pattern formed by vertically splicing a rectangle and a regular trapezoid, a rectangle, and a regular trapezoid, and the second plate has a longitudinal cross-sectional shape of another one of an hourglass shape with a large upper end and a small middle end, a pattern formed by vertically splicing a rectangle and a regular trapezoid, a rectangle, and a regular trapezoid.
3. The integrated circuit of claim 1, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, the first dielectric layer filling lower ends of the first trench and the second trench, the second dielectric layer covering an upper surface of the first dielectric layer and covering sidewalls of the upper ends of the first trench and the second trench.
4. The integrated circuit of claim 3, wherein the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer.
5. The integrated circuit of claim 1, wherein the dielectric layer is recessed into the first trench and the second trench and defines a recess in the first trench and the second trench, respectively; the first capacitor and the second capacitor both comprise third polar plates which are conformally covered on the inner surfaces of the grooves.
6. The integrated circuit of claim 5, wherein a material of the first plate and the second plate is the same as a material of the substrate; the third polar plate is made of metal.
7. The integrated circuit of claim 1, wherein the first capacitor region and the second capacitor region are adjacent, a sidewall of the first plate of the first capacitor region near an edge of the second capacitor region is opposite to a sidewall of the second plate of the second capacitor region near an edge of the first capacitor region, and the opposite sidewall forms a side surface of a third trench; the dielectric layer is also filled in the third groove and covers the inner surface of the third groove; the integrated circuit comprises a third capacitor, wherein the third capacitor comprises a dielectric layer in the third groove, and a first polar plate and a second polar plate which are positioned on two sides of the third groove.
8. A method of forming an integrated circuit, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, an interlayer dielectric layer and an epitaxial layer which are sequentially stacked from bottom to top, and the substrate comprises a first capacitor area for forming a first capacitor and a second capacitor area for forming a second capacitor;
patterning the epitaxial layer, forming at least two first polar plates which are arranged at intervals on the first capacitor area, and forming at least two second polar plates which are arranged at intervals on the second capacitor area; the first polar plate and the second polar plate have different longitudinal section shapes, and the longitudinal sections are in a plane vertical to the upper surface of the substrate; the side walls of two adjacent first polar plates are opposite and form the side surface of the first groove; the side walls of two adjacent second polar plates are opposite and form the side surface of a second groove;
filling a dielectric layer in the first groove and the second groove, wherein the dielectric layer covers the inner surfaces of the first groove and the second groove;
the first capacitor comprises two adjacent first polar plates and a dielectric layer between the two adjacent first polar plates; the second capacitor comprises two adjacent second polar plates and a dielectric layer between the two adjacent second polar plates.
9. The method of forming as claimed in claim 8, wherein patterning the epitaxial layer comprises:
forming a patterned first mask layer on the epitaxial layer;
performing a first etching process by using the patterned first mask layer as a mask, etching the epitaxial layer on the first capacitor region and stopping on the interlayer dielectric layer, wherein the residual epitaxial layer on the first capacitor region is used as the at least two first electrode plates;
removing the first mask layer, and forming a patterned second mask layer on the epitaxial layer and the substrate;
performing a second etching process by using the patterned second mask layer as a mask, etching the epitaxial layer on the second capacitor region and stopping on the interlayer dielectric layer, wherein the residual epitaxial layer on the second capacitor region is used as the at least two second plates;
wherein the first etching process and the second etching process have different process conditions.
10. The method of forming of claim 8, wherein the providing a semiconductor structure comprises:
providing the substrate;
forming an epitaxial layer on the substrate, wherein the epitaxial layer at least covers the upper surface of the substrate of the first capacitor area and the second capacitor area;
and performing ion implantation to form the interlayer dielectric layer on the interface of the substrate and the epitaxial layer.
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