CN209785943U

CN209785943U - InAlN-GaN HEMT device inserted with insulating buried layer

Info

Publication number: CN209785943U
Application number: CN201920358484.5U
Authority: CN
Inventors: 任舰
Original assignee: Huaiyin Normal University
Current assignee: Huaiyin Normal University
Priority date: 2019-03-21
Filing date: 2019-03-21
Publication date: 2019-12-13
Anticipated expiration: 2029-03-21

Abstract

An InAlN-GaN HEMT device inserted with an insulating buried layer relates to the field of manufacturing of semiconductor power devices. The InAlN-GaN HEMT device comprises a SiC substrate, a GaN nucleating layer, a GaN buffer layer, an insulating buried layer, an AlN insert layer, an InAlN barrier layer, a GaN cap layer, an SiN passivation layer, a grid electrode, a source electrode and a drain electrode, wherein the GaN nucleating layer is arranged above the SiC substrate, the GaN buffer layer is arranged above the GaN nucleating layer, the insulating buried layer grows inside the GaN buffer layer and the AlN insert layer, the InAlN barrier layer grows on the upper surface of the AlN insert layer, the SiN passivation layer is arranged on the upper surface of the GaN cap layer, and the grid electrode is positioned between the source electrode and the drain electrode. After the technical scheme is adopted, the beneficial effects of the utility model are that: the structure design is reasonable, the input capacitance is further reduced and the threshold voltage is improved on the premise of avoiding the inverse piezoelectric effect.

Description

InAlN-GaN HEMT device inserted with insulating buried layer

Technical Field

The utility model relates to a semiconductor device makes technical field, concretely relates to insert InAlN-GaN HEMT device of insulating buried layer.

Background

Because the GaN material has good electrical characteristics such as wide forbidden band width, high breakdown electric field, high thermal conductivity, corrosion resistance and the like, the GaN material is praised as a third-generation semiconductor material following a first-generation germanium and silicon semiconductor material, a second-generation gallium arsenide and an indium phosphide compound semiconductor material, and is an ideal material for manufacturing high-temperature, high-voltage, high-frequency and high-power electronic devices. Particularly, the AlGaN/GaN heterojunction with remarkable piezoelectric and spontaneous polarization effects can induce high-concentration two-dimensional electron gas (2 DEG) at an interface, and is a core structure for preparing HEMT at present. However, the AlGaN/GaN hetero-interface has inverse piezoelectric effect, which causes reliability problems such as premature breakdown and current degradation when the device works, and needs to be avoided. Besides, the HEMT device is often used as a power switch, the threshold voltage of the HEMT device directly affects the reliability of the whole circuit system operation, but the threshold voltage of the conventional HEMT device usually does not reach the safe voltage of the circuit operation, so that it is very critical to further raise the threshold voltage of the HEMT device.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to prior art's defect and not enough, provide an insert InAlN-GaN HEMT device of insulating buried layer, its structural design is reasonable, has avoided under the prerequisite of inverse piezoelectric effect, further reduces input capacitance, improves threshold voltage, has important meaning to the preparation of GaN base HEMT device and its electrical reliability of improvement.

In order to achieve the above purpose, the utility model adopts the following technical scheme: the GaN-based light-emitting diode comprises a SiC substrate 1, a GaN nucleating layer 2, a GaN buffer layer 3, an insulating buried layer 4, an AlN insert layer 5, an InAlN barrier layer 6, a GaN cap layer 7, an SiN passivation layer 8, a grid 9, a source electrode 10 and a drain electrode 11, wherein the GaN nucleating layer 2 is arranged above the SiC substrate 1, the GaN buffer layer 3 is arranged above the GaN nucleating layer 2, the AlN insert layer 5 is arranged above the GaN buffer layer 3, the insulating buried layer 4 grows inside the GaN buffer layer 3 and the AlN insert layer 5, the InAlN barrier layer 6 grows on the upper surface of the AlN insert layer 5, the GaN cap layer 7 is arranged above the InAlN barrier layer 6, the SiN passivation layer 8 is arranged on the upper surface of the GaN cap layer 7, the source electrode 10 is formed on one side of the SiN passivation layer 8, the.

The thickness of the GaN nucleating layer 2 is 30nm, and the thickness of the GaN buffer layer 3 is 3 mu m.

The insulating buried layer 4 is positioned below the grid 9, the insulating buried layer 4 starts from the upper surface of the GaN nucleating layer 2, the insulating buried layer 4 is stopped at the lower surface of the InAlN barrier layer 6, and the length of the insulating buried layer 4 is consistent with that of the grid 9.

The AlN insert layer 5 has a thickness of 5 nm.

The thickness of the InAlN barrier layer 6 is 10 nm.

The thickness of the GaN cap layer 7 is 2 nm.

The thickness of the SiN passivation layer 8 is 150 nm.

A gate insulating layer 12 is formed below the gate 9, the gate insulating layer 12 starts from the upper surface of the GaN cap layer 7, the gate insulating layer 12 ends at the lower surface of the gate 9, and the length of the gate insulating layer 12 is consistent with that of the gate 9.

The gate insulating layer 12 is made of nitride, and the thickness of the gate insulating layer 12 is 100 nm.

The grid electrode 9 is made of Ni/Au, the thickness of the Ni/Au material is 50nm and 300nm respectively, the source electrode 10 and the drain electrode 11 are in ohmic contact, the source electrode 10 and the drain electrode 11 are made of Ti/Al/Ti/Au, and the thickness of the Ti/Al/Ti/Au material is 30nm, 120nm, 50nm and 100nm respectively.

The utility model discloses a theory of operation: the InAlN barrier layer is in lattice matching with the GaN material, after the insulating buried layer is inserted, the insulating buried layer cuts off a current path, electrons need to pass through the InAlN barrier layer above the insulating buried layer when passing through the insulating buried layer, and in the process, the electrons need to cross the InAlN/GaN triangular barrier, so that higher voltage is needed, and the purpose of improving the threshold voltage of the device is achieved. In addition, by growing the gate insulating layer, the Schottky barrier capacitance formed by the gate and the gate insulating layer is reduced.

After the technical scheme is adopted, the utility model discloses beneficial effect does: the InAlN barrier layer is in lattice matching with the GaN material, so that the linear dislocation formed by a medium interface in the material growth process is effectively reduced, and the inverse piezoelectric effect at a heterogeneous interface is avoided. On the premise of ensuring the reliability of the device, the Schottky barrier capacitance formed by the gate electrode and the gate insulating layer is reduced by growing the gate insulating layer, so that the input capacitance of the device is reduced, and the threshold voltage is improved by inserting the insulating buried layer, thereby being beneficial to the preparation of the GaN-based power device and the improvement of the electrical reliability. In general, the structure of the GaN-based HEMT device is reasonable in design, the input capacitance is further reduced and the threshold voltage is improved on the premise of avoiding the inverse piezoelectric effect, and the GaN-based HEMT device has important significance for preparing the GaN-based HEMT device and improving the electrical reliability of the GaN-based HEMT device.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of the present invention.

Description of reference numerals: the GaN-based light-emitting diode comprises a SiC substrate 1, a GaN nucleating layer 2, a GaN buffer layer 3, an insulating buried layer 4, an AlN insert layer 5, an InAlN barrier layer 6, a GaN cap layer 7, a SiN passivation layer 8, a grid electrode 9, a source electrode 10, a drain electrode 11 and a grid insulating layer 12.

Detailed Description

Referring to fig. 1, the technical solution adopted by the present embodiment is: the GaN buffer layer 3 is grown on the surface of the GaN nucleating layer 2, the insulating buried layer 2 is positioned above the GaN nucleating layer 4, the AlN inserting layer 5 is positioned outside the insulating buried layer 4, the InAlN barrier layer 6 is grown on the upper surface of the AlN inserting layer 5, the GaN cap layer 7 is arranged on the upper surface of the InAlN barrier layer, the SiN passivation layer 8 is grown on the upper surface of the GaN cap layer 7, the source electrode 10 is arranged on the left side of the grid electrode 9, and the drain electrode 11 is arranged on the right side of the grid electrode 9. The SiN passivation layer 8 reduces surface lateral leakage currents. The test electrode was plated with 2 μm gold for thickening.

The GaN nucleating layer 2 is 30nm thick, and the GaN buffer layer 3 is 3 μm thick.

The insulating buried layer 4 grows below the grid 9, the insulating buried layer 4 starts from the upper surface of the GaN nucleating layer 2 and stops at the lower surface of the InAlN barrier layer 6, and the length of the insulating buried layer 4 is the same as that of the grid 9.

The AlN insert layer 5 is 5nm thick.

The InAlN barrier layer 6 is 10nm thick.

The GaN cap layer 7 is 2nm thick.

The SiN passivation layer 8 is 150nm thick.

A gate insulating layer 12 is formed below the gate 9, the gate insulating layer 12 starts from the upper surface of the GaN cap layer 7, the gate insulating layer 12 ends at the lower surface of the gate 9, and the length of the gate insulating layer 12 is the same as that of the gate 9.

The gate insulating layer 12 is a nitride, and the gate insulating layer 12 is 100nm thick.

The grid electrode 9 is made of a Ni/Au material, the thicknesses of Ni and Au in the Ni/Au material are respectively 50nm and 300nm, the source electrode 10 and the drain electrode 11 are in ohmic contact, the source electrode 10 and the drain electrode 11 are made of a Ti/Al/Ti/Au material, and the thicknesses of Ti, Al, Ti and Au in the Ti/Al/Ti/Au material are respectively 30nm, 120nm, 50nm and 100 nm.

The above description is only for the purpose of illustrating the technical solutions of the present invention and not for the purpose of limiting the same, and other modifications or equivalent replacements made by those of ordinary skill in the art to the technical solutions of the present invention should be covered within the scope of the claims of the present invention as long as they do not depart from the spirit and scope of the technical solutions of the present invention.

Claims

1. An InAlN-GaN HEMT device inserted with an insulating buried layer is characterized in that: the GaN-based buried-film transistor comprises a SiC substrate (1), a GaN nucleating layer (2), a GaN buffer layer (3), an insulating buried layer (4), an AlN insert layer (5), an InAlN barrier layer (6), a GaN cap layer (7), an SiN passivation layer (8), a grid (9), a source electrode (10) and a drain electrode (11), wherein the GaN nucleating layer (2) is arranged above the SiC substrate (1), the GaN buffer layer (3) is arranged above the GaN nucleating layer (2), the AlN insert layer (5) is arranged above the GaN buffer layer (3), the insulating buried layer (4) is grown inside the GaN buffer layer (3) and the AlN insert layer (5), the InAlN barrier layer (6) is grown on the upper surface of the AlN insert layer (5), the GaN cap layer (7) is arranged above the InAlN barrier layer (6), the SiN passivation layer (8) is arranged on the upper surface of the GaN cap layer (7), the source electrode (10) is formed on one side of the SiN, the gate (9) is located between the source (10) and the drain (11).

2. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the thickness of the GaN nucleating layer (2) is 30nm, and the thickness of the GaN buffer layer (3) is 3 mu m.

3. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the insulating buried layer (4) is located below the grid (9), the insulating buried layer (4) starts from the upper surface of the GaN nucleating layer (2), the insulating buried layer (4) stops at the lower surface of the InAlN barrier layer (6), and the length of the insulating buried layer (4) is consistent with that of the grid (9).

4. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the AlN insert layer (5) has a thickness of 5 nm.

5. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the thickness of the InAlN barrier layer (6) is 10 nm.

6. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the thickness of the GaN cap layer (7) is 2 nm.

7. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the thickness of the SiN passivation layer (8) is 150 nm.

8. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: a gate insulating layer (12) is formed below the gate (9), the gate insulating layer (12) starts from the upper surface of the GaN cap layer (7), the gate insulating layer (12) is stopped at the lower surface of the gate (9), and the length of the gate insulating layer (12) is consistent with that of the gate (9).

9. The InAlN-GaN HEMT device according to claim 8, inserted with a buried insulating layer, wherein: the gate insulating layer (12) is made of nitride, and the thickness of the gate insulating layer (12) is 100 nm.

10. The InAlN-GaN HEMT device inserted with the insulating buried layer according to claim 1, wherein: the grid electrode (9) is made of Ni/Au, the thickness of the Ni/Au material is 50nm and 300nm respectively, the source electrode (10) and the drain electrode (11) are in ohmic contact, the source electrode (10) and the drain electrode (11) are made of Ti/Al/Ti/Au, and the thickness of the Ti/Al/Ti/Au material is 30nm, 120nm, 50nm and 100nm respectively.