CN208622713U - 一种半导体封装结构 - Google Patents

一种半导体封装结构 Download PDF

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CN208622713U
CN208622713U CN201821531563.3U CN201821531563U CN208622713U CN 208622713 U CN208622713 U CN 208622713U CN 201821531563 U CN201821531563 U CN 201821531563U CN 208622713 U CN208622713 U CN 208622713U
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chip
convex block
face
packaging body
convex
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江子标
朱耀明
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Shenzhen Ambrose Power Semiconductor Co Ltd
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Shenzhen Ambrose Power Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型公开了一种半导体封装结构，包括封装体以及设置在封装体内的半导体互联结构；半导体互联结构包括若干第一凸块和第二凸块，第一凸块和第二凸块的底端伸出封装体底端面；所述第二凸块的顶端倒装焊接第一芯片，第二凸块的数量与第一芯片的焊点数量及位置均相对应；第一芯片的顶端面上粘附有第二芯片，第二芯片的焊点朝上设置；第二凸块的顶端与第二芯片的焊点之间通过金属布线层电连接，金属布线层裸露于封装体顶端面设置并通过塑封层覆盖。本实用新型结构简单、制作方便，具有较多的输入、输出端，并且封装结构中无需打线，在降低了制作难度的基础上，提高了芯片的可靠性，保证了封装中芯片的工作效率。

Description

一种半导体封装结构
技术领域
本实用新型涉及导体芯片封装技术领域，特别是一种半导体封装结构。
背景技术
随着电子工程的发展，人们对于集成电路（Integrated Circuit，简称IC）芯片小型化、轻量化及功能化的需求日渐增加，从最开始的单一组件的开发阶段，逐渐进入到了集结多个组件的系统开发阶段，与此同时在产品高效能及外观轻薄的要求下，不同功能的芯片开始迈向整合的阶段，因此封装技术的不断发展和突破，成为推动整合的力量之一。在半导体芯片封装技术领域中，半导体封装产业为了满足更高的需求，如高密度、低成本、高性能的封装，逐渐发展出各种不同型式的封装构造，目前，市面上常用的四方扁平无外引脚封装（QFN），在一定程度上满足了半导体封装对密度、成本以及性能的要求，方扁平无外引脚封装是通过设置在芯片底部的导线框架与外面接触，无需值放焊球，因此密度较高。
现有四方扁平无外引脚的封装结构如图1所示，将层叠后的半导体芯片A设置在底部导线框架B上，底部导线框架为能够承载最大的半导体芯片，通常设置为大于最下层半导体芯片的形状，而为了将芯片的电极引出，通常需要通过打线的方式将芯片的电极连接至底部导线框架同平面的其他周边导线框架C上，但是由于底部导线框架B较大，无法增加更多的周边导线框架C来满足引线需求；即使可以设置较多的周边导线框架C来满足引线需求，后续工艺中还会出现打线变得异常复杂的情况，当打线过长时，会出现电学信号传输缓慢的问题，另外打线间的复杂排列还容易发生短路现象，变向提高了设计的难度。
发明内容
本实用新型需要解决的技术问题是提供一种结构简单、能够保证传输效率并具有较多输入输出端的半导体封装结构。
为解决上述技术问题，本实用新型所采取的技术方案如下。
一种半导体封装结构，包括封装体以及设置在封装体内的半导体互联结构；所述半导体互联结构包括相互之间平行设置、且垂直于封装体底端面的若干第一凸块和第二凸块，第一凸块和第二凸块的底端伸出封装体底端面；所述第二凸块的顶端倒装焊接第一芯片，第二凸块的数量与第一芯片的焊点数量及位置均相对应；第一芯片的顶端面上粘附有第二芯片，第二芯片的焊点朝上设置；所述第二凸块的顶端与第二芯片的焊点之间通过金属布线层电连接，所述金属布线层裸露于封装体顶端面设置并通过塑封层覆盖。
上述一种半导体封装结构，所述第一凸块围设在所有第二凸块的外围。
由于采用了以上技术方案，本实用新型所取得技术进步如下。
本实用新型结构简单、制作方便，具有较多的输入、输出端，并且封装结构中无需打线，在降低了制作难度的基础上，提高了芯片的可靠性，保证了封装中芯片的工作效率。本实用新型中，第二凸块与金属布线之间直接连接，可提高芯片的传输速度以及电学性能。
附图说明
图1为传统四方扁平无外引脚封装结构的结构示意图；
图2为本实用新型的结构示意图。
其中：1.第一芯片，2.第二芯片，3.粘接层，4.焊球，5.第二凸块，6.金属布线层，7.第一凸块。
A.半导体芯片，B.底部导线框架，C.周边导线框架。
具体实施方式
下面将结合具体实施例对本实用新型进行进一步详细说明。
一种半导体封装结构，其结构如图2所示，包括封装体以及设置在封装体内的半导体互联结构。
半导体互联结构包括若干第一凸块7和第二凸块5，第一凸块7围设在所有第二凸块5的外围，且第一凸块7的高度高于第二凸块5的高度；第一凸块7和第二凸块5之间相互平行设置、且垂直于封装体底端面，第一凸块和第二凸块的底端伸出封装体底端面。
第二凸块的顶端倒装焊接第一芯片1，第二凸块5的数量与第一芯片的焊点数量及位置均相对应，以保证能够将第一芯片的所有焊点引出。第一芯片的顶端面上粘附有第二芯片2，第二芯片的焊点朝上设置；第二凸块的顶端与第二芯片的焊点之间通过金属布线层6实现电连接。
为方便批量生产，并保证芯片的工作效率，本实用新型中，第一凸块7的高度与第二凸块、第一芯片以及第二芯片的高度和相等，也即金属布线层平行于第一芯片和第二芯片设置。
本实用新型的制作时，首先在一个载片上形成多个第一凸块及多个第二凸块，其中第二凸块的高度比第一凸块的高度高；再将焊球成型的第一芯片倒装在第一凸块上，将第二芯片正面朝上通过粘接剂层叠于第一芯片上；其次，对整个结构进行填充，填充后进行CMP研磨，使第二凸块与第二芯片上的焊点同时出现，然后通过RDL金属布线层连接第二凸块与第二芯片上的焊点，再将露在外面的金属连接线进行塑封；最后将载片通过CNP研磨或刻蚀的方式使第一凸块和第二凸块的底端显现，便完成整个封装结构。

Claims (2)

1.一种半导体封装结构，其特征在于：包括封装体以及设置在封装体内的半导体互联结构；所述半导体互联结构包括相互之间平行设置、且垂直于封装体底端面的若干第一凸块（7）和第二凸块（5），第一凸块和第二凸块的底端伸出封装体底端面；所述第二凸块的顶端倒装焊接第一芯片（1），第二凸块（5）的数量与第一芯片的焊点数量及位置均相对应；第一芯片的顶端面上粘附有第二芯片（2），第二芯片的焊点朝上设置；所述第二凸块的顶端与第二芯片的焊点之间通过金属布线层（6）电连接，所述金属布线层裸露于封装体顶端面设置并通过塑封层覆盖。
2.根据权利要求1所述的一种半导体封装结构，其特征在于：所述第一凸块（7）围设在所有第二凸块（5）的外围。
CN201821531563.3U 2018-09-19 2018-09-19 一种半导体封装结构 Expired - Fee Related CN208622713U (zh)

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