CN208596700U

CN208596700U - Semiconductor chip for light emitting diode

Info

Publication number: CN208596700U
Application number: CN201821130030.4U
Authority: CN
Inventors: 邬新根; 李俊贤; 刘英策; 魏振东; 周弘毅
Original assignee: Xiamen Changelight Co Ltd
Current assignee: Xiamen Changelight Co Ltd
Priority date: 2018-07-17
Filing date: 2018-07-17
Publication date: 2019-03-12
Anticipated expiration: 2028-07-17

Abstract

The utility model discloses the semiconductor chips that one is used for light emitting diode, it includes an extension unit, an at least current barrier layer, one transparency conducting layer, one N-type electrode and a P-type electrode, wherein the current barrier layer is laminated in the n type semiconductor layer of the extension unit, the transparency conducting layer is laminated in the p type semiconductor layer of the extension unit in a manner of coating the current barrier layer, and a column perforation of the transparency conducting layer corresponds respectively to the different location of the current barrier layer, and perforation described at least one of described perforation of a column is different with the adjacent perforation, the N-type electrode is laminated in the n type semiconductor layer, the P-type electrode is laminated in the transparency conducting layer, and each p-type of the P-type electrode is interdigital to be respectively formed in and is maintained at described in each of described transparency conducting layer Perforation.

Description

Semiconductor chip for light emitting diode

Technical field

The utility model relates to a LED chip, in particular to one semiconductor chip and its manufacture for light emitting diode Method.

Background technique

The packed LED chip of the prior art is come usually using lithography step to both structures by two kinds of structures, industry Packed LED chip is named, that is, three structure packed LED chips and five structure packed LED chips.That is, three Structure packed LED chip uses three lithography steps during being produced, and five structure packed LED chips are being produced Five lithography steps are used in the process, it is generally the case that the lithography step of five structure packed LED chips can also be by five light It carves step and is reduced to four lithography steps.For three structure packed LED chips, process include Mesa process (step, Refer in the way of dry etching in the process of epitaxial wafer surface production N-type layer exposed region), ITO process (refers to Bright conductive film layer figure process) and PV&Pad process (refer to that passivation layer and electrode use identical procedure photoetching figure The process that shape is made)；For five structure packed LED chips, process includes Mesa process, CB process (current blocking The production process of layer), ITO process and PV&Pad process.It is said from structure, three structure packed LED chips and five Structure packed LED chip no significant difference, from process for, five structure packed LED chips are than five structure forward LED cores The more structures of current barrier layer (CB) of piece, are the current barrier layer of P-type electrode, in order to prevent packed LED chip From P-type electrode inject current convergence the underface of P-type electrode and caused by current-crowding effect.Certainly, current barrier layer The increase of structure is to increase packed LED chip processing procedure cost, is based on this, small-power chip commonly used in the trade, display are with chip Three structure packed LED chips, and high-power chip, illumination chip are five structure packed LED chips.

From the point of view of the PN diode positive and negative resistance of five structure packed LED chips composition, P-type electrode electric current flows through metal Electrode is to inject transparency conducting layer after being extended by metal electrode, then by injecting p-type gallium nitride layer after transparency conducting layer, most Enter active layer afterwards；And N-type electrode resistance group becomes electronics by metal electrode with injection N-type nitridation after being extended by metal electrode Gallium layer, finally enters active area, in active area recombination luminescence.Electricity from the point of view of entire current course, relative to semiconductor layer The conductivity of conductance, metal electrode is higher, and therefore, the electric current on P-type electrode surface has the tendency that being gathered in P interdigital electrode end. From the point of view of the curve of the characteristics of luminescence of five structure packed LED chips, with the rising of current density, brightness has under rising then The trend of drop, there are saturation current densities, this will affect the luminous efficiency of five structure packed LED chips.Ideal high brightness Luminescence chip structure enables to the current density of packed LED chip to maintain the higher region of luminous efficiency, however, current Five structure packed LED chips cannot achieve.

Utility model content

One of the utility model is designed to provide a semiconductor chip for light emitting diode, wherein described partly lead Body chip provides a p type semiconductor layer, can be evenly distributed over by the electric current for injecting the p type semiconductor layer, thus favorably In the overall brightness for promoting the semiconductor chip.

One of the utility model is designed to provide a semiconductor chip for light emitting diode, wherein described partly lead Body chip provides the transparency conducting layer for being laminated in the p type semiconductor layer and the p-type for being laminated in transparency conducting layer electricity Pole, wherein the electric current injected through the P-type electrode can be uniformly implanted the p-type after the diffusion of the transparency conducting layer Semiconductor layer, to be conducive to be promoted the overall brightness of the semiconductor chip.One of the utility model is designed to provide One is used for the semiconductor chip of light emitting diode, wherein a P-type electrode offer at least column p-type is interdigital, wherein a column P The interdigital length direction along the semiconductor chip of type arranges and is inserted into the inside of the transparency conducting layer, in this way Mode, electric current can be injected the transparency conducting layer through the P-type electrode from the surface of the transparency conducting layer and inside, this The mode of sample is conducive to be uniformly injected into electric current to the p type semiconductor layer.

One of the utility model is designed to provide a semiconductor chip for light emitting diode, wherein the p-type Electrode provides a P-type electrode pad and at least P-type electrode extension item, wherein the P-type electrode pad is formed in and described partly leads The first end of body chip, the P-type electrode extension item is from the P-type electrode pad to the second end of the semiconductor chip Direction extends, and each p-type during a column p-type is interdigital is interdigital to be formed in the P-type electrode extension item spaced reciprocally respectively, And p-type described in a column p-type is at least one of interdigital is interdigital different with the interdigital shape or size of the adjacent p-type, In this way, being conducive to the electric current injected through the P-type electrode can be equal after the diffusion of the transparency conducting layer The p type semiconductor layer is injected evenly.

One of the utility model is designed to provide a semiconductor chip for light emitting diode, wherein described in a column Each of the interdigital interdigital shape of the p-type of p-type extends a gradual change along the P-type electrode, in this way, favorably The p-type can be uniformly implanted after the diffusion of the transparency conducting layer in the electric current injected through the P-type electrode partly to lead Body layer.

One of the utility model is designed to provide a semiconductor chip for light emitting diode, wherein described in a column Each of the interdigital interdigital size of the p-type of p-type extends a gradual change along the P-type electrode, in this way, favorably The p-type can be uniformly implanted after the diffusion of the transparency conducting layer in the electric current injected through the P-type electrode partly to lead Body layer.

One of the utility model is designed to provide a semiconductor chip for light emitting diode, wherein described in a column Spacing between the two neighboring p-type during p-type is interdigital is interdigital extends a gradual change along the P-type electrode, in this way Mode, institute can be uniformly implanted after the diffusion of the transparency conducting layer by being conducive to the electric current injected through the P-type electrode State p type semiconductor layer.

According to the one aspect of the utility model, the utility model provides a semiconductor chip for being used for light emitting diode, Include:

One extension unit, wherein the extension unit include the substrate stacked gradually, it is a n type semiconductor layer, one active Area and a p type semiconductor layer and with extending to the n type semiconductor layer through the active area from the p type semiconductor layer At least exposed portion of semiconductor；

An at least current barrier layer, wherein the current barrier layer is laminated in the p type semiconductor layer；

One transparency conducting layer, wherein the transparency conducting layer have at least one column perforation, wherein the transparency conducting layer with The mode for coating the current barrier layer is laminated in the p type semiconductor layer, and the perforation of the transparency conducting layer corresponds to The current barrier layer, and perforation described at least one of described perforation of a column is different from the adjacent perforation；And

One electrode group, wherein the electrode group includes being laminated in a N-type electrode of the n type semiconductor layer and being laminated in institute State a P-type electrode of transparency conducting layer, wherein the N-type electrode include be formed in the semiconductor chip the second end one N-type electrode pad and at least N-type electricity extended from the N-type electrode pad to the second end direction of the semiconductor chip Pole extend item, wherein the P-type electrode include be formed in the first end of the semiconductor chip a P-type electrode pad and from At least P-type electrode that the P-type electrode pad extends to the second end direction of the semiconductor chip extends item, wherein institute Stating P-type electrode extension item has a column p-type interdigital, wherein the p-type is interdigital to be formed in and be maintained at the transparency conducting layer The perforation.

One embodiment according to the present utility model, the size of each of column perforation perforation is from described half The first end of conductor chip is gradually increased to the second end direction, thus each of the interdigital P of a column p-type The interdigital size of type is reversely gradually increased from the first end of the semiconductor chip to the second end.

One embodiment according to the present utility model, the size of each of column perforation perforation is from described half The first end of conductor chip is gradually reduced to the second end direction, thus each of the interdigital P of a column p-type The interdigital size of type is reversely gradually reduced from the first end of the semiconductor chip to the second end.

One embodiment according to the present utility model, one arranges the spacing between the two neighboring perforation in the perforation It is gradually increased from the first end of the semiconductor chip to the second end direction, thus during a column p-type is interdigital Spacing between the two neighboring p-type is interdigital from the first end of the semiconductor chip to the second end direction gradually Increase.

One embodiment according to the present utility model, one arranges the spacing between the two neighboring perforation in the perforation It is gradually reduced from the first end of the semiconductor chip to the second end direction, thus during a column p-type is interdigital Spacing between the two neighboring p-type is interdigital from the first end of the semiconductor chip to the second end direction gradually Reduce.

One embodiment according to the present utility model, the N-type electrode include that the N-type electrode extends item, the N Type electrode extension item extends at the middle part of the semiconductor chip along the length direction of the semiconductor chip, wherein the P Type electrode includes that two P-type electrodes extend item, and two P-type electrode extension items are in symmetrical mode described half The edge of conductor chip extends along the length direction of the semiconductor chip, wherein N-type electrode extension item is maintained at Between two P-type electrode extension items.

One embodiment according to the present utility model, the N-type electrode include that two N-type electrodes extend items, and two The N-type electrode extension exposed portion of item prolongs at the middle part of the semiconductor chip along the length direction of the semiconductor chip It stretches, wherein fettered P-type electrode includes that three P-type electrodes extend items, the extension article of respectively one first P-type electrode, one the Two P-type electrodes extend item and a third P-type electrode extends item, the first P-type electrode extension item and the third P-type electrode Item is extended to extend at the edge of the semiconductor chip along the length direction of the semiconductor chip in symmetrical mode, The second P-type electrode extension item extends at the middle part of the semiconductor chip along the length direction of the semiconductor chip, One of them described N-type electrode extension item is maintained at the first P-type electrode extension item and second P-type electrode extension item Between, another described N-type electrode extension item is maintained at the second P-type electrode extension item and the third P-type electrode expands It opens up between item.

One embodiment according to the present utility model, the N-type electrode include that two N-type electrodes extend items, and two The N-type electrode extension item is in symmetrical mode at the edge of the semiconductor chip along the length of the semiconductor chip It spends direction to extend, wherein the P-type electrode includes that the P-type electrode extends item, the P-type electrode extension item is described half The middle part of conductor chip extends along the length direction of the P-type electrode, wherein P-type electrode extension item is maintained at two Between the N-type electrode extension item.

One embodiment according to the present utility model, the N-type electrode include that three N-type electrodes extend item, respectively Item is extended for one first N-type electrode, one second N-type electrode extends item and a third N-type electrode extends item, first N-type Electrode extension item and the third N-type electrode extension item in symmetrical mode at the edge of the semiconductor chip along institute The length direction for stating semiconductor chip extends, and the second N-type electrode extension item is at the middle part of the semiconductor chip along institute The length direction for stating semiconductor chip extends, wherein the P-type electrode includes that two P-type electrodes extend item, two P Type electrode extension item is in symmetrical mode at the middle part of the semiconductor chip along the length side of the semiconductor chip Shape extends, one of them described P-type electrode extension item is maintained at the first N-type electrode extension item and second N-type electricity Pole extends between item, another described P-type electrode extension article is maintained at the second N-type electrode extension article and the 3rd N Between type electrode extension item.

One embodiment according to the present utility model, the n type semiconductor layer of the extension unit are exposed on institute The surface for stating semiconductor bare portion is laminated at least one described current barrier layer, wherein N-type electrode cladding is laminated in institute State the current barrier layer of n type semiconductor layer.

One embodiment according to the present utility model is laminated in the current barrier layer of the n type semiconductor layer in item It is band-like, extend along the length direction of the semiconductor chip.

One embodiment according to the present utility model is laminated in the number of the current barrier layer of the n type semiconductor layer Amount be it is multiple, these described current barrier layers it is stripped in a row along the semiconductor chip length direction extend, and And there is spaced slot between the two neighboring current barrier layer.

One embodiment according to the present utility model, the semiconductor chip further comprise a passivation layer, wherein described Passivation layer has a first through hole and one second through-hole, wherein the passivation layer is to coat the N-type electrode and the P-type electrode Mode be laminated in the p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer is corresponding Correspond to the P-type electrode in second through-hole of the N-type electrode, the passivation layer.

Detailed description of the invention

Figure 1A is illustrated according to the vertical view of the manufacturing step of the semiconductor chip of first preferred embodiment of the utility model Figure.Figure 1B is the schematic cross-sectional view according to the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model.

Fig. 2A is illustrated according to the section view of the manufacturing step of the semiconductor chip of second preferred embodiment of the utility model Figure.

Fig. 2 B is shown according to the section view of the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model It is intended to.

Fig. 3 A is illustrated according to the section view of the manufacturing step of the semiconductor chip of the third preferred embodiment of the utility model Figure.

Fig. 3 B is shown according to the section view of the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model It is intended to.

Fig. 4 A is illustrated according to the section view of the manufacturing step of the semiconductor chip of the 4th preferred embodiment of the utility model Figure.

Fig. 4 B is shown according to the section view of the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model It is intended to.

Fig. 5 A is illustrated according to the section view of the manufacturing step of the semiconductor chip of the 5th preferred embodiment of the utility model Figure.Fig. 5 B is the schematic cross-sectional view according to the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model.

Fig. 6 A is illustrated according to the section view of the manufacturing step of the semiconductor chip of the 6th preferred embodiment of the utility model Figure.

Fig. 6 B is shown according to the section view of the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model It is intended to.

Fig. 7 A is illustrated according to the section view of the manufacturing step of the semiconductor chip of the 7th preferred embodiment of the utility model Figure.

Fig. 7 B is shown according to the section view of the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model It is intended to.

Fig. 8 A is illustrated according to the section view of the manufacturing step of the semiconductor chip of the 8th preferred embodiment of the utility model Figure.

Fig. 8 B is shown according to the section view of the manufacturing step of the semiconductor chip of the above-mentioned preferred embodiment of the utility model It is intended to.

Fig. 9 is the manufacturing step schematic diagram according to the semiconductor chip of the 9th preferred embodiment of the utility model.

Figure 10 is the manufacturing step schematic diagram according to the semiconductor chip of the tenth preferred embodiment of the utility model.

Figure 11 is the manufacturing step schematic diagram according to the semiconductor chip of the 11st preferred embodiment of the utility model.

Figure 12 is the manufacturing step schematic diagram according to the semiconductor chip of the 12nd preferred embodiment of the utility model.

Specific embodiment

It is described below for disclosing the utility model so that those skilled in the art can be realized the utility model.It retouches below Preferred embodiment in stating is only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It is retouched following The basic principle of the utility model defined in stating can be applied to other embodiments, deformation scheme, improvement project, etc. Tongfangs The other technologies scheme of case and the spirit and scope without departing from the utility model.

It will be understood by those skilled in the art that in the exposure of the utility model, term " longitudinal direction ", " transverse direction ", "upper", The orientation of the instructions such as "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" or position are closed System is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of describing the present invention and simplifying the description, without It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore on Stating term should not be understood as limiting the present invention.

It is understood that term " one " is interpreted as " at least one " or " one or more ", i.e., in one embodiment, The quantity of one element can be one, and in a further embodiment, the quantity of the element can be it is multiple, term " one " is no It can be interpreted as the limitation to quantity.

With reference to the attached drawing 1A and Figure 1B of the Figure of description of the utility model, according to a preferred embodiment of the utility model One semiconductor chip for being used for light emitting diode is disclosed for and is set forth in following description, wherein the semiconductor chip Including an extension unit 10, at least a current barrier layer 20, a transparency conducting layer 30 and an electrode group 40.

Specifically, the extension unit 10 includes a substrate 11, a n type semiconductor layer 12, an active area 13 and a P Type semiconductor layer 14, wherein the n type semiconductor layer 12 is grown from the substrate 11, so that the n type semiconductor layer 12 is laminated In the substrate 11, wherein the active area 13 is grown from the n type semiconductor layer 12, so that the active area 13 is laminated in institute N type semiconductor layer 12 is stated, wherein the p type semiconductor layer 14 is grown from the active area 13, so that the p type semiconductor layer 14 It is laminated in the active area 13.

It is noted that the semiconductor of the type of the substrate 11 of the extension unit 10 in the utility model It is unrestricted in chip, such as the substrate 11 can be but not limited to Sapphire Substrate, silicon substrate etc..In addition, the N-type half Conductor layer 12 and the type of the p type semiconductor layer 14 can also be unrestricted in the semiconductor chip of the utility model System, such as the n type semiconductor layer 12 can be n type gallium nitride layer, and correspondingly, the p type semiconductor layer 14 can be p-type nitrogen Change gallium layer.

With reference to attached drawing 1A and Figure 1B, the extension unit 10 has at least exposed portion 15 of semiconductor, wherein described partly lead The exposed portion 15 of body extends to the n type semiconductor layer 12 through the active area 13 from the p type semiconductor layer 14, described in exposure N type semiconductor layer 12.That is, a part of surface of the n type semiconductor layer 12 is exposed on the semiconductor bare portion 15。

In the semiconductor chip of the utility model, it is possible, firstly, to utilize metallo-organic compound chemical vapor deposition Described in shallow lake equipment (Metal-organic Chemical Vapor Deposition, MOCVD) is successively grown from the substrate 11 N type semiconductor layer 12, the active area 13 and the p type semiconductor layer 14, the substrate 11 stacked gradually, the N Type semiconductor layer 12, the active area 13 and the p type semiconductor layer 14.Secondly, making Mesa figure using photoresist.So Afterwards, using inductively coupled plasma (Inductively Coupled Plasma, ICP) successively to the p type semiconductor layer 14 and the active area 13 carry out dry etching, with formed extend to institute through the active area 13 from the p type semiconductor layer 14 The semiconductor bare portion 15 of n type semiconductor layer 12 is stated, and the n type semiconductor layer 12 is made to be exposed to the semiconductor Exposed portion 15.

In another preferable examples of the semiconductor chip of the utility model, it can be used inductively equal in vitro Son further etches the n type semiconductor layer 12, extends to institute through the active area 13 from the p type semiconductor layer 14 to be formed The semiconductor bare portion 15 of n type semiconductor layer 12 is stated, and the n type semiconductor layer 12 is made to be exposed to the semiconductor Exposed portion 15.That is, in this preferable examples of the semiconductor chip of the utility model, the N-type semiconductor The thickness corresponding to the semiconductor bare portion 15 of layer 12 is less than the thickness of the other parts of the n type semiconductor layer 12 Size.

Preferably, the depth dimensions range in the semiconductor bare portion 15 of the extension unit 10 is 0.7 μm to 3 μm (including 0.7 μm and 3 μm).Using inductively coupled plasma to the p type semiconductor layer 14, the active area 13 and described It is Cl2 (chlorine), BCl3 (boron chloride) and Ar (argon gas) that n type semiconductor layer 12, which carries out the gas used when dry etching,.? The p type semiconductor layer 14, the active area 13 and the n type semiconductor layer 12 are done using inductively coupled plasma Method etches after forming the semiconductor bare portion 15, the photoresist is removed, to obtain the extension unit 10.Described in removal The mode of photoresist is unrestricted in the semiconductor chip of the utility model, such as can be through but not limited to removing glue The mode removed photoresist removes the photoresist.

Further, with reference to attached drawing 1A and Figure 1B, the semiconductor chip has a first end 101 and corresponds to described One the second end 102 of first end 101.With continued reference to attached drawing 1A and Figure 1B, the semiconductor bare portion 15 has N-type electricity The exposed portion 151 of pole pad and two N-type electrodes extend the exposed portion 152 of item, wherein the N-type electrode in the semiconductor bare portion 15 The exposed portion 151 of pad is formed in the second end 102 of the semiconductor chip, two institutes in the semiconductor bare portion 15 State N-type electrode extension the exposed portion 152 of item in symmetrical mode at the middle part of the semiconductor chip along the semiconductor The first end 101 direction of the length direction of chip from the exposed portion 151 of the N-type electrode pad to the semiconductor chip Extend.The N-type electrode extension of two of the semiconductor bare portion 15 exposed portion 152 of item is respectively communicated with the N-type electrode weldering The exposed portion 151 of disk.

It is understood that the exposed portion 151 of the N-type electrode pad in the semiconductor bare portion 15 and two N The exposed portion 152 of type electrode extension item by with along with etch process formed, and the semiconductor bare portion 15 the N-type electricity The exposed portion 151 of pole pad and two N-type electrodes extension exposed portions 152 of item described in the p type semiconductor layer 14 warp from having Source region 13 extends to the n type semiconductor layer 12, with a part of surface of the exposure n type semiconductor layer 12 in the semiconductor The exposed portion 151 of the N-type electrode pad in exposed portion 15 and two N-type electrodes extend the exposed portion 152 of item.

With reference to attached drawing 1A and Figure 1B, it is laminated described at least one in the p type semiconductor layer 14 of the extension unit 10 Current barrier layer 20.Preferably, the quantity of the current barrier layer 20 is three, and three current barrier layers 20 are in Ribbon, wherein these three described current barrier layers 20 are successively defined as one first current barrier layer 20a, the resistance of one second electric current A barrier 20b and third current barrier layer 20c, wherein the first current barrier layer 20a, second current barrier layer The 20b and third current barrier layer 20c respectively along the semiconductor chip length direction from the semiconductor chip The first end 101 extends to 102 direction of the second end.

The N-type electrode extension of one of the semiconductor bare portion 15 exposed portion 152 of item is maintained at first electricity Between flow barrier 20a and the second current barrier layer 20b, another N-type electrode in the semiconductor bare portion 15 The extension exposed portion 152 of item is maintained between the second current barrier layer 20b and the third current barrier layer 20c.It is preferred that Ground, the first current barrier layer 20a and the third current barrier layer 20c are in symmetrical mode in the semiconductor core The edge of piece is along the length direction of the semiconductor chip from the first end 101 of the semiconductor chip to described Two ends, 102 direction extends, and the second current barrier layer 20b is to be maintained at the first current barrier layer 20a and described Mode between third current barrier layer 20c is at the middle part of the semiconductor chip along the length direction of the semiconductor chip Extend from the first end 101 of the semiconductor chip to 102 direction of the second end.

The mode that the current barrier layer 20 is laminated in the p type semiconductor layer 14 of the extension unit 10 is practical at this It is unrestricted in the novel semiconductor chip.For example, one in the semiconductor chip of the utility model is specifically shown In example, firstly, utilizing vapour deposition process (the Plasma Enhanced Chemical Vapor of plasma enhanced chemical Deposition, PECVD) precipitating one layer of SiO2 (silica) Yu Suoshu extension unit 10 the p type semiconductor layer 14, The thickness range of SiO2 is 500 angstroms to 10000 angstroms (including 500 angstroms and 10000 angstroms), and the reaction gas used is SiH4 (silicon Alkane), N2O (nitrous oxide) and N2 (nitrogen).Secondly, make the structure of the current barrier layer 20 by lithography using positive photoresist, Described in photoresist thickness range be 0.5 μm to 5 μm (including 0.5 μm and 5 μm).Then, it is lost using the mode of wet etching SiO2 is carved to make the figure of the current barrier layer 20, wherein etching solution is the mixed solution in hydrofluoric acid and ammonium fluoride.Most Afterwards, the photoresist is removed after the etch is completed, and the p type semiconductor layer 14 of the extension unit 10 is laminated in formation The current barrier layer 20.

Preferably, the current barrier layer 20 can also be laminated in the n type semiconductor layer 12 of the extension unit 10. For example, the current barrier layer 20 can be formed in the N-type electrode extension in the semiconductor bare portion 15 with reference to attached drawing 1A The exposed portion 152 of item, so that the current barrier layer 20 is laminated in the n type semiconductor layer 12 of the extension unit 10.More Preferably, the adjacent current barrier layer 20 for being laminated in the n type semiconductor layer 12 is spaced apart from each other, and these described electric currents Barrier layer 20 is naked along the N-type electrode extension item in the semiconductor bare portion 15 with stripped mode to be spaced apart from each other The extending direction in dew portion 152 extends.

It is noted that although in this preferable examples of the semiconductor chip shown in attached drawing 1A and Figure 1B with The quantity of the current barrier layer 20 of the n type semiconductor layer 12 of the extension unit 10 is laminated in as multiple and adjacent institute Stating has spaced slot between current barrier layer 20, it will be appreciated that those skilled in the art that attached drawing 1A and Figure 1B are shown The semiconductor chip it is merely illustrative, that is, in other possible examples of the semiconductor chip, be laminated in the N-type The quantity of the current barrier layer 20 of semiconductor layer 12 can be one, and the current barrier layer 20 is stripped, with Make the extending direction of the current barrier layer 20 and the N-type electrode extension item of development length and the semiconductor bare portion 15 The extending direction in exposed portion 152 is consistent with development length.

With reference to attached drawing 1A and Figure 1B, firstly, deposition indium oxide layer tin layers (Indium Tin Oxides, ITO) Yu Suoshu The p type semiconductor layer 14 of extension unit 10, wherein the indium tin oxide layer is electrically connected to the p type semiconductor layer 14.Its It is secondary, alloy treatment is carried out to the indium tin oxide layer.Preferably, the mode of alloy treatment is carried out to the indium tin oxide layer at this It is unrestricted in the semiconductor chip of utility model, quick anneal oven or alloy furnace tubes by adopting can be used for example to the oxygen Change indium tin and carries out alloy treatment.Then, figure photoetching is carried out to the indium tin oxide layer using positive photoresist, is utilized after the completion of photoetching The mode of wet etching etches the indium tin oxide layer, and described transparent lead is obtained after the photoresist to complete and remove in etching Electric layer 30, wherein the transparency conducting layer 30 has at least one column perforation 31, wherein each of described perforation 31 described in each column The perforation 31 corresponds respectively to the different location of the current barrier layer 20, so that the current barrier layer 20 is exposed on institute State these described perforation 31 of transparency conducting layer 30.Preferably, the indium tin oxide layer is being etched in the way of wet etching When the etching solution that uses be hydrochloric acid and iron chloride mixed solution.

Preferably, with reference to attached drawing 1A, the transparency conducting layer 30 has the perforation 31 of three column, wherein the electrically conducting transparent Each of the column perforation 31 of layer 30 perforation 31 corresponds respectively to the different positions of the first current barrier layer 20a It sets, each of described perforation 31 of another column of the transparency conducting layer 30 perforation 31 corresponds respectively to second electric current The different location of barrier layer 20b, the transparency conducting layer 30 further arrange each of described perforation 31 31 difference of perforation Different location corresponding to the third current barrier layer 20c.In this of the semiconductor chip shown in attached drawing 1A and Figure 1B In a preferable examples, perforation 31 described at least one of described perforation 31 of at least one column and the adjacent perforation 31 are different, example Such as, in this preferable examples of the semiconductor chip of the utility model, at least one arranges at least one in the perforation 31 A perforation 31 is different with the size of the adjacent perforation 31.Certainly, it will be apparent to a skilled person that in this reality In other preferable examples with the novel semiconductor chip, perforate described at least one of described perforation 31 of at least one column 31 and the adjacent perforation 31 shape can different or shape and size can be different.

Preferably, in this preferable examples of the semiconductor chip shown in attached drawing 1A and Figure 1B, at least one column institute The size of each of perforation 31 perforation 31 is stated from the first end 101 of the semiconductor chip to the second end 102 direction of portion is incremented by successively.That is, the perforation 31 of the second end 102 of the close semiconductor chip Size is greater than the size of the perforation 31 of the first end 101 close to the semiconductor chip.

With reference to attached drawing 1A and Figure 1B, firstly, going out the electrode using negative-working photoresist on the surface of the transparency conducting layer 30 The figure of one N-type electrode 41 of group 40 and the figure of a P-type electrode 42.Secondly, by vapor deposition or sputter in the way of deposited metal Electrode layer.Then, the remaining photoresist of extra metal layer and removal is removed, by the way of removing to form the electrode group 40 N-type electrode 41 and the P-type electrode 42.

Specifically, the N-type electrode 41 includes a N-type electrode pad 411 and is electrically connected to the N-type electrode pad 411 two N-type electrodes extend item 412, wherein the N-type electrode pad 411 of the N-type electrode 41 is formed in the extension list Member 10 the semiconductor bare portion 15 the exposed portion 151 of the N-type electrode pad so that 411 layers of the N-type electrode pad It is laminated on and is electrically connected to the n type semiconductor layer 12 of the extension unit 10, wherein the N-type electricity of the N-type electrode 41 Pole extension item 412 is formed in the N-type electrode extension exposed portion of item in the semiconductor bare portion 15 of the extension unit 10 152, so that N-type electrode extension item 412 is laminated in and is electrically connected to the n type semiconductor layer of the extension unit 10 12.It is understood that the N-type electrode extension item 412 is filled in the adjacent electricity for being laminated in the n type semiconductor layer 12 Spaced slot between flow barrier 20.Preferably, two N-type electrode extension items 412 are in symmetrical mode in institute It is partly led along the length direction of the semiconductor chip from the N-type electrode pad 411 to described at the middle part for stating semiconductor chip 101 direction of the first end of body chip extends.

Correspondingly, the P-type electrode 42 includes a P-type electrode pad 421 and is electrically connected to the P-type electrode pad 421 Three P-type electrodes extend item 422, wherein a P-type electrode extension item 422 is defined as one first P-type electrode extension item 422a, another P-type electrode extension item 422 are defined as one second P-type electrode extension 422b, p-type described in another item Electrode extension item 423 is defined as third P-type electrode extension 422c.The P-type electrode pad of the P-type electrode 42 421 and every P-type electrode extension item 422 be laminated in the transparency conducting layer 30, wherein the P-type electrode 42 is described P-type electrode pad 421 is formed in the first end 101 of the semiconductor chip, every P of the P-type electrode 42 Type electrode extension item 422 is partly led respectively along the length direction of the semiconductor chip from the P-type electrode pad 421 from described The first end 101 of body chip extends to 102 direction of the second end.In the short transverse of the chip, the p-type First P-type electrode extension 422a and the first current barrier layer 20a of electrode 42 overlaps, so that described It is described that the p-type interdigital 4220 of first P-type electrode extension 422a is formed in and is maintained at each of described transparency conducting layer 30 Perforation 31；Second P-type electrode extension 422b of the P-type electrode 42 and the second current barrier layer 20b phase mutual respect Close so that second P-type electrode extension 422b the p-type it is interdigital 4220 refer to be formed in and be maintained at it is described The perforation 31 of each of bright conductive layer 30；The third P-type electrode extension 422c of the P-type electrode 42 and the third Current barrier layer 20c overlaps, so that the p-type interdigital 4220 of first P-type electrode extension 422a is formed In be maintained at each of described transparency conducting layer 30 it is described perforation 31.

That is, first P-type electrode extension 422a of the P-type electrode 42 and the third P-type electrode expand A 422c is opened up in symmetrical mode respectively at the edge of the semiconductor chip along the length side of the semiconductor chip Extend to 102 direction of the second end from the P-type electrode pad 421 to the semiconductor chip, the P-type electrode 42 Second P-type electrode extension 422b at the middle part of the semiconductor chip along the length direction of the semiconductor chip 10 direction of the second end from from the P-type electrode pad 421 to the semiconductor chip extends.The N-type electrode 41 One N-type electrode extension item 412 is maintained at first P-type electrode extension 422a and the institute of the P-type electrode 42 It states between the second P-type electrode extension 422b, another described N-type electrode extension item 412 is maintained at second P-type electrode It extends between a 422b and third P-type electrode extension 422c.

Each of the P-type electrode 42 P-type electrode extension item 422 is respectively provided with the column p-type interdigital 4220, That is, the first P-type electrode extension 422a has a column p-type interdigital 4220, second P-type electrode extends a 422b With a column p-type interdigital 4220, the third P-type electrode extension 422c has a column p-type interdigital 4220.

During the P-type electrode 42 is laminated in transparency conducting layer 30, described the first of the P-type electrode 42 P-type electrode extension 422a one column the p-type interdigital each of 4220 p-type interdigital 4220 be formed simultaneously in protected It holds in each of the column perforation 31 of the transparency conducting layer 30 perforation 31, because the one of the transparency conducting layer 30 The size of the perforation each of 31 perforation 31 is arranged from the first end 101 of the semiconductor chip to described second 102 direction of end is incremented by successively, thus a column p-type interdigital each of 4220 of first P-type electrode extension 422a The size of the p-type interdigital 4220 from the first end 101 of the semiconductor chip to 102 direction of the second end according to It is secondary to be incremented by.That is, close to the p-type interdigital 4220 of the P-type electrode pad 411 in a column p-type interdigital 4220 Size be less than the size of the p-type interdigital 4220 far from the P-type electrode pad 411, such mode is conducive to electric current It is uniformly distributed into the p type semiconductor layer 14.

During the P-type electrode 42 is laminated in transparency conducting layer 30, described the second of the P-type electrode 42 P-type electrode extension 422b one column the p-type interdigital each of 4220 p-type interdigital 4220 be formed simultaneously in protected It holds in each of the column perforation 31 of the transparency conducting layer 30 perforation 31, because the one of the transparency conducting layer 30 The size of the perforation each of 31 perforation 31 is arranged from the first end 101 of the semiconductor chip to described second 102 direction of end is incremented by successively, thus a column p-type interdigital each of 4220 of second P-type electrode extension 422b The size of the p-type interdigital 4220 from the first end 101 of the semiconductor chip to 102 direction of the second end according to It is secondary to be incremented by.That is, close to the p-type interdigital 4220 of the P-type electrode pad 411 in a column p-type interdigital 4220 Size be less than the size of the p-type interdigital 4220 far from the P-type electrode pad 411, such mode is conducive to electric current It is uniformly distributed into the p type semiconductor layer 14.

During the P-type electrode 42 is laminated in transparency conducting layer 30, the third of the P-type electrode 42 P-type electrode extension 422c one column the p-type interdigital each of 4220 p-type interdigital 4220 be formed simultaneously in protected It holds in each of the column perforation 31 of the transparency conducting layer 30 p-type interdigital 4220, because of the transparency conducting layer The size of each of 30 column perforation 31 perforation 31 is from the first end 101 of the semiconductor chip to institute State that 102 direction of the second end is incremented by successively, thus a column p-type interdigital 4220 of third P-type electrode extension 422c Each of the p-type interdigital 4220 size from the first end 101 of the semiconductor chip to the second end 102 Direction is incremented by successively.That is, the p-type in a column p-type interdigital 4220 close to the P-type electrode pad 411 is pitched Refer to that 4220 size is less than the size of the p-type interdigital 4220 far from the P-type electrode pad 411, such mode is advantageous The p type semiconductor layer 14 is uniformly distributed into electric current.

Preferably, with reference to attached drawing 1A and Figure 1B, the semiconductor chip further comprises a passivation layer 50, wherein described blunt Change layer 50 and be laminated in the p type semiconductor layer 14 of the extension unit 10, and the passivation layer 50 coats described transparent lead The N-type electrode 41 and the P-type electrode 42 of electric layer 30 and the electrode group 40, wherein the passivation layer 50 has at least One first through hole 51 and at least one second through-hole 52, wherein the first through hole 51 of the passivation layer 50 corresponds to the electrode The N-type electrode pad 411 of the N-type electrode 41 of group 40, so that the N-type electrode pad 411 is exposed on described the One through-hole 41, correspondingly, second through-hole 52 of the passivation layer 50 correspond to the P-type electrode 42 of the electrode group 40 The P-type electrode pad 421 so that the P-type electrode pad 421 is exposed on second through-hole 42.

Specifically, with reference to attached drawing 1A and Figure 1B, firstly, utilizing the vapour deposition process of plasma enhanced chemical (Plasma Enhanced Chemical Vapor Deposition, PECVD) precipitates one layer of SiO2 (silica) Yu Suoshu The p type semiconductor layer 14 of extension unit 10, the thickness range of SiO2 be 500 angstroms to 10000 angstroms (including 500 angstroms and 10000 Angstrom), the reaction gas used is SiH4 (silane), N2O (nitrous oxide) and N2 (nitrogen).Secondly, using positive photoresist photoetching The structure of the passivation layer 30 out.Then, SiO2 is etched using the mode of wet etching to make the figure of the passivation layer 30, Wherein etching solution is the mixed solution in hydrofluoric acid and ammonium fluoride.Finally, removing the photoresist, after the etch is completed to be formed It is laminated in the passivation layer 50 of the p type semiconductor layer 14 of the extension unit 10, and the passivation layer 50 coats institute State the N-type electrode 41 and the P-type electrode 42 of transparency conducting layer 30 and the electrode group 40, and the passivation layer 50 The first through hole 51 correspond to the N-type electrode pad 411 of the N-type electrode 41 of the electrode group 40 and described Second through-hole 52 corresponds to the P-type electrode pad 421 of the P-type electrode 42 of the electrode group 40.

External power supply can the first through hole 51 through the passivation layer 50 and second through-hole 52 be respectively supplied to The N-type electrode 41 and the P-type electrode 42 of the electrode group 40.Electric current can be through the N-type electricity of the N-type electrode 41 Pole pad 411 and N-type electrode extension item 412 inject the n type semiconductor layer 12 of the extension unit 10, wherein in institute It states and has been kept the current barrier layer 20 between N-type electrode extension item 412 and the n type semiconductor layer 12, wherein the electricity Flow barrier 20 can prevent current convergence in the lower part of N-type electrode extension item 412, so that electric current can around It is injected into the n type semiconductor layer 12 evenly.Correspondingly, electric current can be through the P-type electrode pad of the P-type electrode 42 421 and every P-type electrode extension item 422 inject the transparency conducting layer 30 because every P-type electrode extends item 422 are laminated in the transparency conducting layer 30 and the p-type interdigital 4220 of every P-type electrode extension item 422 is protected respectively Hold these described perforation 31 in the transparency conducting layer 30, and the p-type fork of every P-type electrode extension item 422 The direction of the second end 102 of the size of finger 4220 from the P-type electrode pad 421 to the semiconductor chip successively increases Add, so that electric current can be uniformly injected into from the surface of the transparency conducting layer 30 and inside through P-type electrode extension item 422 The transparency conducting layer 30, and because the electricity is maintained between the transparency conducting layer 30 and the p type semiconductor layer 14 Flow barrier 20, thus the current barrier layer 20 can prevent current convergence the P-type electrode extension item 422 lower part, So that electric current can be uniformly injected into around to the p type semiconductor layer 14.It is uniformly implanted the n type semiconductor layer 12 electric current and the electric current for being uniformly implanted the p type semiconductor layer 14 can be compound in the active area 13 and generate light Line, and such mode enables the brightness of the semiconductor chip to be sufficiently elevated.

Attached drawing 2A and Fig. 2 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip described in transparency conducting layer 30 at least one column perforation each of 31 perforation 31 ruler The very little first end 101 from the semiconductor chip to the second end 102 it is incremented by successively unlike, in attached drawing 2A In this preferable examples of the semiconductor chip shown in Fig. 2 B, at least one column perforation of the transparency conducting layer 30 The size of each of 31 perforation 31 is from the first end 101 of the semiconductor chip to the second end 102 Successively successively decrease in direction.That is, the size close to the perforation 31 of the second end 102 of the semiconductor chip is small In the size of the perforation 31 of the first end 101 close to the semiconductor chip.

Correspondingly, after the P-type electrode 42 is laminated in the transparency conducting layer 30, the P of the P-type electrode 42 The size of the one column p-type interdigital each of 4220 p-type interdigital 4220 of type electrode extension item 422 is from the semiconductor core The first end 101 of piece successively successively decreases to 102 direction of the second end.That is, close to the semiconductor chip The second end 102 the p-type interdigital 4220 size be less than close to the semiconductor chip the first end The size of 101 p-type interdigital 4220, such mode are conducive to electric current and are uniformly distributed into the p type semiconductor layer 14.

Attached drawing 3A and Fig. 3 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip described in transparency conducting layer 30 at least one column perforation each of 31 perforation 31 ruler The very little first end 101 from the semiconductor chip to the second end 102 it is incremented by successively unlike, in attached drawing 3A In this preferable examples of the semiconductor chip shown in Fig. 3 B, at least one column perforation of the transparency conducting layer 30 The size of each of 31 perforation 31 is all the same, and at least one column perforation 31 of the transparency conducting layer 30 is adjacent Spacing between two perforation 31 is from the first end 101 of the semiconductor chip to 102 side of the second end To being gradually reduced.To, after the P-type electrode 42 is laminated in the transparency conducting layer 30, the P-type electrode 42 it is described P-type electrode extends the size constancy of the column p-type interdigital each of 4220 p-type interdigital 4220 of item 422, and institute The two neighboring p-type stated in a column p-type interdigital 4220 of the P-type electrode extension item 422 of P-type electrode 42 is interdigital Spacing between 4220 is gradually reduced from the first end 101 of the semiconductor chip to 102 direction of the second end, Such mode is conducive to electric current and is uniformly distributed into the p type semiconductor layer 14.

Attached drawing 4A and Fig. 4 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip described in transparency conducting layer 30 at least one column perforation each of 31 perforation 31 ruler The very little first end 101 from the semiconductor chip to the second end 102 it is incremented by successively unlike, in attached drawing 4A In this preferable examples of the semiconductor chip shown in Fig. 4 B, at least one column perforation of the transparency conducting layer 30 The size of each of 31 perforation 31 is from the first end 101 of the semiconductor chip to the second end 102 Direction is gradually successively decreased, and the spacing between the two neighboring perforation 31 of the column perforation 31 is from the semiconductor chip The first end 101 be gradually reduced to 102 direction of the second end.To be laminated in the P-type electrode 42 described After transparency conducting layer 30, the ruler of a column p-type interdigital 4220 of the P-type electrode extension item 422 of the P-type electrode 42 The very little first end 101 from the semiconductor chip gradually successively decreases to 102 direction of the second end, and described in the column The first end of spacing between the two neighboring p-type interdigital 4220 of p-type interdigital 4220 from the semiconductor chip 101 are gradually reduced to 102 direction of the second end, and such mode is conducive to electric current and is uniformly distributed into the p-type partly to lead Body layer 14.

Attached drawing 5A and Fig. 5 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip described in transparency conducting layer 30 at least one column perforation each of 31 perforation 31 ruler The very little first end 101 from the semiconductor chip to the second end 102 it is incremented by successively unlike, in attached drawing 5A In this preferable examples of the semiconductor chip shown in Fig. 5 B, at least one column perforation of the transparency conducting layer 30 The size of each of 31 perforation 31 is from the first end 101 of the semiconductor chip to the second end 102 Direction is gradually successively decreased, and the spacing between the two neighboring perforation 31 of the column perforation 31 is from the semiconductor chip The first end 101 gradually increased to 102 direction of the second end.To be laminated in the P-type electrode 42 described After transparency conducting layer 30, the ruler of a column p-type interdigital 4220 of the P-type electrode extension item 422 of the P-type electrode 42 The very little first end 101 from the semiconductor chip gradually successively decreases to 102 direction of the second end, and described in the column The first end of spacing between the two neighboring p-type interdigital 4220 of p-type interdigital 4220 from the semiconductor chip 101 gradually increase to 102 direction of the second end, and such mode is conducive to electric current and is uniformly distributed into the p-type partly to lead Body layer 14.

Attached drawing 6A and Fig. 6 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip described in transparency conducting layer 30 at least one column perforation each of 31 perforation 31 ruler The very little first end 101 from the semiconductor chip to the second end 102 it is incremented by successively unlike, in attached drawing 6A In this preferable examples of the semiconductor chip shown in Fig. 6 B, at least one column perforation of the transparency conducting layer 30 The size of each of 31 perforation 31 is all the same, and at least one column perforation 31 of the transparency conducting layer 30 is adjacent Spacing between two perforation 31 is from the first end 101 of the semiconductor chip to 102 side of the second end To gradually increasing.To, after the P-type electrode 42 is laminated in the transparency conducting layer 30, the P-type electrode 42 it is described P-type electrode extends the size constancy of the column p-type interdigital each of 4220 p-type interdigital 4220 of item 422, and institute The two neighboring p-type stated in a column p-type interdigital 4220 of the P-type electrode extension item 422 of P-type electrode 42 is interdigital Spacing between 4220 is gradually increased from the first end 101 of the semiconductor chip to 102 direction of the second end, Such mode is conducive to electric current and is uniformly distributed into the p type semiconductor layer 14.

Attached drawing 7A and Fig. 7 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip unlike, in this preferable examples of the semiconductor chip shown in attached drawing 7A and Fig. 7 B, The size of at least one column of the transparency conducting layer 30 perforation each of 31 perforation 31 is from the semiconductor chip The first end 101 be gradually incremented by 102 direction of the second end, and the column it is described perforation 31 two neighboring institute The spacing between perforation 31 is stated from the first end 101 of the semiconductor chip to 102 direction of the second end gradually Reduce.To, after the P-type electrode 42 is laminated in the transparency conducting layer 30, the p-type electricity of the P-type electrode 42 Pole extends the size of a column p-type interdigital 4220 of item 422 from the first end 101 of the semiconductor chip to described 102 direction of the second end is gradually incremented by, and between the two neighboring p-type interdigital 4220 of the column p-type interdigital 4220 Spacing be gradually reduced from the first end 101 of the semiconductor chip to 102 direction of the second end, such side Formula is conducive to electric current and is uniformly distributed into the p type semiconductor layer 14.

Attached drawing 8A and Fig. 8 B show a variant embodiment of the semiconductor chip, show with attached drawing 1A and Figure 1B The semiconductor chip unlike, in this preferable examples of the semiconductor chip shown in attached drawing 8A and Fig. 8 B, The size of at least one column of the transparency conducting layer 30 perforation each of 31 perforation 31 is from the semiconductor chip The first end 101 be gradually incremented by 102 direction of the second end, and the column it is described perforation 31 two neighboring institute The spacing between perforation 31 is stated from the first end 101 of the semiconductor chip to 102 direction of the second end gradually Increase.To, after the P-type electrode 42 is laminated in the transparency conducting layer 30, the p-type electricity of the P-type electrode 42 Pole extends the size of a column p-type interdigital 4220 of item 422 from the first end 101 of the semiconductor chip to described 102 direction of the second end is gradually incremented by, and between the two neighboring p-type interdigital 4220 of the column p-type interdigital 4220 Spacing gradually increased from the first end 101 of the semiconductor chip to 102 direction of the second end, such side Formula is conducive to electric current and is uniformly distributed into the p type semiconductor layer 14.

Attached drawing 9 shows a variant embodiment of the semiconductor chip, described in shown in attached drawing 1A and Figure 1B Unlike semiconductor chip, in this preferable examples of the semiconductor chip shown in attached drawing 9, the semiconductor bare There is an exposed portion 151 of N-type electrode pad and a N-type electrode to extend the exposed portion 152 of item in portion 15, wherein described The exposed portion 151 of N-type electrode pad is formed in the second end 102 of the semiconductor chip, and the N-type electrode extension item is naked Dew portion 152 is naked from the N-type electrode pad along the length direction of the semiconductor chip at the middle part of the semiconductor chip Dew portion 151 extends to 101 direction of the first end of the semiconductor chip.

Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 includes one and is laminated in the N-type half Conductor layer 12 and it is maintained at the N-type electrode pad 411 in the exposed portion 151 of the N-type electrode pad and one is laminated in institute It states n type semiconductor layer 12 and the N-type p-type for being maintained at the N-type electrode extension exposed portion 152 of item inserts finger electrode extension item 412, wherein the N-type electrode extends item 412 at the middle part of the semiconductor chip along the length side of the semiconductor chip Extend to 101 direction of the first end from the N-type electrode pad 411 to the semiconductor chip.

With reference to attached drawing 9, the quantity of the current barrier layer 20 is two, and current barrier layer 20 is described in two of them with mutual Symmetrical mode is at the edge of the semiconductor chip along the length direction of the semiconductor chip from the semiconductor chip The first end 101 extend to 102 direction of the second end.Subsequent, to coat the side of the current barrier layer 20 Formula is laminated the transparency conducting layer 30 in the p type semiconductor layer 14, and perforates described in each column of the transparency conducting layer 30 31 correspond respectively to the current barrier layer 20.Correspondingly, the transparency conducting layer 30 has the perforation 31 of two column, wherein often Arrange the different location that each of described perforation 31 perforation 31 corresponds respectively to each current barrier layer 20.

Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one The P-type electrode pad 421 of conductive layer 30 and two P-type electrodes extend item 422, wherein the P-type electrode pad 421 It is formed in the first end 101 of the semiconductor chip, wherein each P-type electrode extension item 422 is respectively with mutual Symmetrical mode is at the edge of the semiconductor chip along the length direction of the semiconductor chip from the P-type electrode pad 421 extend to 102 direction of the second end of the semiconductor chip, and the institute of each P-type electrode extension item 422 It states p-type interdigital 4220 and is respectively formed in and is maintained at the perforation 31 of each of described transparency conducting layer 30.With reference to attached drawing 9, The N-type electrode extension item 412 of the N-type electrode 41 is maintained at two P-type electrode extensions of the P-type electrode 42 Between item 422.

With continued reference to attached drawing 9, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40 Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.

Attached drawing 10 shows another variant embodiment of the semiconductor chip, with the institute shown in attached drawing 1A and Figure 1B It states unlike semiconductor chip, in this preferable examples of the semiconductor chip shown in attached drawing 10, the semiconductor There is an exposed portion 151 of N-type electrode pad and three N-type electrodes to extend the exposed portion 152 of item in exposed portion 15, wherein The exposed portion 151 of N-type electrode pad is formed in the second end 102 of the semiconductor chip, wherein three N-types The exposed portion 152 of electrode extension item is respectively defined as the exposed portion 152a of one first extension item, the one second extension exposed portion 152b of item And one third extend the exposed portion 152c of item, wherein it is described first extension the exposed portion 152a of item and the third extend the exposed portion of item 152c in symmetrical mode at the edge of the semiconductor chip along the length direction of the semiconductor chip from the N The exposed portion 151 of type electrode pad extends to 101 direction of the first end of the semiconductor chip, and the second extension item is naked Dew portion 152b is naked from the N-type electrode pad along the length direction of the semiconductor chip at the middle part of the semiconductor chip Dew portion 151 extends to 101 direction of the first end of the semiconductor chip.

Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 includes a N-type electrode pad 411 and three N-type electrodes extend items 412, wherein the N-type electrode pad 411 is laminated in 12 He of n type semiconductor layer It is maintained at the exposed portion 151 of the N-type electrode pad, wherein three N-type electrode extensions article 412 are defined as one the oneth N Type electrode extension 412a, one second N-type electrode extension 412b and a third N-type electrode extend a 412c, wherein described First N-type electrode extends 412c points of a 412a, second N-type electrode extension 412b and third N-type electrode extension It is not laminated in the n type semiconductor layer 12 and is respectively held in the exposed portion 152a of the first extension item, second extension The exposed portion 152b of item and the third extend the exposed portion 152c of item, so that first N-type electrode extension 412a and institute State third N-type electrode extension 412c in symmetrical mode at the edge of the semiconductor chip along the semiconductor core The first end 101 direction of the length direction of piece from the N-type electrode pad 411 to the semiconductor chip extends, institute State the second N-type electrode extension 412b at the middle part of the semiconductor chip along the length direction of the semiconductor chip from institute N-type electrode pad 411 is stated to extend to 101 direction of the first end of the semiconductor chip.

With reference to attached drawing 10, the quantity of the current barrier layer 20 is two, and current barrier layer 20 is described in two of them with phase Mutually symmetrical mode at the middle part of the semiconductor chip along the length direction of the semiconductor chip from the semiconductor core The first end 101 of piece extends to 102 direction of the second end.Subsequent, to coat the current barrier layer 20 The transparency conducting layer 30 is laminated in the p type semiconductor layer 14 in mode, and the perforation 31 of the transparency conducting layer 30 Correspond respectively to the current barrier layer 20.Correspondingly, the transparency conducting layer 30 has the perforation 31 of two column, wherein each column The perforation 31 corresponds respectively to each current barrier layer 20.

Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one The P-type electrode pad 421 of conductive layer 30 and two P-type electrodes extend item 422, wherein each P-type electrode expands Open up item 422 respectively in symmetrical mode at the middle part of the semiconductor chip along the length direction of the semiconductor chip 102 direction of the second end from from the P-type electrode pad 421 to the semiconductor chip extends, and each p-type It is described that the p-type interdigital 4220 of electrode extension item 422 is respectively formed in and is maintained at each of described transparency conducting layer 30 Perforation 31.With reference to attached drawing 10, the P-type electrode extension item 422 of one of the P-type electrode 42 is maintained at first N-type Between electrode extension 412a and second N-type electrode extension 412b, another described P-type electrode extension item 422 is protected It holds and is extended between a 412b and third N-type electrode extension 412c in second N-type electrode.

With continued reference to attached drawing 10, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40 Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.

Attached drawing 11 shows another variant embodiment of the semiconductor chip, and described shown in attached drawing 10 is partly led Unlike body chip, in this preferable examples of the semiconductor chip shown in attached drawing 11, the semiconductor bare portion 15 there is an exposed portion 151 of N-type electrode pad and two N-type electrodes to extend the exposed portion 152 of item, wherein the N The exposed portion 151 of type electrode pad is formed in the second end 102 of the semiconductor chip, two N-type electrode extensions The exposed portion 152 of item is in symmetrical mode at the edge of the semiconductor chip along the length direction of the semiconductor chip Extend from the exposed portion 151 of the N-type electrode pad to 101 direction of the first end of the semiconductor chip.

Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 includes a N-type electrode pad 411 and two N-type electrodes extend items 412, wherein the N-type electrode pad 411 is laminated in 12 He of n type semiconductor layer It is maintained at the exposed portion 151 of the N-type electrode pad, wherein each N-type electrode extension item 412 is respectively laminated on the N Type semiconductor layer 12 extends the exposed portion 152 of item with each N-type electrode is maintained at, so that each N-type electrode Extend item 412 with symmetrical mode the edge of the semiconductor chip along the semiconductor chip length direction from The N-type electrode pad 411 extends to 101 direction of the first end of the semiconductor chip.

With reference to attached drawing 11, the quantity of the current barrier layer 20 is one, wherein the current barrier layer 20 is described half The middle part of conductor chip along the semiconductor chip length direction from the first end 101 of the semiconductor chip to 102 direction of the second end extends.Subsequent, the transparency conducting layer is laminated in a manner of coating the current barrier layer 20 30 in the p type semiconductor layer 14, and the perforation 31 of the transparency conducting layer 30 corresponds to the current barrier layer 20.

Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one The P-type electrode pad 421 of conductive layer 30 and a P-type electrode extend item 422, wherein the P-type electrode pad 421 It is formed in the first end 101 of the semiconductor chip, the P-type electrode extension item 421 is in the semiconductor chip Middle part along the length direction of the semiconductor chip from the P-type electrode pad 421 to the semiconductor chip described Two ends, 102 direction extends, and the p-type interdigital 4220 of P-type electrode extension item 422 is formed in and is maintained at institute State the perforation 31 of transparency conducting layer 30.With reference to attached drawing 11, the P-type electrode extension item 422 of the P-type electrode 42 is protected It holds between two N-type electrode extension items 412 of the N-type electrode 41.

With continued reference to attached drawing 11, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40 Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.

Attached drawing 12 shows another variant embodiment of the semiconductor chip, and described shown in attached drawing 11 is partly led Unlike body chip, in this preferable examples of the semiconductor chip shown in attached drawing 12, the semiconductor bare portion 15 only have an exposed portion 151 of N-type electrode pad, are formed in the second end 102 of the semiconductor chip. Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 only includes a N-type electrode pad 411, Described in N-type electrode pad 411 be laminated in the n type semiconductor layer 12 and be maintained at the exposed portion of N-type electrode pad 151。

With reference to attached drawing 12, the quantity of the current barrier layer 20 is one, wherein the current barrier layer 20 is described half The middle part of conductor chip along the semiconductor chip length direction from the first end 101 of the semiconductor chip to 102 direction of the second end extends, and subsequent, the transparency conducting layer is laminated in a manner of coating the current barrier layer 20 30 in the p type semiconductor layer 14, and the perforation 31 of the transparency conducting layer 30 corresponds to the current barrier layer 20.

Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one The P-type electrode pad 421 of conductive layer 30 and a P-type electrode extend item 422, wherein the P-type electrode pad 421 It is formed in the first end 101 of the semiconductor chip, the P-type electrode extension item 421 is in the semiconductor chip Middle part along the length direction of the semiconductor chip from the P-type electrode pad 421 to the semiconductor chip described Two ends, 102 direction extends, and the p-type interdigital 4220 of P-type electrode extension item 422 is formed in and is maintained at institute State the perforation 31 of transparency conducting layer 30.

With continued reference to attached drawing 12, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40 Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.

It is worth noting that, the substrate 11, institute in the semiconductor chip shown in the accompanying drawings of the utility model State n type semiconductor layer 12, the active area 13, second semiconductor layer 14, the current barrier layer 20, the electrically conducting transparent The thickness of layer 30, the N-type electrode 41 and the P-type electrode 42 is merely illustrative, is not offered as the substrate 11, the N-type Semiconductor layer 12, the active area 13, second semiconductor layer 14, the current barrier layer 20, the transparency conducting layer 30, The actual thickness of the N-type electrode 41 and the P-type electrode 42.Also, it is the substrate 11, the n type semiconductor layer 12, described Active area 13, second semiconductor layer 14, the current barrier layer 20, the transparency conducting layer 30,41 and of the N-type electrode Actual proportions between the P-type electrode 42 are also unlike shown in the accompanying drawings.In addition, the N of the electrode group 40 The dimension scale of other layers of the size of type electrode 41 and the P-type electrode 42 and the semiconductor chip is also not limited to attached drawing Illustrated in.

In addition, described in the transparency conducting layer 30 of the semiconductor chip shown in the accompanying drawings of the utility model The spacing of the size of perforation 31, the dimension scale of the adjacent perforation 31 and the adjacent perforation 31 is example, to be used for It discloses and illustrates the content and feature of the semiconductor chip of the utility model, and be not construed as the institute to the utility model State the limitation of the content and range of semiconductor chip.

Correspondingly, in the P of the P-type electrode 42 of the semiconductor chip shown in the accompanying drawings of the utility model The spacing of the size of type interdigital 4220, the dimension scale of the adjacent p-type interdigital 4220 and the adjacent p-type interdigital 4220 is equal For example, with the content and feature for disclosing and illustrating the semiconductor chip of the utility model, and it is not construed as pair The limitation of the content and range of the semiconductor chip of the utility model.

It will be appreciated by those skilled in the art that above embodiments are only for example, wherein the feature of different embodiments It can be combined with each other, do not explicitly pointed out in the accompanying drawings with obtaining being readily conceivable that according to the content that the utility model discloses Embodiment.

It should be understood by those skilled in the art that foregoing description and the embodiments of the present invention shown in the drawings are only used as It illustrates and is not intended to limit the utility model.The purpose of this utility model completely and effectively realizes.The function of the utility model Energy and structural principle show and illustrate in embodiment, under without departing from the principle, the embodiments of the present invention Can there are any deformation or modification.

Claims

1. one is used for the semiconductor chip of light emitting diode characterized by comprising

One extension unit, wherein the extension unit include the substrate stacked gradually, a n type semiconductor layer, an active area and One p type semiconductor layer and with extending to the n type semiconductor layer at least through the active area from the p type semiconductor layer The exposed portion of semiconductor；

One transparency conducting layer, wherein the transparency conducting layer has at least one column perforation, wherein the transparency conducting layer is to coat The mode of the current barrier layer is laminated in the p type semiconductor layer, and the perforation of the transparency conducting layer corresponds to described Current barrier layer, and perforation described at least one of described perforation of a column is different from the adjacent perforation；And

One electrode group, wherein the electrode group includes being laminated in a N-type electrode of the n type semiconductor layer and being laminated in described One P-type electrode of bright conductive layer, wherein the N-type electrode includes being formed in a N-type of the second end of the semiconductor chip Electrode pad, wherein the P-type electrode include be formed in the first end of the semiconductor chip a P-type electrode pad and from At least P-type electrode that the P-type electrode pad extends to the second end direction of the semiconductor chip extends item, wherein institute Stating P-type electrode extension item has a column p-type interdigital, wherein the p-type is interdigital to be formed in and be maintained at the transparency conducting layer The perforation.

2. semiconductor chip according to claim 1, wherein the N-type electrode further comprises that an at least N-type electrode expands Item is opened up, wherein N-type electrode extension item prolongs from the N-type electrode pad to the second end direction of the semiconductor chip It stretches.

3. semiconductor chip according to claim 1, wherein the size of each of column perforation perforation from The first end of the semiconductor chip is gradually increased to the second end direction, thus every during a column p-type is interdigital The interdigital size of a p-type is reversely gradually increased from the first end of the semiconductor chip to the second end.

4. semiconductor chip according to claim 2, wherein the size of each of column perforation perforation from The first end of the semiconductor chip is gradually increased to the second end direction, thus every during a column p-type is interdigital The interdigital size of a p-type is reversely gradually increased from the first end of the semiconductor chip to the second end.

5. semiconductor chip according to claim 1, wherein the size of each of column perforation perforation from The first end of the semiconductor chip is gradually reduced to the second end direction, thus every during a column p-type is interdigital The interdigital size of a p-type is reversely gradually reduced from the first end of the semiconductor chip to the second end.

6. semiconductor chip according to claim 2, wherein the size of each of column perforation perforation from The first end of the semiconductor chip is gradually reduced to the second end direction, thus every during a column p-type is interdigital The interdigital size of a p-type is reversely gradually reduced from the first end of the semiconductor chip to the second end.

7. semiconductor chip according to claim 1, wherein between the two neighboring perforation in a column perforation Spacing be gradually increased from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually increased.

8. semiconductor chip according to claim 2, wherein between the two neighboring perforation in a column perforation Spacing be gradually increased from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually increased.

9. semiconductor chip according to claim 3, wherein between the two neighboring perforation in a column perforation Spacing be gradually increased from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually increased.

10. semiconductor chip according to claim 4, wherein between the two neighboring perforation in a column perforation Spacing be gradually increased from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually increased.

11. semiconductor chip according to claim 5, wherein between the two neighboring perforation in a column perforation Spacing be gradually increased from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually increased.

12. semiconductor chip according to claim 6, wherein between the two neighboring perforation in a column perforation Spacing be gradually increased from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually increased.

13. semiconductor chip according to claim 1, wherein between the two neighboring perforation in a column perforation Spacing be gradually reduced from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually reduced.

14. semiconductor chip according to claim 2, wherein between the two neighboring perforation in a column perforation Spacing be gradually reduced from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually reduced.

15. semiconductor chip according to claim 3, wherein between the two neighboring perforation in a column perforation Spacing be gradually reduced from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually reduced.

16. semiconductor chip according to claim 4, wherein between the two neighboring perforation in a column perforation Spacing be gradually reduced from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually reduced.

17. semiconductor chip according to claim 5, wherein between the two neighboring perforation in a column perforation Spacing be gradually reduced from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually reduced.

18. semiconductor chip according to claim 6, wherein between the two neighboring perforation in a column perforation Spacing be gradually reduced from the first end of the semiconductor chip to the second end direction, thus column p-type fork Spacing between the two neighboring p-type in finger is interdigital is from the first end of the semiconductor chip to the second end side To being gradually reduced.

19. according to the semiconductor chip any in claim 2,4,6,8,10,12,14,16 and 18, wherein the N-type Electrode includes that the N-type electrode extends item, and the N-type electrode extension item is at the middle part of the semiconductor chip along described The length direction of semiconductor chip extends, wherein the P-type electrode includes that two P-type electrodes extend item, two p-types Electrode extension item is in symmetrical mode at the edge of the semiconductor chip along the length direction of the semiconductor chip Extend, wherein N-type electrode extension item is maintained between two P-type electrode extension items.

20. according to the semiconductor chip any in claim 2,4,6,8,10,12,14,16 and 18, wherein the N-type Electrode includes that two N-type electrodes extend item, and the two N-type electrode extension exposed portions of item are in the semiconductor chip Portion extends along the length direction of the semiconductor chip, wherein fettered P-type electrode includes three P-type electrode extensions Item, respectively one first P-type electrode extend item, one second P-type electrode extension item and a third P-type electrode and extend item, described First P-type electrode extends item and third P-type electrode extension item in symmetrical mode on the side of the semiconductor chip Edge extends along the length direction of the semiconductor chip, and the second P-type electrode extension item is in the semiconductor chip Portion extends along the length direction of the semiconductor chip, one of them described N-type electrode extension article is maintained at the first P Between type electrode extension item and second P-type electrode extension item, another described N-type electrode extension article is maintained at described the Two P-type electrodes extend between item and third P-type electrode extension item.

21. according to the semiconductor chip any in claim 2,4,6,8,10,12,14,16 and 18, wherein the N-type Electrode includes that two N-type electrodes extend item, and two N-type electrode extension items are partly led in symmetrical mode described The edge of body chip extends along the length direction of the semiconductor chip, wherein the P-type electrode includes the p-type electricity Pole extends item, and the P-type electrode extension item prolongs at the middle part of the semiconductor chip along the length direction of the P-type electrode It stretches, wherein P-type electrode extension item is maintained between two N-type electrode extension items.

22. according to the semiconductor chip any in claim 2,4,6,8,10,12,14,16 and 18, wherein the N-type Electrode includes that three N-type electrodes extend items, respectively one first N-type electrode extend item, one second N-type electrode extension item with And one third N-type electrode extend item, first N-type electrode extension item and third N-type electrode extension item are with symmetrical Mode the edge of the semiconductor chip along the semiconductor chip length direction extend, second N-type electrode It extends item to extend at the middle part of the semiconductor chip along the length direction of the semiconductor chip, wherein the P-type electrode Item is extended including two P-type electrodes, two P-type electrode extension items are in symmetrical mode in the semiconductor core Along the rectangular extension of length of the semiconductor chip, one of them described P-type electrode extension item is maintained at institute at the middle part of piece It states between the first N-type electrode extension item and second N-type electrode extension item, another described P-type electrode extension item is kept It is extended between item and third N-type electrode extension item in second N-type electrode.

23. according to the semiconductor chip any in claim 2,4,6,8,10,12,14,16 and 18, wherein the extension The surface for being exposed on the semiconductor bare portion of the n type semiconductor layer of unit is laminated at least one described electric current resistance Barrier, wherein N-type electrode cladding is laminated in the current barrier layer of the n type semiconductor layer.

24. semiconductor chip according to claim 19, wherein the n type semiconductor layer of the extension unit is sudden and violent The surface for being exposed at the semiconductor bare portion is laminated at least one described current barrier layer, wherein the N-type electrode clad It is laminated on the current barrier layer of the n type semiconductor layer.

25. semiconductor chip according to claim 20, wherein the n type semiconductor layer of the extension unit is sudden and violent The surface for being exposed at the semiconductor bare portion is laminated at least one described current barrier layer, wherein the N-type electrode clad It is laminated on the current barrier layer of the n type semiconductor layer.

26. semiconductor chip according to claim 21, wherein the n type semiconductor layer of the extension unit is sudden and violent The surface for being exposed at the semiconductor bare portion is laminated at least one described current barrier layer, wherein the N-type electrode clad It is laminated on the current barrier layer of the n type semiconductor layer.

27. semiconductor chip according to claim 22, wherein the n type semiconductor layer of the extension unit is sudden and violent The surface for being exposed at the semiconductor bare portion is laminated at least one described current barrier layer, wherein the N-type electrode clad It is laminated on the current barrier layer of the n type semiconductor layer.

28. semiconductor chip according to claim 23, wherein being laminated in the current blocking of the n type semiconductor layer Layer is stripped, extends along the length direction of the semiconductor chip.

29. semiconductor chip according to claim 24, wherein being laminated in the current blocking of the n type semiconductor layer Layer is stripped, extends along the length direction of the semiconductor chip.

30. semiconductor chip according to claim 25, wherein being laminated in the current blocking of the n type semiconductor layer Layer is stripped, extends along the length direction of the semiconductor chip.

31. semiconductor chip according to claim 26, wherein being laminated in the current blocking of the n type semiconductor layer Layer is stripped, extends along the length direction of the semiconductor chip.

32. semiconductor chip according to claim 27, wherein being laminated in the current blocking of the n type semiconductor layer Layer is stripped, extends along the length direction of the semiconductor chip.

33. semiconductor chip according to claim 23, wherein being laminated in the current blocking of the n type semiconductor layer Layer quantity be it is multiple, these described current barrier layers are stripped to be prolonged along the length direction of the semiconductor chip in a row It stretches, and there is spaced slot between the two neighboring current barrier layer.

34. semiconductor chip according to claim 24, wherein being laminated in the current blocking of the n type semiconductor layer Layer quantity be it is multiple, these described current barrier layers are stripped to be prolonged along the length direction of the semiconductor chip in a row It stretches, and there is spaced slot between the two neighboring current barrier layer.

35. semiconductor chip according to claim 25, wherein being laminated in the current blocking of the n type semiconductor layer Layer quantity be it is multiple, these described current barrier layers are stripped to be prolonged along the length direction of the semiconductor chip in a row It stretches, and there is spaced slot between the two neighboring current barrier layer.

36. semiconductor chip according to claim 26, wherein being laminated in the current blocking of the n type semiconductor layer Layer quantity be it is multiple, these described current barrier layers are stripped to be prolonged along the length direction of the semiconductor chip in a row It stretches, and there is spaced slot between the two neighboring current barrier layer.

37. semiconductor chip according to claim 27, wherein being laminated in the current blocking of the n type semiconductor layer Layer quantity be it is multiple, these described current barrier layers are stripped to be prolonged along the length direction of the semiconductor chip in a row It stretches, and there is spaced slot between the two neighboring current barrier layer.

38. further comprising a passivation layer, wherein described blunt according to claim 1 to any semiconductor chip in 18 Changing layer has a first through hole and one second through-hole, wherein the passivation layer is to coat the N-type electrode and the P-type electrode Mode is laminated in the p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to Second through-hole of the N-type electrode, the passivation layer corresponds to the P-type electrode.

39. semiconductor chip according to claim 19 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

40. semiconductor chip according to claim 20 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

41. semiconductor chip according to claim 21 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

42. semiconductor chip according to claim 22 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

43. semiconductor chip according to claim 23 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

44. semiconductor chip according to claim 24 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

45. semiconductor chip according to claim 25 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

46. semiconductor chip according to claim 26 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

47. semiconductor chip according to claim 27 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

48. semiconductor chip according to claim 28 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

49. semiconductor chip according to claim 29 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

50. semiconductor chip according to claim 30 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

51. semiconductor chip according to claim 31 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

52. semiconductor chip according to claim 32 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

53. semiconductor chip according to claim 33 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

54. semiconductor chip according to claim 34 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

55. semiconductor chip according to claim 35 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

56. semiconductor chip according to claim 36 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.

57. the semiconductor chip according to claim 37 further comprises a passivation layer, wherein the passivation layer has one First through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode The p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity Second through-hole of pole, the passivation layer corresponds to the P-type electrode.