CN208478366U - The chip of light emitting diode - Google Patents
The chip of light emitting diode Download PDFInfo
- Publication number
- CN208478366U CN208478366U CN201821130101.0U CN201821130101U CN208478366U CN 208478366 U CN208478366 U CN 208478366U CN 201821130101 U CN201821130101 U CN 201821130101U CN 208478366 U CN208478366 U CN 208478366U
- Authority
- CN
- China
- Prior art keywords
- type electrode
- chip
- type
- item
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Led Devices (AREA)
Abstract
The utility model discloses the chips of a light emitting diode, wherein the chip includes the substrate stacked gradually, one n type semiconductor layer, one active area and a p type semiconductor layer and with the exposed portion of at least semiconductor for extending to the n type semiconductor layer from the p type semiconductor layer, the chip further includes a current barrier layer, one transparency conducting layer, one N-type electrode and a P-type electrode, wherein the current barrier layer is laminated in the p type semiconductor layer, the transparency conducting layer is laminated in the p type semiconductor layer in a manner of coating the current barrier layer, and the perforation of the transparency conducting layer corresponds to the current barrier layer, the N-type electrode is laminated in the n type semiconductor layer, the P-type electrode is laminated in the transparency conducting layer, and the p-type of the P-type electrode interdigital is maintained at the transparency conducting layer The perforation.
Description
Technical field
The utility model relates to a LED chips, the in particular to chip of a light emitting diode.
Background technique
The packed LED chip of the prior art is come usually using lithography step to both structures by two kinds of structures, industry
Packed LED chip is named, that is, three structure packed LED chips and five structure packed LED chips.That is, three
Structure packed LED chip uses three lithography steps during being produced, and five structure packed LED chips are being produced
Five lithography steps are used in the process, it is generally the case that the lithography step of five structure packed LED chips can also be by five light
It carves step and is reduced to four lithography steps.For three structure packed LED chips, process include Mesa process (step,
Refer in the way of dry etching in the process of epitaxial wafer surface production N-type layer exposed region), ITO process (refers to
Bright conductive film layer figure process) and PV&Pad process (refer to that passivation layer and electrode use identical procedure photoetching figure
The process that shape is made);For five structure packed LED chips, process includes Mesa process, CB process (current blocking
The production process of layer), ITO process and PV&Pad process.It is said from structure, three structure packed LED chips and five
Structure packed LED chip no significant difference, from process for, five structure packed LED chips are than five structure forward LED cores
The more structures of current barrier layer (CB) of piece, are the current barrier layer of P-type electrode, in order to prevent packed LED chip
From P-type electrode inject current convergence the underface of P-type electrode and caused by current-crowding effect.Certainly, current barrier layer
The increase of structure is to increase packed LED chip processing procedure cost, is based on this, small-power chip commonly used in the trade, display are with chip
Three structure packed LED chips, and high-power chip, illumination chip are five structure packed LED chips.
From the point of view of the PN diode positive and negative resistance of five structure packed LED chips composition, P-type electrode electric current flows through metal
Electrode is to inject transparency conducting layer after being extended by metal electrode, then by injecting p-type gallium nitride layer after transparency conducting layer, most
Enter active layer afterwards;And N-type electrode resistance group becomes electronics by metal electrode with injection N-type nitridation after being extended by metal electrode
Gallium layer, finally enters active area, in active area recombination luminescence.Electricity from the point of view of entire current course, relative to semiconductor layer
The conductivity of conductance, metal electrode is higher, and therefore, the electric current on P-type electrode surface has the tendency that being gathered in P interdigital electrode end.
From the point of view of the curve of the characteristics of luminescence of five structure packed LED chips, with the rising of current density, brightness has under rising then
The trend of drop, there are saturation current densities, this will affect the luminous efficiency of five structure packed LED chips.Ideal high brightness
Luminescence chip structure enables to the current density of packed LED chip to maintain the higher region of luminous efficiency, however, current
Five structure packed LED chips cannot achieve.
Utility model content
One of the utility model is designed to provide the chip of a light emitting diode, wherein the brightness of the chip can
It is sufficiently elevated.
One of the utility model is designed to provide the chip of a light emitting diode, wherein injecting a P of the chip
The electric current of type semiconductor layer can be evenly distributed over, to be conducive to be promoted the brightness of the chip.
One of the utility model is designed to provide the chip of a light emitting diode, wherein the chip provides a p-type
Electrode can be forced to be distributed by the electric current that the P-type electrode injects the chip, in this way, so that injection
The electric current of the p type semiconductor layer can be evenly distributed over, to be conducive to be promoted the brightness of the chip.
One of the utility model is designed to provide the chip of a light emitting diode, wherein chip offer is laminated in
One current barrier layer of the p type semiconductor layer and it is laminated in the one of the p type semiconductor layer and the cladding current barrier layer
Transparency conducting layer, wherein the P-type electrode is laminated in the transparency conducting layer, so as to derive from the electric current of P-type electrode injection
It is stopped after the transparency conducting layer can be further injected by the current barrier layer, to avoid current collection in the p-type
The bad phenomenon of electrode occurs, electric current can be made to be uniformly distributed into the p type semiconductor layer subsequent.
One of the utility model is designed to provide the chip of a light emitting diode, wherein the p-type of the P-type electrode is pitched
Refer to and be inserted into the transparency conducting layer, so that the electric current for being injected the P-type electrode can be further from the transparency conducting layer
Surface and the internal injection transparency conducting layer, in this way, electric current can be uniformly distributed into the P-type semiconductor
Layer.
One of the utility model is designed to provide the chip of a light emitting diode, wherein the transparency conducting layer provides
At least one perforation is formed in and is kept wherein the p-type of the P-type electrode is interdigital to correspond to the current barrier layer
In the perforation of the transparency conducting layer, so that the electric current for being injected the P-type electrode can be further from described
The surface of bright conductive layer and the internal injection transparency conducting layer.
One of the utility model is designed to provide the chip of a light emitting diode, wherein forming in the P-type electrode
During, the interdigital perforation for being formed in and being maintained at the transparency conducting layer of the p-type of the P-type electrode, from
And the P-type electrode is made to be embedded in the transparency conducting layer, this combination of the P-type electrode and the transparency conducting layer
It can effectively guarantee the stability and reliability of the chip.
According to the one aspect of the utility model, the utility model provides the chip of a light emitting diode comprising:
One extension unit, wherein the extension unit includes that a substrate and the N-type successively grown from the substrate are partly led
Body layer, an active area and a p type semiconductor layer, wherein the extension unit has at least exposed portion of semiconductor, it is described partly to lead
The exposed portion of body extends to the n type semiconductor layer through the active area from the p type semiconductor layer;
An at least current barrier layer, wherein the current barrier layer is laminated in the P-type semiconductor of the extension unit
Layer;
One transparency conducting layer, wherein the transparency conducting layer is perforated at least one, wherein the transparency conducting layer is to wrap
The mode for covering the current barrier layer is laminated in the p type semiconductor layer, and the perforation of the transparency conducting layer is corresponding
In the current barrier layer;And
One electrode group, wherein the electrode group includes an at least N-type electrode and an at least P-type electrode, wherein the N-type is electric
Pole is laminated in the n type semiconductor layer in a manner of being formed in the semiconductor bare portion, wherein the P-type electrode has at least
One p-type is interdigital, and when the P-type electrode is laminated in the transparency conducting layer, the p-type of the P-type electrode is interdigital to be formed in
With the perforation for being maintained at the transparency conducting layer.
One embodiment according to the present utility model, the N-type electrode include the second end for being formed in the chip
One N-type electrode pad and at least N-type electrode extended from the N-type electrode pad to the first end direction of the chip expand
Item is opened up, wherein the P-type electrode includes being formed in a P-type electrode pad of the first end of the chip and from p-type electricity
At least two P-type electrodes that pole pad extends to the second end direction of the chip extend item, the electricity of N-type described in wherein at least one
Pole extension item is maintained between the two neighboring P-type electrode extension item.
The quantity of one embodiment according to the present utility model, the N-type electrode extension item of the N-type electrode is one
It is a, and N-type electrode extension item extends at the middle part of the chip along the length direction of the chip, wherein the P
The quantity of the P-type electrode extension item of type electrode is two, and two P-type electrode extension items are with symmetrical side
Formula extends at the edge of the chip along the length direction of the chip.
The quantity of one embodiment according to the present utility model, the N-type electrode extension item of the N-type electrode is two
It is a, and N-type electrode extension item extends at the middle part of the chip along the length direction of the chip, wherein the P
The quantity of the P-type electrode extension item of type electrode is three, and respectively one first P-type electrode extends item, one second P-type electrode
Extend item and a third P-type electrode extend item, the first P-type electrode extension item and third P-type electrode extension item with
Symmetrical mode extends at the edge of the chip along the length direction of the chip, the second P-type electrode extension
Item extends at the middle part of the chip along the length direction of the chip, one of them described N-type electrode extension item is kept
It is extended between item and second P-type electrode extension item in first P-type electrode, another described N-type electrode extends item quilt
It is maintained between the second P-type electrode extension item and third P-type electrode extension item.
One embodiment according to the present utility model, the N-type electrode include the second end for being formed in the chip
One N-type electrode pad and at least two N-type electrodes extended from the N-type electrode pad to the first end direction of the chip expand
Item is opened up, wherein the P-type electrode includes being formed in a P-type electrode pad of the first end of the chip and from p-type electricity
At least P-type electrode that pole pad extends to the second end direction of the chip extends item, the electricity of p-type described in wherein at least one
Pole extension item is maintained between the two neighboring N-type electrode extension item.
The quantity of one embodiment according to the present utility model, the N-type electrode extension item of the N-type electrode is two
It is a, and two N-type electrodes extension items in symmetrical mode at the edge of the chip along the length of the chip
It spends direction to extend, wherein the quantity of the P-type electrode extension item of the P-type electrode is one, and the P-type electrode extends
Item extends at the middle part of the chip along the length direction of the chip.
The quantity of one embodiment according to the present utility model, the N-type electrode extension item of the N-type electrode is three
A, respectively one first N-type electrode extends item, one second N-type electrode extension item and a third N-type electrode and extends item, described
First N-type electrode extend item and the third N-type electrode extension item with symmetrical mode the edge of the chip along
The length direction of the chip extends, and the second N-type electrode extension item is at the middle part of the chip along the length of the chip
Direction is spent to extend, wherein the quantity of the P-type electrode extension item of the P-type electrode is two, P-type electrode described in two of them
It extends item to extend at the middle part of the chip along the length direction of the chip, one of them described P-type electrode extends item quilt
It is maintained between the first N-type electrode extension item and second N-type electrode extension item, another described P-type electrode extension
Item is maintained between the second N-type electrode extension item and third N-type electrode extension item.
One embodiment according to the present utility model, the N-type electrode include the second end for being formed in the chip
One N-type electrode pad, wherein the P-type electrode include be formed in the first end of the chip a P-type electrode pad and from
The P-type electrode that the P-type electrode pad extends to the second end direction of the chip extends item.
One embodiment according to the present utility model, the n type semiconductor layer of the extension unit are exposed on institute
The surface for stating semiconductor bare portion is laminated at least one described current barrier layer, wherein N-type electrode cladding is laminated in institute
State the current barrier layer of n type semiconductor layer.
One embodiment according to the present utility model is laminated in the current barrier layer of the n type semiconductor layer in item
It is band-like, extend along the length direction of the chip.
One embodiment according to the present utility model is laminated in the number of the current barrier layer of the n type semiconductor layer
Amount be it is multiple, these described current barrier layers are stripped to be extended along the length direction of the chip in a row, and in phase
There is spaced slot between adjacent two current barrier layers.
One embodiment according to the present utility model, the chip further comprises a passivation layer, wherein the passivation layer
With a first through hole and one second through-hole, wherein the passivation layer is in a manner of coating the N-type electrode and the P-type electrode
It is laminated in the p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N
Second through-hole of type electrode, the passivation layer corresponds to the P-type electrode.
According to the other side of the utility model, the utility model further provides for the manufacturing method of a chip, wherein institute
Manufacturing method is stated to include the following steps:
(a) one current barrier layer of stacking is in a p type semiconductor layer of an extension unit;
(b) transparency conducting layer is laminated in a manner of coating the current barrier layer in the p type semiconductor layer, wherein institute
Transparency conducting layer is stated at least one perforation, to correspond to the current barrier layer;And
(c) the N-type electricity is laminated in such a way that a N-type electrode is maintained at the exposed portion of semiconductor of the extension unit
Pole is formed in the transparency conducting layer in a n type semiconductor layer of the extension unit, and with the p-type of a P-type electrode is interdigital
The P-type electrode is laminated in the transparency conducting layer, the chip is made in the mode of the perforation.
One embodiment according to the present utility model, the manufacturing method further comprises step:
(d) be laminated in a manner of coating the N-type electrode and the P-type electrode passivation layer in the transparency conducting layer and
The p type semiconductor layer, wherein the passivation layer has the first passage corresponding to the N-type electrode and corresponds to the P
One second channel of type electrode.
One embodiment according to the present utility model further comprises step in the step (a):
(a.1) one layer insulating of deposition is in the p type semiconductor layer;With
(a.2) insulating layer described in wet etching, to be laminated on the institute of the p type semiconductor layer by the insulating layer formation layer
State current barrier layer.
One embodiment according to the present utility model, before the step (a.2), the step (a) further comprises
Step: positive photoresist photoetching current barrier layer structure, to be etched in the step (a.2) according to current barrier layer architecture wet
The insulating layer, to be laminated on the current barrier layer of the p type semiconductor layer by the insulating layer formation layer, and in institute
After stating step (a.2), the step (a) further comprises step: removal photoresist.
One embodiment according to the present utility model, the material of the insulating layer are SiO2 materials.
One embodiment according to the present utility model, in the step (a.1), reaction gas SiH4, N2O and N2, with
The insulating layer is deposited in the p type semiconductor layer.
One embodiment according to the present utility model, the thickness range of the insulating layer are 500 angstroms to 10000 angstroms.
One embodiment according to the present utility model, the thickness range of photoresist are 0.5 μm to 5 μm.
One embodiment according to the present utility model, the etching solution that insulating layer described in wet etching uses are hydrofluoric acid and fluorine
Change the mixed solution of ammonium.
One embodiment according to the present utility model further comprises step in the step (b):
(b.1) deposition coats the indium oxide layer tin layers of the current barrier layer in the p type semiconductor layer;(b.2)
Tin indium oxide described in wet etching, to form the transparency conducting layer by the indium tin oxide layer and form the electrically conducting transparent
The perforation of layer.
One embodiment according to the present utility model, before the step (b.2), the step (b) further comprises
Step: positive photoresist photoetching structure of transparent conductive layer, to be etched in the step (b.2) according to the structure of the bright Dao electricity Ceng Eng of Tou
The indium tin oxide layer, to form the transparency conducting layer by the indium tin oxide layer and form the institute of the transparency conducting layer
Perforation is stated, and after the step (b.2), the step (b) further comprises step: removal photoresist.
One embodiment according to the present utility model, the positive photoresist photoetching transparency conducting layer the step of before, the step
Suddenly (b) further comprises step: carrying out alloy to the indium tin oxide layer.
One embodiment according to the present utility model, the etching solution that indium tin oxide layer described in wet etching uses be hydrochloric acid and
Chlorination iron mixed solution.
One embodiment according to the present utility model, in the step (a), be further laminated the current barrier layer in
The surface for being exposed on the semiconductor bare portion of the n type semiconductor layer, thus in the step (c), the N-type electricity
Pole cladding is laminated in the current barrier layer of the N-type peninsula head layer.
Detailed description of the invention
Figure 1A is the schematic cross-sectional view according to one of the manufacturing step of a chip of a preferred embodiment of the utility model.
Figure 1B is illustrated according to the vertical view of one of the manufacturing step of the chip of above-mentioned preferred embodiment of the utility model
Figure.
Fig. 2A is illustrated according to two section view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure.
Fig. 2 B is illustrated according to two vertical view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure.
Fig. 3 A is illustrated according to three section view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure.
Fig. 3 B is illustrated according to three vertical view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure.
Fig. 4 A is illustrated according to four section view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure.
Fig. 4 B is illustrated according to four vertical view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure.
Fig. 5 A is illustrated according to five section view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure, it illustrates the section view states of the chip.
Fig. 5 B is illustrated according to five vertical view of the manufacturing step of the chip of the above-mentioned preferred embodiment of the utility model
Figure, it illustrates the overlooking states of the chip.
Fig. 6 is walked according to the manufacture of a variant embodiment of the chip of the above-mentioned preferred embodiment of the utility model
Rapid schematic diagram.
Fig. 7 is the manufacture according to another variant embodiment of the chip of the above-mentioned preferred embodiment of the utility model
Step schematic diagram.
Fig. 8 is the manufacture according to another variant embodiment of the chip of the above-mentioned preferred embodiment of the utility model
Step schematic diagram.
Fig. 9 is the manufacture according to another variant embodiment of the chip of the above-mentioned preferred embodiment of the utility model
Step schematic diagram.
Specific embodiment
It is described below for disclosing the utility model so that those skilled in the art can be realized the utility model.It retouches below
Preferred embodiment in stating is only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It is retouched following
The basic principle of the utility model defined in stating can be applied to other embodiments, deformation scheme, improvement project, etc. Tongfangs
The other technologies scheme of case and the spirit and scope without departing from the utility model.
It will be understood by those skilled in the art that in the exposure of the utility model, term " longitudinal direction ", " transverse direction ", "upper",
The orientation of the instructions such as "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" or position are closed
System is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of describing the present invention and simplifying the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore on
Stating term should not be understood as limiting the present invention.
It is understood that term " one " is interpreted as " at least one " or " one or more ", i.e., in one embodiment,
The quantity of one element can be one, and in a further embodiment, the quantity of the element can be it is multiple, term " one " is no
It can be interpreted as the limitation to quantity.
With reference to the attached drawing 1A to Fig. 5 B of the Figure of description of the utility model, according to a preferred embodiment of the utility model
The chip of one light emitting diode is disclosed for and is set forth in following description, wherein the chip includes an extension unit
10, an at least current barrier layer 20, a transparency conducting layer 30 and an electrode group 40.
Specifically, the extension unit 10 includes a substrate 11, a n type semiconductor layer 12, an active area 13 and a P
Type semiconductor layer 14, wherein the n type semiconductor layer 12 is grown from the substrate 11, so that the n type semiconductor layer 12 is laminated
In the substrate 11, wherein the active area 13 is grown from the n type semiconductor layer 12, so that the active area 13 is laminated in institute
N type semiconductor layer 12 is stated, wherein the p type semiconductor layer 14 is grown from the active area 13, so that the p type semiconductor layer 14
It is laminated in the active area 13.
It is noted that the type of the substrate 11 of the extension unit 10 is in the chip of the utility model
It is unrestricted, such as the substrate 11 can be but not limited to Sapphire Substrate, silicon substrate etc..In addition, the n type semiconductor layer
12 and the type of the p type semiconductor layer 14 can also be unrestricted in the chip of the utility model, such as the N-type
Semiconductor layer 12 can be n type gallium nitride layer, and correspondingly, the p type semiconductor layer 14 can be p-type gallium nitride layer.
With reference to attached drawing 1A and Figure 1B, the extension unit 10 has at least exposed portion 15 of semiconductor, wherein described partly lead
The exposed portion 15 of body extends to the n type semiconductor layer 12 through the active area 13 from the p type semiconductor layer 14, described in exposure
N type semiconductor layer 12.That is, a part of surface of the n type semiconductor layer 12 is exposed on the semiconductor bare portion
15。
In the chip of the utility model, it is possible, firstly, to utilize metallo-organic compound chemical gaseous phase deposition equipment
(Metal-organic Chemical Vapor Deposition, MOCVD) successively grows the N-type half from the substrate 11
Conductor layer 12, the active area 13 and the p type semiconductor layer 14, the substrate 11 stacked gradually, the N-type are partly led
Body layer 12, the active area 13 and the p type semiconductor layer 14.Secondly, making Mesa figure using photoresist.Then, it uses
Inductively coupled plasma (Inductively Coupled Plasma, ICP) is successively to the p type semiconductor layer 14 and described
Active area 13 carries out dry etching, extends to the N-type through the active area 13 from the p type semiconductor layer 14 with formation and partly leads
The semiconductor bare portion 15 of body layer 12, and the n type semiconductor layer 12 is made to be exposed to the semiconductor bare portion 15.
In another preferable examples of the chip of the utility model, can be used inductively plasmon into one
N type semiconductor layer 12 described in step etching extend to the N-type through the active area 13 from the p type semiconductor layer 14 to be formed
The semiconductor bare portion 15 of semiconductor layer 12, and the n type semiconductor layer 12 is made to be exposed to the semiconductor bare
Portion 15.That is, in this preferable examples of the chip of the utility model, the correspondence of the n type semiconductor layer 12
Thickness in the semiconductor bare portion 15 is less than the thickness of the other parts of the n type semiconductor layer 12.
Preferably, the depth dimensions range in the semiconductor bare portion 15 of the extension unit 10 is 0.7 μm to 3 μm
(including 0.7 μm and 3 μm).Using inductively coupled plasma to the p type semiconductor layer 14, the active area 13 and described
It is Cl2 (chlorine), BCl3 (boron chloride) and Ar (argon gas) that n type semiconductor layer 12, which carries out the gas used when dry etching,.?
The p type semiconductor layer 14, the active area 13 and the n type semiconductor layer 12 are done using inductively coupled plasma
Method etches after forming the semiconductor bare portion 15, the photoresist is removed, to obtain the extension unit 10.Described in removal
The mode of photoresist is unrestricted in the chip of the utility model, such as can be through but not limited to going glue to remove photoresist
Mode removes the photoresist.
Further, with reference to attached drawing 1A to Fig. 5 B, the chip has a first end 101 and corresponds to the first end
One the second end 102 in portion 101.With continued reference to attached drawing 1A and Figure 1B, the semiconductor bare portion 15 has a N-type electrode pad
Exposed portion 151 and two N-type electrodes extend the exposed portion 152 of item, wherein the N-type electrode pad in the semiconductor bare portion 15 is naked
Dew portion 151 is formed in the second end 102 of the chip, and the N-type electrode of two of the semiconductor bare portion 15 expands
Open up the exposed portion 152 of item in symmetrical mode at the middle part of the chip along the length direction of the chip from the N-type
The exposed portion 151 of electrode pad extends to 101 direction of the first end of the chip.Two of the semiconductor bare portion 15
The N-type electrode extension exposed portion 152 of item is respectively communicated with the exposed portion 151 of the N-type electrode pad.
It is understood that the exposed portion 151 of the N-type electrode pad in the semiconductor bare portion 15 and two N
The exposed portion 152 of type electrode extension item by with along with etch process formed, and the semiconductor bare portion 15 the N-type electricity
The exposed portion 151 of pole pad and two N-type electrodes extension exposed portions 152 of item described in the p type semiconductor layer 14 warp from having
Source region 13 extends to the n type semiconductor layer 12, with a part of surface of the exposure n type semiconductor layer 12 in the semiconductor
The exposed portion 151 of the N-type electrode pad in exposed portion 15 and two N-type electrodes extend the exposed portion 152 of item.
With reference to attached drawing 2A and Fig. 2 B, it is laminated described at least one in the p type semiconductor layer 14 of the extension unit 10
Current barrier layer 20.Preferably, the quantity of the current barrier layer 20 is three, and three current barrier layers 20 are in
Ribbon, wherein these three described current barrier layers 20 are successively defined as one first current barrier layer 20a, the resistance of one second electric current
A barrier 20b and third current barrier layer 20c, wherein the first current barrier layer 20a, second current barrier layer
The 20b and third current barrier layer 20c respectively along the chip length direction from the first end of the chip
101 extend to 102 direction of the second end.
The N-type electrode extension of one of the semiconductor bare portion 15 exposed portion 152 of item is maintained at first electricity
Between flow barrier 20a and the second current barrier layer 20b, another N-type electrode in the semiconductor bare portion 15
The extension exposed portion 152 of item is maintained between the second current barrier layer 20b and the third current barrier layer 20c.It is preferred that
Ground, the first current barrier layer 20a and the third current barrier layer 20c are in symmetrical mode on the side of the chip
Edge extends from the first end 101 of the chip to 102 direction of the second end along the length direction of the chip,
The second current barrier layer 20b be maintained at the first current barrier layer 20a and third current barrier layer 20c it
Between mode at the middle part of the chip along the length direction of the chip from the first end 101 of the chip to institute
State the extension of 102 direction of the second end.
The mode that the current barrier layer 20 is laminated in the p type semiconductor layer 14 of the extension unit 10 is practical at this
It is unrestricted in the novel chip.For example, in a specific example of the chip of the utility model, firstly, sharp
With the vapour deposition process of plasma enhanced chemical (Plasma Enhanced Chemical Vapor Deposition,
PECVD one layer of SiO2 (silica)) is precipitated in the p type semiconductor layer 14 of the extension unit 10, the thickness model of SiO2
It encloses for 500 angstroms to 10000 angstroms (including 500 angstroms and 10000 angstroms), the reaction gas used is SiH4 (silane), (one aoxidizes N2O
Phenodiazine) and N2 (nitrogen).Secondly, make the structure of the current barrier layer 20 by lithography using positive photoresist, wherein the photoresist
Thickness range is 0.5 μm to 5 μm (including 0.5 μm and 5 μm).Then, SiO2 is etched to make using the mode of wet etching
The figure of current barrier layer 20 is stated, wherein etching solution is the mixed solution in hydrofluoric acid and ammonium fluoride.Finally, after the etch is completed
The photoresist is removed, to form the current barrier layer for the p type semiconductor layer 14 for being laminated in the extension unit 10
20。
Preferably, the current barrier layer 20 can also be laminated in the n type semiconductor layer 12 of the extension unit 10.
For example, the current barrier layer 20 can be formed in the N-type electrode extension in the semiconductor bare portion 15 with reference to attached drawing 2B
The exposed portion 152 of item, so that the current barrier layer 20 is laminated in the n type semiconductor layer 12 of the extension unit 10.More
Preferably, the adjacent current barrier layer 20 is spaced apart from each other, and these described current barrier layers 20 are to be spaced apart from each other and be in item
Band-like mode extends along the extending direction in the N-type electrode extension exposed portion 152 of item in the semiconductor bare portion 15.
It is noted that although described outer to be laminated in this preferable examples of the chip shown in attached drawing 2B
The quantity for prolonging the current barrier layer 20 of the n type semiconductor layer 12 of unit 10 is the multiple and adjacent current barrier layer
Between 20 with for spaced slot come disclose and illustrate the utility model the chip content and feature, but this field skill
Art personnel are not construed as the institute to the utility model it should be understood that the chip shown in attached drawing 2B is merely illustrative
State the limitation of the content and range of chip, that is, in other possible examples of the chip, be laminated in the N-type semiconductor
The quantity of the current barrier layer 20 of layer 12 can be one, and the current barrier layer 20 is stripped, so that described
The N-type electrode in the extending direction and development length of current barrier layer 20 and the semiconductor bare portion 15 extends the exposed portion of item
152 extending direction is consistent with development length.
With reference to attached drawing 3A and Fig. 3 B, firstly, deposition indium oxide layer tin layers (Indium Tin Oxides, ITO) is in described
The p type semiconductor layer 14 of extension unit 10, wherein the indium tin oxide layer is electrically connected to the p type semiconductor layer 14.Its
It is secondary, alloy treatment is carried out to the indium tin oxide layer.Preferably, the mode of alloy treatment is carried out to the indium tin oxide layer at this
It is unrestricted in the chip of utility model, quick anneal oven or alloy furnace tubes by adopting can be used for example to the tin indium oxide
Carry out alloy treatment.Then, figure photoetching is carried out to the indium tin oxide layer using positive photoresist, is lost after the completion of photoetching using wet process
The mode at quarter etches the indium tin oxide layer, to obtain the transparency conducting layer after etching is completed and removes the photoresist
30, wherein the transparency conducting layer 30 has at least one perforation 31, these described 31 difference of perforation of the transparency conducting layer 30
The different location of the corresponding current barrier layer 20 for being laminated in the p type semiconductor layer 14, so that the current barrier layer 20
It is exposed on the perforation 31 of the transparency conducting layer 30.Preferably, the oxidation is being etched in the way of wet etching
The etching solution used when indium tin layer is the mixed solution of hydrochloric acid and iron chloride.
Preferably, the transparency conducting layer 30 has the perforation 31 of three column, wherein a column of the transparency conducting layer 30
The perforation 31 corresponds respectively to the different location of the first current barrier layer 20a, another column of the transparency conducting layer 30
The perforation 31 corresponds respectively to the different location of the second current barrier layer 20b, another column of the transparency conducting layer 30
The perforation 31 corresponds respectively to the different location of the third current barrier layer 20c.
With reference to attached drawing 4A and Fig. 4 B, firstly, going out the electrode using negative-working photoresist on the surface of the transparency conducting layer 30
The figure of one N-type electrode 41 of group 40 and the figure of a P-type electrode 42.Secondly, by vapor deposition or sputter in the way of deposited metal
Electrode layer.Then, the remaining photoresist of extra metal layer and removal is removed, by the way of removing to form the electrode group
40 N-type electrode 41 and the P-type electrode 42.
Specifically, the N-type electrode 41 includes a N-type electrode pad 411 and is electrically connected to the N-type electrode pad
411 two N-type electrodes extend item 412, wherein the N-type electrode pad 411 of the N-type electrode 41 is formed in the extension list
Member 10 the semiconductor bare portion 15 the exposed portion 151 of the N-type electrode pad so that 411 layers of the N-type electrode pad
It is laminated on and is electrically connected to the n type semiconductor layer 12 of the extension unit 10, wherein the N-type electricity of the N-type electrode 41
Pole extension item 412 is formed in the N-type electrode extension exposed portion of item in the semiconductor bare portion 15 of the extension unit 10
152, so that N-type electrode extension item 412 is laminated in and is electrically connected to the n type semiconductor layer of the extension unit 10
12.It is understood that the N-type electrode extension item 412 is filled in the adjacent electricity for being laminated in the n type semiconductor layer 12
Spaced slot between flow barrier 20.Preferably, two N-type electrode extension items 412 are in symmetrical mode in institute
State the first end of the middle part of chip along the length direction of the chip from the N-type electrode pad 411 to the chip
101 direction of portion extends.
Correspondingly, the P-type electrode 42 includes a P-type electrode pad 421 and is electrically connected to the P-type electrode pad 421
Three P-type electrodes extend item 422, wherein a P-type electrode extension item 422 is defined as one first P-type electrode extension item
422a, another P-type electrode extension item 422 are defined as one second P-type electrode extension 422b, p-type described in another item
Electrode extension item 423 is defined as third P-type electrode extension 422c.The P-type electrode pad of the P-type electrode 42
421 and every P-type electrode extension item 422 be laminated in the transparency conducting layer 30, wherein the P-type electrode 42 is described
P-type electrode pad 421 is formed in the first end 101 of the chip, every P-type electrode of the P-type electrode 42
Item 422 is extended respectively along the length direction of the chip from the P-type electrode pad 421 to 102 direction of the second end
Extend.In the short transverse of the chip, first P-type electrode extension 422a and described first of the P-type electrode 42
Current barrier layer 20a overlaps so that first P-type electrode extension 422a p-type interdigital 4220 be formed in and
It is maintained at the perforation 31 of each of described transparency conducting layer 30;Second P-type electrode of the P-type electrode 42 extends item
422b overlaps with the second current barrier layer 20b, so that the P of second P-type electrode extension 422b
Type interdigital 4220, which refers to, is formed in and is maintained at the perforation 31 of each of described transparency conducting layer 30;The P-type electrode 42
The third P-type electrode extension 422c and third current barrier layer 20c overlaps, so that first p-type
The p-type interdigital 4220 of electrode extension 422a is formed in and is maintained at the perforation of each of the transparency conducting layer 30
31。
That is, first P-type electrode extension 422a of the P-type electrode 42 and the third P-type electrode expand
It is electric from the p-type along the length direction of the chip at the edge of the chip respectively in symmetrical mode to open up a 422c
Pole pad 421 extends to 102 direction of the second end of the chip, and second P-type electrode of the P-type electrode 42 expands
Exhibition 422b is at the middle part of the chip along the length direction of the chip from the P-type electrode pad 421 to the chip
102 direction of the second end extend.The N-type electrode extension item 412 of one of the N-type electrode 41 is maintained at described
Between first P-type electrode extension 422a and second P-type electrode extension 422b of P-type electrode 42, another institute
It states N-type electrode extension item 412 and is maintained at the second P-type electrode extension 422b and third P-type electrode extension item
Between 422c.
Preferably, the chip further comprises a passivation layer 50, wherein the passivation layer 50 is laminated in the extension list
The p type semiconductor layer 14 of member 10, and the passivation layer 50 coats the transparency conducting layer 30 and the electrode group 40
The N-type electrode 41 and the P-type electrode 42, wherein the passivation layer 50 has an at least first through hole 51 and at least 1 the
Two through-holes 52, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41 of the electrode group 40
The N-type electrode pad 411, so that the N-type electrode pad 411 is exposed on the first through hole 41, it is correspondingly, described blunt
Second through-hole 52 of change layer 50 corresponds to the P-type electrode pad 421 of the P-type electrode 42 of the electrode group 40,
So that the P-type electrode pad 421 is exposed on second through-hole 42.
Specifically, with reference to attached drawing 5A and Fig. 5 B, firstly, utilizing the vapour deposition process of plasma enhanced chemical
(Plasma Enhanced Chemical Vapor Deposition, PECVD) precipitates one layer of SiO2 (silica) in described
The p type semiconductor layer 14 of extension unit 10, the thickness range of SiO2 be 500 angstroms to 10000 angstroms (including 500 angstroms and 10000
Angstrom), the reaction gas used is SiH4 (silane), N2O (nitrous oxide) and N2 (nitrogen).Secondly, using positive photoresist photoetching
The structure of the passivation layer 30 out.Then, SiO2 is etched using the mode of wet etching to make the figure of the passivation layer 30,
Wherein etching solution is the mixed solution in hydrofluoric acid and ammonium fluoride.Finally, removing the photoresist, after the etch is completed to be formed
It is laminated in the passivation layer 50 of the p type semiconductor layer 14 of the extension unit 10, and the passivation layer 50 coats institute
State the N-type electrode 41 and the P-type electrode 42 of transparency conducting layer 30 and the electrode group 40, and the passivation layer 50
The first through hole 51 correspond to the N-type electrode pad 411 of the N-type electrode 41 of the electrode group 40 and described
Second through-hole 52 corresponds to the P-type electrode pad 421 of the P-type electrode 42 of the electrode group 40.
External power supply can the first through hole 51 through the passivation layer 50 and second through-hole 52 be respectively supplied to
The N-type electrode 41 and the P-type electrode 42 of the electrode group 40.Electric current can be through the N-type electricity of the N-type electrode 41
Pole pad 411 and N-type electrode extension item 412 inject the n type semiconductor layer 12 of the extension unit 10, wherein in institute
It states and has been kept the current barrier layer 20 between N-type electrode extension item 412 and the n type semiconductor layer 12, wherein the electricity
Flow barrier 20 can prevent current convergence in the lower part of N-type electrode extension item 412, so that electric current can around
It is injected into the n type semiconductor layer 12 evenly.Correspondingly, electric current can be through the P-type electrode pad of the P-type electrode 42
421 and every P-type electrode extension item 422 inject the transparency conducting layer 30 because every P-type electrode extends item
422 are laminated in the transparency conducting layer 30 and the p-type interdigital 4220 of every P-type electrode extension item 422 is protected respectively
These described perforation 31 in the transparency conducting layer 30 are held, so that electric current can be from the surface of the transparency conducting layer 30 and interior
Portion is uniformly injected into the transparency conducting layer 30 through P-type electrode extension item 422, and because in 30 He of transparency conducting layer
The current barrier layer 20 is maintained between the p type semiconductor layer 14, so that the current barrier layer 20 can prevent electric current
The lower part for concentrating on the P-type electrode extension item 422, partly leads so that electric current can be uniformly injected into around to the p-type
Body layer 14.It is uniformly implanted the electric current of the n type semiconductor layer 12 and is uniformly implanted the electricity of the p type semiconductor layer 14
Stream can be compound in the active area 13 and generates light, and such mode enables the brightness of the chip effective
Ground is promoted.
Attached drawing 6 shows a variant embodiment of the chip, and the chip shown in attached drawing 1A to Fig. 5 B is not
With in this preferable examples of the chip shown in attached drawing 6, the semiconductor bare portion 15 has a N
The exposed portion 151 of type electrode pad and a N-type electrode extend the exposed portion 152 of item, wherein the exposed portion of N-type electrode pad
151 are formed in the second end 102 of the chip, and the N-type electrode extension exposed portion 152 of item is at the middle part of the chip
101 side of the first end along the length direction of the chip from from the exposed portion 151 of the N-type electrode pad to the chip
To extension.
Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 includes one and is laminated in the N-type half
Conductor layer 12 and it is maintained at the N-type electrode pad 411 in the exposed portion 151 of the N-type electrode pad and one is laminated in institute
It states n type semiconductor layer 12 and is maintained at the N-type electrode extension item 412 in the N-type electrode extension exposed portion 152 of item,
Described in N-type electrode extension item 412 at the middle part of the chip along the length direction of the chip from the N-type electrode pad
411 extend to 101 direction of the first end of the chip.
With reference to attached drawing 6, the quantity of the current barrier layer 20 is two, and current barrier layer 20 is described in two of them with mutual
Symmetrical mode the edge of the chip along the chip length direction from the first end 101 of the chip to
102 direction of the second end extends.Subsequent, the transparency conducting layer is laminated in a manner of coating the current barrier layer 20
30 in the p type semiconductor layer 14, and the perforation 31 of the transparency conducting layer 30 corresponds respectively to the current blocking
Layer 20.Correspondingly, the transparency conducting layer 30 has the perforation 31 of two column, and wherein perforation 31 described in each column corresponds respectively to every
The different location of a current barrier layer 20.
Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one
The P-type electrode pad 421 of conductive layer 30 and two P-type electrodes extend item 422, wherein the P-type electrode pad 421
It is formed in the first end 101 of the chip, wherein each P-type electrode extension item 422 is respectively with symmetrical
Institute of the mode at the edge of the chip along the length direction of the chip from the P-type electrode pad 421 to the chip
The extension of 102 direction of the second end is stated, and the p-type interdigital 4220 of each P-type electrode extension item 422 is respectively formed in
Be maintained at each of described transparency conducting layer 30 it is described perforation 31.With reference to attached drawing 6, the N-type electricity of the N-type electrode 41
Pole extension item 412 is maintained between two P-type electrode extension items 422 of the P-type electrode 42.
With continued reference to attached drawing 6, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and
And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40
Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode
It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type
Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.
Attached drawing 7 shows another variant embodiment of the chip, the chip shown in attached drawing 1A to Fig. 5 B
Unlike, in this preferable examples of the chip shown in attached drawing 7, the semiconductor bare portion 15 has described in one
The exposed portion 151 of N-type electrode pad and three N-type electrodes extend the exposed portion 152 of item, wherein the N-type electrode pad is exposed
Portion 151 is formed in the second end 102 of the chip, wherein three N-type electrodes extension exposed portions 152 of item respectively by
It is defined as the exposed portion 152a of one first extension item, the exposed portion 152b of one second extension item and the third extension exposed portion of item
152c, wherein the first extension exposed portion 152a of item and the third extension exposed portion 152c of item are existed in symmetrical mode
The edge of the chip is along the length direction of the chip from the exposed portion 151 of the N-type electrode pad to the institute of the chip
The extension of 101 direction of first end is stated, the second extension exposed portion 152b of item is at the middle part of the chip along the chip
The first end 101 direction of the length direction from the exposed portion 151 of the N-type electrode pad to the chip extends.
Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 includes a N-type electrode pad
411 and three N-type electrodes extend items 412, wherein the N-type electrode pad 411 is laminated in 12 He of n type semiconductor layer
It is maintained at the exposed portion 151 of the N-type electrode pad, wherein three N-type electrode extensions article 412 are defined as one the oneth N
Type electrode extension 412a, one second N-type electrode extension 412b and a third N-type electrode extend a 412c, wherein described
First N-type electrode extends 412c points of a 412a, second N-type electrode extension 412b and third N-type electrode extension
It is not laminated in the n type semiconductor layer 12 and is respectively held in the exposed portion 152a of the first extension item, second extension
The exposed portion 152b of item and the third extend the exposed portion 152c of item, so that first N-type electrode extension 412a and institute
State length direction of the third N-type electrode extension 412c in symmetrical mode at the edge of the chip along the chip
101 direction of the first end from from the N-type electrode pad 411 to the chip extends, and second N-type electrode extends item
Institute of the 412b at the middle part of the chip along the length direction of the chip from the N-type electrode pad 411 to the chip
State the extension of 101 direction of first end.
With reference to attached drawing 7, the quantity of the current barrier layer 20 is two, and current barrier layer 20 is described in two of them with mutual
Symmetrical mode the middle part of the chip along the chip length direction from the first end 101 of the chip to
102 direction of the second end extends.Subsequent, the transparency conducting layer is laminated in a manner of coating the current barrier layer 20
30 in the p type semiconductor layer 14, and the perforation 31 of the transparency conducting layer 30 corresponds respectively to the current blocking
Layer 20.Correspondingly, the transparency conducting layer 30 has the perforation 31 of two column, and wherein perforation 31 described in each column corresponds respectively to every
A current barrier layer 20.
Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one
The P-type electrode pad 421 of conductive layer 30 and two P-type electrodes extend item 422, wherein each P-type electrode expands
It is electric from the p-type along the length direction of the chip at the middle part of the chip in symmetrical mode respectively to open up item 422
Pole pad 421 extends to 102 direction of the second end of the chip, and the institute of each P-type electrode extension item 422
It states p-type interdigital 4220 and is respectively formed in and is maintained at the perforation 31 of each of described transparency conducting layer 30.With reference to attached drawing 7,
The P-type electrode extension item 422 of one of the P-type electrode 42 is maintained at the first N-type electrode extension 412a and institute
It states between the second N-type electrode extension 412b, another described P-type electrode extension item 422 is maintained at second N-type electrode
It extends between a 412b and third N-type electrode extension 412c.
With continued reference to attached drawing 7, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and
And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40
Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode
It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type
Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.
Attached drawing 8 shows another variant embodiment of the chip, and the chip shown in from attached drawing 7 is different
It is that in this preferable examples of the chip shown in attached drawing 8, the semiconductor bare portion 15 has the N-type electricity
The exposed portion 151 of pole pad and two N-type electrodes extend the exposed portion 152 of item, wherein the exposed portion 151 of the N-type electrode pad
It is formed in the second end 102 of the chip, the two N-type electrode extension exposed portions 152 of item are with symmetrical side
Formula is at the edge of the chip along the length direction of the chip from the exposed portion 151 of the N-type electrode pad to the chip
101 direction of the first end extend.
Correspondingly, after the subsequent N-type electrode 41 forms, the N-type electrode 41 includes a N-type electrode pad
411 and two N-type electrodes extend items 412, wherein the N-type electrode pad 411 is laminated in 12 He of n type semiconductor layer
It is maintained at the exposed portion 151 of the N-type electrode pad, wherein each N-type electrode extension item 412 is respectively laminated on the N
Type semiconductor layer 12 extends the exposed portion 152 of item with each N-type electrode is maintained at, so that each N-type electrode
Extend item 412 in symmetrical mode at the edge of the chip along the length direction of the chip from the N-type electrode
Pad 411 extends to 101 direction of the first end of the chip.
With reference to attached drawing 8, the quantity of the current barrier layer 20 is one, wherein the current barrier layer 20 is in the chip
Middle part along the length direction of the chip from the first end 101 of the chip to 102 direction of the second end
Extend.Subsequent, the transparency conducting layer 30 is laminated in a manner of coating the current barrier layer 20 in the p type semiconductor layer
14, and the perforation 31 of the transparency conducting layer 30 corresponds to the current barrier layer 20.
Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one
The P-type electrode pad 421 of conductive layer 30 and a P-type electrode extend item 422, wherein the P-type electrode pad 421
It is formed in the first end 101 of the chip, the P-type electrode extension item 421 is at the middle part of the chip along described
The second end 102 direction of the length direction of chip from the P-type electrode pad 421 to the chip extends, and institute
The p-type interdigital 4220 for stating P-type electrode extension item 422 is formed in and is maintained at the perforation of the transparency conducting layer 30
31.With reference to attached drawing 8, the P-type electrode extension item 422 of the P-type electrode 42 is maintained at two institutes of the N-type electrode 41
It states between N-type electrode extension item 412.
With continued reference to attached drawing 8, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and
And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40
Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode
It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type
Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.
Attached drawing 9 shows another variant embodiment of the chip, and the chip shown in from attached drawing 8 is different
It is that in this preferable examples of the chip shown in attached drawing 9, the semiconductor bare portion 15 only has a N-type
The exposed portion 151 of electrode pad, is formed in the second end 102 of the chip.Correspondingly, in the subsequent N-type electrode
After 41 moldings, the N-type electrode 41 only includes a N-type electrode pad 411, wherein the N-type electrode pad 411 is laminated
In the n type semiconductor layer 12 and it is maintained at the exposed portion 151 of the N-type electrode pad.
With reference to attached drawing 9, the quantity of the current barrier layer 20 is one, wherein the current barrier layer 20 is in the chip
Middle part along the length direction of the chip from the first end 101 of the chip to 102 direction of the second end
Extend, subsequent, the transparency conducting layer 30 is laminated in a manner of coating the current barrier layer 20 in the p type semiconductor layer
14, and the perforation 31 of the transparency conducting layer 30 corresponds to the current barrier layer 20.
Correspondingly, after the subsequent P-type electrode 42 forms, the P-type electrode 42 is laminated in described transparent including one
The P-type electrode pad 421 of conductive layer 30 and a P-type electrode extend item 422, wherein the P-type electrode pad 421
It is formed in the first end 101 of the chip, the P-type electrode extension item 421 is at the middle part of the chip along described
The second end 102 direction of the length direction of chip from the P-type electrode pad 421 to the chip extends, and institute
The p-type interdigital 4220 for stating P-type electrode extension item 422 is formed in and is maintained at the perforation of the transparency conducting layer 30
31。
With continued reference to attached drawing 9, the passivation layer 50 is laminated in the p type semiconductor layer 14 of the extension unit 10, and
And the passivation layer 50 coats the N-type electrode 41 and p-type electricity of the transparency conducting layer 30 and the electrode group 40
Pole 42, wherein the first through hole 51 of the passivation layer 50 corresponds to the N-type electrode 41, so that 41 quilt of the N-type electrode
It is exposed to the first through hole 51 of the passivation layer 50, second through-hole 52 of the passivation layer 50 corresponds to the p-type
Electrode 42, so that the P-type electrode 42 is exposed on second through-hole 52 of the passivation layer 50.
According to the other side of the utility model, the utility model further provides for the manufacturing method of the chip, wherein
The manufacturing method includes the following steps:
(a) current barrier layer 20 is laminated in the p type semiconductor layer 14 of the extension unit 10;
(b) transparency conducting layer 30 is laminated in a manner of coating the current barrier layer 20 in the p type semiconductor layer
14, wherein the transparency conducting layer 30 has at least one described perforation 31, to correspond to the current barrier layer 20;And
(c) layer in such a way that the N-type electrode 41 is maintained at the semiconductor bare portion 15 of the extension unit 10
The N-type electrode 41 is folded in the n type semiconductor layer 12 of the extension unit 10, and with the p-type of the P-type electrode 42
Interdigital 4220 modes for being formed in the perforation 31 of the transparency conducting layer 30 are laminated the P-type electrode 42 and transparent lead in described
Electric layer 30, the chip is made.
Further, the manufacturing method comprising steps of
(d) passivation layer 50 is laminated in a manner of coating the N-type electrode 41 and the P-type electrode 42 in described transparent
Conductive layer 30 and the p type semiconductor layer 14, wherein the passivation layer 50 has described first corresponding to the N-type electrode 41
Channel 51 and the second channel 42 corresponding to the P-type electrode 52.
It is worth noting that, the substrate 11, the N-type half in the chip shown in the accompanying drawings of the utility model
Conductor layer 12, the active area 13, second semiconductor layer 14, the current barrier layer 20, the transparency conducting layer 30, institute
The thickness for stating N-type electrode 41 and the P-type electrode 42 is merely illustrative, is not offered as the substrate 11, the n type semiconductor layer
12, the active area 13, second semiconductor layer 14, the current barrier layer 20, the transparency conducting layer 30, the N-type
The actual thickness of electrode 41 and the P-type electrode 42.Also, the substrate 11, the n type semiconductor layer 12, the active area
13, second semiconductor layer 14, the current barrier layer 20, the transparency conducting layer 30, the N-type electrode 41 and the P
Actual proportions between type electrode 42 are also unlike shown in the accompanying drawings.In addition, the N-type electrode of the electrode group 40
41 and the P-type electrode 42 the size and chip other layers dimension scale be also not limited to it is shown in the accompanying drawings that
Sample.
It will be appreciated by those skilled in the art that above embodiments are only for example, wherein the feature of different embodiments
It can be combined with each other, do not explicitly pointed out in the accompanying drawings with obtaining being readily conceivable that according to the content that the utility model discloses
Embodiment.
It should be understood by those skilled in the art that foregoing description and the embodiments of the present invention shown in the drawings are only used as
It illustrates and is not intended to limit the utility model.The purpose of this utility model completely and effectively realizes.The function of the utility model
Energy and structural principle show and illustrate in embodiment, under without departing from the principle, the embodiments of the present invention
Can there are any deformation or modification.
Claims (13)
1. the chip of a light emitting diode characterized by comprising
One extension unit, wherein the extension unit include a substrate and the n type semiconductor layer successively grown from the substrate,
One active area and a p type semiconductor layer, wherein the extension unit has at least exposed portion of semiconductor, the semiconductor bare
Portion extends to the n type semiconductor layer through the active area from the p type semiconductor layer;
An at least current barrier layer, wherein the current barrier layer is laminated in the p type semiconductor layer of the extension unit;
One transparency conducting layer, wherein the transparency conducting layer is perforated at least one, wherein the transparency conducting layer is to coat
The mode for stating current barrier layer is laminated in the p type semiconductor layer, and the perforation of the transparency conducting layer corresponds to institute
State current barrier layer;And
One electrode group, wherein the electrode group include an at least N-type electrode and an at least P-type electrode, wherein the N-type electrode with
The mode for being formed in the semiconductor bare portion is laminated in the n type semiconductor layer, wherein the P-type electrode has an at least P
Type is interdigital, when the P-type electrode is laminated in the transparency conducting layer, the p-type of the P-type electrode is interdigital be formed in and by
It is maintained at the perforation of the transparency conducting layer.
2. chip according to claim 1, wherein the N-type electrode include be formed in the chip the second end one
N-type electrode pad and at least N-type electrode extension extended from the N-type electrode pad to the first end direction of the chip
Item, wherein the P-type electrode includes being formed in a P-type electrode pad of the first end of the chip and from the P-type electrode
At least two P-type electrodes that pad extends to the second end direction of the chip extend item, N-type electrode described in wherein at least one
Extension item is maintained between the two neighboring P-type electrode extension item.
3. chip according to claim 2, wherein the quantity of the N-type electrode extension item of the N-type electrode is one,
And the N-type electrode extension item extends at the middle part of the chip along the length direction of the chip, wherein the p-type is electric
The quantity of the P-type electrode extension item of pole is two, and two P-type electrode extension items are existed in symmetrical mode
The edge of the chip extends along the length direction of the chip.
4. chip according to claim 2, wherein the quantity of the N-type electrode extension item of the N-type electrode is two,
And the N-type electrode extension item extends at the middle part of the chip along the length direction of the chip, wherein the p-type is electric
The quantity of the P-type electrode extension item of pole is three, and respectively one first P-type electrode extends item, the extension of one second P-type electrode
Item and a third P-type electrode extend item, and the first P-type electrode extension item and third P-type electrode extension item are with mutual
Symmetrical mode extends at the edge of the chip along the length direction of the chip, and the second P-type electrode extension item exists
The middle part of the chip extends along the length direction of the chip, one of them described N-type electrode extension item is maintained at institute
It states between the first P-type electrode extension item and second P-type electrode extension item, another described N-type electrode extension item is kept
It is extended between item and third P-type electrode extension item in second P-type electrode.
5. chip according to claim 1, wherein the N-type electrode include be formed in the chip the second end one
N-type electrode pad and at least two N-type electrodes extension extended from the N-type electrode pad to the first end direction of the chip
Item, wherein the P-type electrode includes being formed in a P-type electrode pad of the first end of the chip and from the P-type electrode
At least P-type electrode that pad extends to the second end direction of the chip extends item, P-type electrode described in wherein at least one
Extension item is maintained between the two neighboring N-type electrode extension item.
6. chip according to claim 5, wherein the quantity of the N-type electrode extension item of the N-type electrode is two,
And two N-type electrode extension items are in symmetrical mode at the edge of the chip along the length side of the chip
To extension, wherein the quantity of the P-type electrode extension item of the P-type electrode is one, and P-type electrode extension item exists
The middle part of the chip extends along the length direction of the chip.
7. chip according to claim 5, wherein the quantity of the N-type electrode extension item of the N-type electrode is three,
Respectively one first N-type electrode extends item, one second N-type electrode extends item and third N-type electrode extension item, and described first
N-type electrode extend item and the third N-type electrode extension item in symmetrical mode at the edge of the chip along described
The length direction of chip extends, and the second N-type electrode extension item is at the middle part of the chip along the length side of the chip
To extension, wherein the quantity of the P-type electrode extension item of the P-type electrode is two, the extension of P-type electrode described in two of them
Item extends at the middle part of the chip along the length direction of the chip, one of them described P-type electrode extension item is kept
It is extended between item and second N-type electrode extension item in first N-type electrode, another described P-type electrode extends item quilt
It is maintained between the second N-type electrode extension item and third N-type electrode extension item.
8. chip according to claim 1, wherein the N-type electrode include be formed in the chip the second end one
N-type electrode pad, wherein the P-type electrode includes being formed in a P-type electrode pad of the first end of the chip and from institute
State the P-type electrode extension item that P-type electrode pad extends to the second end direction of the chip.
9. according to claim 1 to any chip in 8, wherein the quilt of the n type semiconductor layer of the extension unit
The surface for being exposed to the semiconductor bare portion is laminated at least one described current barrier layer, wherein the N-type electrode coats
It is laminated in the current barrier layer of the n type semiconductor layer.
10. chip according to claim 9, wherein being laminated in the current barrier layer of the n type semiconductor layer in item
It is band-like, extend along the length direction of the chip.
11. chip according to claim 9, wherein being laminated in the number of the current barrier layer of the n type semiconductor layer
Amount be it is multiple, these described current barrier layers are stripped to be extended along the length direction of the chip in a row, and in phase
There is spaced slot between adjacent two current barrier layers.
12. further comprising a passivation layer, wherein the passivation layer has according to claim 1 to any chip in 8
One first through hole and one second through-hole, wherein the passivation layer is laminated in a manner of coating the N-type electrode and the P-type electrode
In the p type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electricity
Second through-hole of pole, the passivation layer corresponds to the P-type electrode.
13. chip according to claim 9 further comprises a passivation layer, wherein the passivation layer has one first to lead to
Hole and one second through-hole, wherein the passivation layer is laminated in the P in a manner of coating the N-type electrode and the P-type electrode
Type semiconductor layer and the transparency conducting layer, and the first through hole of the passivation layer corresponds to the N-type electrode, it is described
Second through-hole of passivation layer corresponds to the P-type electrode.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201821130101.0U CN208478366U (en) | 2018-07-17 | 2018-07-17 | The chip of light emitting diode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201821130101.0U CN208478366U (en) | 2018-07-17 | 2018-07-17 | The chip of light emitting diode |
Publications (1)
Publication Number | Publication Date |
---|---|
CN208478366U true CN208478366U (en) | 2019-02-05 |
Family
ID=65211079
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201821130101.0U Active CN208478366U (en) | 2018-07-17 | 2018-07-17 | The chip of light emitting diode |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN208478366U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108831976A (en) * | 2018-07-17 | 2018-11-16 | 厦门乾照光电股份有限公司 | The chip and its manufacturing method of light emitting diode |
-
2018
- 2018-07-17 CN CN201821130101.0U patent/CN208478366U/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108831976A (en) * | 2018-07-17 | 2018-11-16 | 厦门乾照光电股份有限公司 | The chip and its manufacturing method of light emitting diode |
CN108831976B (en) * | 2018-07-17 | 2024-02-13 | 厦门乾照光电股份有限公司 | Light emitting diode chip and method for manufacturing the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN108831976A (en) | The chip and its manufacturing method of light emitting diode | |
JP5801791B2 (en) | Silicon solar cell having emitter with back-etching and method of forming similar solar cell | |
CN208596700U (en) | Semiconductor chip for light emitting diode | |
US9029188B2 (en) | Solar cell and method for manufacturing the same | |
US9070839B2 (en) | Method of manufacturing a light emitting diode | |
US11469349B2 (en) | Semiconductor chip of light emitting diode and manufacturing method thereof | |
CN103346227B (en) | A kind of gallium nitride LED chip and preparation method thereof | |
US20120326117A1 (en) | Semiconductor light emmiting device | |
CN103441196B (en) | Light-emitting component and its manufacture method | |
US20120094421A1 (en) | Method of manufacturing solar cell | |
CN106409994A (en) | AlGaInP based light emitting diode chip and manufacturing method thereof | |
CN100477423C (en) | Nitride semiconductor laser element and fabrication method thereof | |
CN106058003B (en) | A method of promoting LED chip brightness | |
CN106025012A (en) | Preparation method of LED chip and LED chip prepared by adopting method | |
CN105720155B (en) | A kind of Light-emitting diode LED and preparation method thereof | |
CN208478366U (en) | The chip of light emitting diode | |
CN110212069A (en) | Light-emitting diode chip for backlight unit and preparation method thereof | |
CN109192830A (en) | Semiconductor chip for light emitting diode | |
WO2023123756A1 (en) | Semiconductor light-emitting element and preparation method therefor, and led chip | |
CN104332532A (en) | Method for manufacturing high-luminous-efficiency light-emitting diode | |
CN110957405A (en) | LED chip and manufacturing method thereof | |
CN209709011U (en) | LED luminescence chip | |
JP2017216280A (en) | Group iii nitride semiconductor light-emitting device and method for manufacturing the same | |
US20210193871A1 (en) | Reduction in leakage current and increase in efficiency of iii-nitride leds by sidewall passivation using atomic layer deposition | |
JPH08255952A (en) | Fabrication of semiconductor light emission element |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |