CN208571230U - A kind of VCSEL chip for concentrating electric current injection - Google Patents
A kind of VCSEL chip for concentrating electric current injection Download PDFInfo
- Publication number
- CN208571230U CN208571230U CN201821526256.6U CN201821526256U CN208571230U CN 208571230 U CN208571230 U CN 208571230U CN 201821526256 U CN201821526256 U CN 201821526256U CN 208571230 U CN208571230 U CN 208571230U
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- vcsel chip
- current
- contact electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
This application discloses a kind of VCSEL chips of concentration electric current injection, the VCSEL chip for concentrating electric current injection is additionally provided with current convergence layer on epitaxial structure, current convergence layer cooperation is located at the insulating layer and electric connection layer of current convergence layer two sides, one is constituted from electrode structure-electrode concentrated layer-conductive structure-quantum well layer current path, and due to the orthographic projection of current convergence layer on substrate, in the orthographic projection of conductive structure on substrate, so that the current path formed is evenly distributed in conductive structure, avoid current convergence appearance the oxidation structure edge the case where, improve the current flow uniformity of VCSEL chip interior, so that the VCSEL chip for concentrating electric current injection can be realized the outgoing of single-mode optics.
Description
Technical field
This application involves laser chip technical fields, more specifically to a kind of VCSEL core of concentration electric current injection
Piece.
Background technique
Vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser) chip, also known as
VCSEL chip, be by the Laser emission chip based on gallium arsenide semiconductor material, have small in size, round output facula,
Single longitudinal mode output, threshold current it is small, cheap, easy of integration be large area array the advantages that, be widely applied it is mutual with optic communication, light
The fields such as company, optical storage.
The cross-section structure of VCSEL chip in the prior art refers to Fig. 1, mainly including gallium arsenide substrate 10 and positioned at arsenic
N-type DBR20 (Distributed Bragg Reflection, the Distributed Bragg Reflection stacked gradually on gallium substrate 10
Mirror), quantum well layer 30, limiting layer 40, p-type DBR50, gaas contact layer 60 and electrode structure 70, wherein limiting layer 40 includes
Conductive structure 41 and oxidation structure 42 positioned at 41 two sides of conductive structure, to play convergence electric current, to form Bulk current injection
The purpose of excitation laser in quantum well layer 30；Electrode structure 70 includes first electrode 71 and second electrode 72,71 He of first electrode
Second electrode 72 is located at the both ends of gaas contact layer 60, and the region between first electrode 71 and second electrode 72 is
The output optical zone domain of VCSEL chip.
In this VCSEL chip, with reference to Fig. 2, since electric current usually walks the smallest path of resistance, traditional
It in VCSEL chip, be easy to cause current convergence the oxidation structure edge the case where, generates multimode light so as to cause VCSEL chip,
It is difficult to realize the purpose of outgoing single-mode optics.
Utility model content
In order to solve the above technical problems, being avoided this application provides a kind of VCSEL chip of concentration electric current injection with realizing
There is the purpose of current convergence in VCSEL chip interior, improves the current flow uniformity of VCSEL chip interior, realize VCSEL chip
It is emitted the purpose of single-mode optics.
To realize the above-mentioned technical purpose, the embodiment of the present application provides following technical solution:
A kind of VCSEL chip for concentrating electric current injection, comprising:
Substrate；
Epitaxial structure on the substrate, the epitaxial structure include being located at the substrate surface to be cascading
Quantum well layer, limiting layer and contact electrode layer；The limiting layer includes conductive structure and positioned at the conductive structure two sides
Oxidation structure
Deviate from the one side of substrate positioned at the contact electrode layer, partially covers the current convergence of the contact electrode layer
Layer, the orthographic projection of the current convergence layer over the substrate, in the orthographic projection of the conductive structure over the substrate；
Positioned at current convergence layer two sides, exposed surface and part the electric current collection of the contact electrode layer are covered
The insulating layer of middle layer side wall；
Cover the electric connection layer of the insulating layer, the current convergence layer top surface and partial sidewall；
Deviate from the one side of substrate positioned at the electric connection layer, and part covers the electrode structure of the electric connection layer, institute
It states electric connection layer the contact electrode layer is not covered by the orthographic projection of region that the electrode structure covers over the substrate and exist
Orthographic projection on the substrate.
Optionally, the current convergence layer is gallium phosphide layer.
Optionally, the epitaxial structure further include:
The first type reflecting layer between the substrate and the quantum well layer；
Second type reflecting layer between the limiting layer and contact electrode layer.
Optionally, first type reflecting layer is N-type distributed bragg reflector mirror DBR layer；
The second type reflecting layer is p-type DBR layer.
Optionally, the contact electrode layer is gallium arsenide layer；
The conductive structure is aluminium arsenide structure；
The insulating layer is silicon nitride layer or silicon oxide layer；
The electric connection layer is indium tin oxide layer；
The substrate is gallium arsenide substrate.
It can be seen from the above technical proposal that the embodiment of the present application provides a kind of VCSEL chip of concentration electric current injection,
The VCSEL chip for concentrating electric current injection is additionally provided with current convergence layer on epitaxial structure, which matches coincidence
Insulating layer and electric connection layer in current convergence layer two sides constitute one from electrode structure-electrode concentrated layer-conduction knot
Structure-quantum well layer current path, and the orthographic projection due to current convergence layer on substrate are located at conductive structure in substrate
On orthographic projection in so that formed the current path be evenly distributed in conductive structure, avoid current convergence and aoxidizing
The case where structural edge, occurs, and improves the current flow uniformity of VCSEL chip interior, so that described concentrate electric current to inject
VCSEL chip can be realized the outgoing of single-mode optics.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is the schematic diagram of the section structure of VCSEL chip in the prior art；
Fig. 2 is the current path schematic diagram in VCSEL chip in the prior art；
Fig. 3 is that a kind of cross-section structure of the VCSEL chip for concentration electric current injection that one embodiment of the application provides shows
It is intended to；
Fig. 4 is the current path schematic diagram in VCSEL chip shown in Fig. 3；
Fig. 5 is a kind of preparation method of the VCSEL chip for concentration electric current injection that one embodiment of the application provides
Flow diagram；
Fig. 6-Figure 11 is a kind of preparation stream of the VCSEL chip for concentration electric current injection that one embodiment of the application provides
Journey schematic diagram；
Figure 12 is a kind of preparation method of the VCSEL chip for concentration electric current injection that another embodiment of the application provides
Flow diagram.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
The embodiment of the present application provides a kind of VCSEL chip of concentration electric current injection, as shown in Figure 3, comprising:
Substrate 100；
Epitaxial structure on the substrate 100, the epitaxial structure include being located at 100 surface of substrate successively layer
Quantum well layer 300, limiting layer 400 and the contact electrode layer 600 of folded setting；The limiting layer 400 includes conductive structure 410 and position
Oxidation structure 420 in 410 two sides of conductive structure
Deviate from 100 side of substrate positioned at the contact electrode layer 600, partially covers the contact electrode layer 600
Current convergence layer 710, orthographic projection of the current convergence layer 710 on the substrate 100 are located at the conductive structure 410 and exist
In orthographic projection on the substrate 100；
Positioned at 710 two sides of current convergence layer, cover described in exposed surface and the part of the contact electrode layer 600
The insulating layer of 710 side wall of current convergence layer；
Cover the electric connection layer 800 of the insulating layer, 710 top surface of current convergence layer and partial sidewall；
Deviate from 100 side of substrate positioned at the electric connection layer 800, and part covers the electricity of the electric connection layer 800
Pole structure 900, orthographic projection of the region that the electric connection layer 800 is not covered by the electrode structure 900 on the substrate 100
Cover orthographic projection of the contact electrode layer 600 on the substrate 100.
In Fig. 3, the electrode structure 900 includes first electrode 910 and second electrode 920.
With reference to Fig. 4, the current convergence layer 710 that VCSEL chip provided by the embodiments of the present application is arranged on epitaxial structure is matched
Insulating layer and electric connection layer 800 are closed, constitutes one from electrode structure 900 to electrode concentrated layer, then arrives conductive structure 410,
The current path of quantum well layer 300, and the orthographic projection due to current convergence layer 710 on substrate 100 are arrived again, are located at conductive knot
Structure 410, so that the current path formed is evenly distributed in conductive structure 410, avoids in the orthographic projection on substrate 100
Current convergence occurs in the case where 420 edge of oxidation structure, improves the current flow uniformity of VCSEL chip interior, to make
Obtaining the VCSEL chip for concentrating electric current injection can be realized the outgoing of single-mode optics.
Optionally, the current convergence layer 710 is gallium phosphide layer；
The contact electrode layer 600 is gallium arsenide layer；
The conductive structure 410 is aluminium arsenide structure；
The insulating layer is silicon nitride layer or silicon oxide layer；
The electric connection layer 800 is indium tin oxide layer；
The substrate 100 is gallium arsenide substrate 100.
The reason of current convergence layer 710 is prepared using gallium phosphide includes: that 1, gallium phosphide can be as contact electrode layer 600
Gallium arsenide layer on grow, and quality of forming film is good；2, gallium phosphide can be with tin indium oxide (Indium tin oxide, ITO)
Form good Ohmic contact；3, gallium phosphide has optical transparent properties, and the light that the excitation of quantum well layer 300 can be made to generate is logical
It crosses, reduces the absorption to light, promote the light utilization efficiency of VCSEL chip.
Referring still to Fig. 3, in order to further enhance the light extraction efficiency of VCSEL chip, the epitaxial structure further include:
The first type reflecting layer 200 between the substrate 100 and the quantum well layer 300；
Second type reflecting layer 500 between the limiting layer 400 and contact electrode layer 600.
Wherein, first type reflecting layer 200 is N-type distributed bragg reflector mirror DBR layer；
The second type reflecting layer 500 is p-type DBR layer.
In the specific embodiment of the application, N-type DBR layer includes the reflector element of 32 stacked arrangements, p-type DBR
Layer includes the reflector element of 20 stacked arrangements, and the reflector element includes one layer of aluminium arsenide layer and one layer of arsenide layers, often
The relationship of the wavelength of the light of thickness and VCSEL the chip outgoing of a reflector element are as follows: the thickness of reflector element=VCSEL chip
The a quarter of the wavelength of the light of outgoing.The quantum well layer 300 includes the Quantum Well unit of three stackings, to keep high collection
In electric current injection.The value range of the thickness of gallium arsenide layer and gallium phosphide layer is 10nm-20nm, to realize gallium arsenide layer and phosphorus
Change the better Ohmic contact of gallium layer.
Correspondingly, such as scheming the embodiment of the present application also provides a kind of preparation method of the VCSEL chip of concentration electric current injection
Shown in 5, comprising:
S101: substrate is provided；
S102: quantum well layer, conductive structure layer and contact electrode layer, the conductive structure are sequentially formed over the substrate
Layer covers the quantum well layer；The diagrammatic cross-section of substrate and its surface texture after step S102 refers to Fig. 6, in Fig. 6
Label 100 indicate substrate, 300 indicate quantum well layers, 410 indicate conductive structure layers, 600 indicate contact electrode layers, in Fig. 6
Also show the first type reflecting layer 200 between the substrate and the quantum well layer；
Second type reflecting layer 500 between conductive structure layer and contact electrode layer.
Wherein, first type reflecting layer is N-type distributed bragg reflector mirror DBR layer；
The second type reflecting layer is p-type DBR layer.
First type reflecting layer and second type reflecting layer can further promote the light extraction efficiency of VCSEL chip.
S103: carrying out oxidation processes to the conductive structure layer, and the both ends of conductive structure layer are aoxidized to form oxidation knot
Structure layer, the oxidation structure layer and the remaining conductive structure layer are construed as limiting layer, the quantum well layer, limiting layer and electrode
Contact layer constitutes epitaxial structure；The schematic diagram of the section structure of substrate and its surface texture after step S103 refers to Fig. 7；Figure
Label 420 indicates the oxidation structure layer in 7, and 400 indicate the limiting layer.
S104: current convergence layer, current convergence layer part are formed away from the one side of substrate in the epitaxial structure
The contact electrode layer is covered, the orthographic projection of the current convergence layer over the substrate is located at the conductive structure described
In orthographic projection on substrate；The specific execution step of step S104 refers to Fig. 8 and Fig. 9；Label 710 in Fig. 8 and Fig. 9 indicates institute
State current convergence layer.
S105: it is formed and is located at current convergence layer two sides, cover exposed surface and the part of the contact electrode layer
The insulating layer of the current convergence layer side wall；The schematic diagram of the section structure of substrate and its surface texture after step S105 is joined
Examine Figure 10；In Figure 10, label 700 indicates the insulating layer.
S106: the electric connection layer for covering the insulating layer, the current convergence layer top surface and partial sidewall is formed；By
The schematic diagram of the section structure of substrate and its surface texture after step S106 refers to Figure 11；In Figure 11, label 800 indicates the electricity
Articulamentum.
S107: it is formed and is located at the electric connection layer away from the one side of substrate, and part covers the electricity of the electric connection layer
Pole structure, the orthographic projection of the region that the electric connection layer is not covered by the electrode structure over the substrate cover the electrode
The orthographic projection of contact layer over the substrate.The schematic diagram of the section structure of substrate and its surface texture after step S106 is joined
Fig. 3 is examined, label 900 indicates the electrode structure in Fig. 3, which includes first electrode 910 and second electrode 920.
The cross-section structure for the VCSEL chip that the preparation method of VCSEL chip provided by the embodiments of the present application prepares is joined
Examine Fig. 4, the current convergence layer that the VCSEL chip for concentrating electric current injection is arranged on epitaxial structure, coordinated insulation layer and
Electric connection layer constitutes one from electrode structure to electrode concentrated layer, then arrives conductive structure, then logical to the electric current of quantum well layer
Road, and the orthographic projection due to current convergence layer on substrate, in the orthographic projection of conductive structure on substrate, so that being formed
The current path be evenly distributed in conductive structure, avoid current convergence appearance the oxidation structure edge the case where, mention
The high current flow uniformity of VCSEL chip interior, so that the VCSEL chip for concentrating electric current injection can be realized single mode
The outgoing of light.
Optionally, the current convergence layer is gallium phosphide layer；
The contact electrode layer is gallium arsenide layer；
The conductive structure is aluminium arsenide structure；
The insulating layer is silicon nitride layer or silicon oxide layer；
The electric connection layer is indium tin oxide layer；
The substrate is gallium arsenide substrate.
The reason of current convergence layer is prepared using gallium phosphide includes: that 1, gallium phosphide can be in the arsenic as contact electrode layer
It is grown on gallium layer, and quality of forming film is good；2, gallium phosphide can be formed good with tin indium oxide (Indium tin oxide, ITO)
Good Ohmic contact；3, gallium phosphide has optical transparent properties, and the light that quantum well layer excitation can be made to generate passes through, reduction pair
The absorption of light promotes the light utilization efficiency of VCSEL chip.
In the specific embodiment of the application, N-type DBR layer includes the reflector element of 32 stacked arrangements, p-type DBR
Layer includes the reflector element of 20 stacked arrangements, and the reflector element includes one layer of aluminium arsenide layer and one layer of arsenide layers, often
The relationship of the wavelength of the light of thickness and VCSEL the chip outgoing of a reflector element are as follows: the thickness of reflector element=VCSEL chip
The a quarter of the wavelength of the light of outgoing.The quantum well layer includes the Quantum Well unit of three stackings, is concentrated with keeping high
Electric current injection.The value range of the thickness of gallium arsenide layer and gallium phosphide layer is 10nm-20nm, to realize gallium arsenide layer and phosphatization
The better Ohmic contact of gallium layer.
On the basis of the above embodiments, in the alternative embodiment of the application, as shown in figure 12, the concentration electricity
The preparation method of VCSEL chip for flowing injection includes:
S201: substrate is provided；
S202: quantum well layer, conductive structure layer and contact electrode layer, the conductive structure are sequentially formed over the substrate
Layer covers the quantum well layer；
S203: wet oxidation process is carried out to the conductive structure, the both ends of conductive structure layer are aoxidized to form oxidation
Structure sheaf, the oxidation structure layer and the remaining conductive structure layer are construed as limiting layer, the quantum well layer, limiting layer and electricity
Pole contact layer constitutes epitaxial structure；
S204: the overlay area of the orthographic projection of the conductive structure over the substrate is measured；
S205: forming the current convergence layer for covering the contact electrode layer, and perform etching to the current convergence layer, with
Make the orthographic projection of the current convergence layer remained over the substrate, positioned at the positive throwing of the conductive structure over the substrate
In shadow, the implementation procedure of step S205 refers to Fig. 8 and Fig. 9；
S206: it is formed and is located at current convergence layer two sides, cover exposed surface and the part of the contact electrode layer
The insulating layer of the current convergence layer side wall；
S207: the electric connection layer for covering the insulating layer, the current convergence layer top surface and partial sidewall is formed；
S208: it is formed and is located at the electric connection layer away from the one side of substrate, and part covers the electricity of the electric connection layer
Pole structure, the orthographic projection of the region that the electric connection layer is not covered by the electrode structure over the substrate cover the electrode
The orthographic projection of contact layer over the substrate.
Wherein, step S205 is specifically included:
Form the gallium phosphide layer for covering the contact electrode layer；
The gallium phosphide layer is performed etching, so that the orthographic projection of the gallium phosphide layer remained over the substrate, position
In the orthographic projection of the conductive structure over the substrate.
In conclusion the embodiment of the present application provides a kind of VCSEL chip of concentration electric current injection, the concentration electric current note
The VCSEL chip entered is additionally provided with current convergence layer on epitaxial structure, and current convergence layer cooperation is located at current convergence layer two
The insulating layer and electric connection layer of side constitute one from electrode structure-electrode concentrated layer-conductive structure-quantum well layer
Current path, and the orthographic projection due to current convergence layer on substrate make in the orthographic projection of conductive structure on substrate
The current path that must be formed is evenly distributed in conductive structure, is avoided current convergence and is gone out in the case where oxidation structure edge
It is existing, the current flow uniformity of VCSEL chip interior is improved, so that the VCSEL chip for concentrating electric current injection can be realized list
The outgoing of mould light.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (5)
1. a kind of VCSEL chip for concentrating electric current injection characterized by comprising
Substrate；
Epitaxial structure on the substrate, the epitaxial structure include the amount being cascading positioned at the substrate surface
Sub- well layer, limiting layer and contact electrode layer；The limiting layer includes conductive structure and the oxidation positioned at the conductive structure two sides
Structure
Deviate from the one side of substrate positioned at the contact electrode layer, partially covers the current convergence layer of the contact electrode layer, institute
The orthographic projection of current convergence layer over the substrate is stated, in the orthographic projection of the conductive structure over the substrate；
Positioned at current convergence layer two sides, exposed surface and part the current convergence layer of the contact electrode layer are covered
The insulating layer of side wall；
Cover the electric connection layer of the insulating layer, the current convergence layer top surface and partial sidewall；
Deviate from the one side of substrate positioned at the electric connection layer, and part covers the electrode structure of the electric connection layer, the electricity
The orthographic projection of the region that articulamentum is not covered by the electrode structure over the substrate covers the contact electrode layer described
Orthographic projection on substrate.
2. the VCSEL chip according to claim 1 for concentrating electric current injection, which is characterized in that the current convergence layer is
Gallium phosphide layer.
3. the VCSEL chip according to claim 1 for concentrating electric current injection, which is characterized in that the epitaxial structure also wraps
It includes:
The first type reflecting layer between the substrate and the quantum well layer；
Second type reflecting layer between the limiting layer and contact electrode layer.
4. the VCSEL chip according to claim 3 for concentrating electric current injection, which is characterized in that first type reflecting layer
For N-type distributed bragg reflector mirror DBR layer；
The second type reflecting layer is p-type DBR layer.
5. the VCSEL chip according to claim 1 for concentrating electric current injection, which is characterized in that the contact electrode layer is
Gallium arsenide layer；
The conductive structure is aluminium arsenide structure；
The insulating layer is silicon nitride layer or silicon oxide layer；
The electric connection layer is indium tin oxide layer；
The substrate is gallium arsenide substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821526256.6U CN208571230U (en) | 2018-09-18 | 2018-09-18 | A kind of VCSEL chip for concentrating electric current injection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821526256.6U CN208571230U (en) | 2018-09-18 | 2018-09-18 | A kind of VCSEL chip for concentrating electric current injection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN208571230U true CN208571230U (en) | 2019-03-01 |
Family
ID=65451757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201821526256.6U Active CN208571230U (en) | 2018-09-18 | 2018-09-18 | A kind of VCSEL chip for concentrating electric current injection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN208571230U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309344A (en) * | 2018-09-18 | 2019-02-05 | 厦门乾照半导体科技有限公司 | A kind of VCSEL chip and preparation method thereof for concentrating electric current injection |
-
2018
- 2018-09-18 CN CN201821526256.6U patent/CN208571230U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309344A (en) * | 2018-09-18 | 2019-02-05 | 厦门乾照半导体科技有限公司 | A kind of VCSEL chip and preparation method thereof for concentrating electric current injection |
| CN109309344B (en) * | 2018-09-18 | 2023-11-28 | 厦门乾照半导体科技有限公司 | VCSEL chip with concentrated current injection and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP6722221B2 (en) | Light emitting diode | |
| CN104319325B (en) | A kind of reddish yellow light-emitting diode and preparation method thereof | |
| EP2720327A1 (en) | Hybrid vertical cavity laser for photonic integrated circuit | |
| JP7107849B2 (en) | Semiconductor device manufacturing method | |
| CN110620169B (en) | Transverse current limiting high-efficiency light-emitting diode based on resonant cavity | |
| CN108767656A (en) | Coherent source component | |
| CN101471541A (en) | Method for making laminated travelling wave electroabsorption modulation laser with epitaxial selection region | |
| CN110197992A (en) | A kind of efficient VCSEL chip and its manufacturing method | |
| CN101316027A (en) | Production method of quantum well edge-emission semiconductor laser | |
| CN110011181A (en) | Transistor vertical cavity surface emitting lasers and preparation method thereof | |
| JP6911111B2 (en) | Manufacturing method of optoelectronic semiconductor chip and optoelectronic semiconductor chip | |
| CN208571230U (en) | A kind of VCSEL chip for concentrating electric current injection | |
| KR101431306B1 (en) | Method for producing a radiation-emitting component and radiation-emitting component | |
| CN103986063B (en) | A kind of longitudinal mode semiconductor laser based on bandpass filtering structure | |
| CN107681026B (en) | A kind of light emitting diode and preparation method thereof | |
| JP2004281559A (en) | Semiconductor light emitting device | |
| CN108879328A (en) | A kind of VCSEL chip of improving laser gain and preparation method thereof | |
| CN110197993B (en) | VCSEL chip with high recombination efficiency and manufacturing method thereof | |
| CN109309344A (en) | A kind of VCSEL chip and preparation method thereof for concentrating electric current injection | |
| JP5717640B2 (en) | Optoelectronic semiconductor chip and method of manufacturing optoelectronic semiconductor chip | |
| CN103401140A (en) | Semiconductor laser with novel cavity surface non-injection area window structure | |
| JP2021072299A (en) | Semiconductor optical element | |
| US20150249318A1 (en) | Non-evanescent hybrid laser | |
| KR20080098574A (en) | Long wavelength vertical cavity surface emitting laser device and method for fabricating the same | |
| CN209608089U (en) | Transistor vertical cavity surface emitting lasers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |