CN110011181A - Transistor vertical cavity surface emitting lasers and preparation method thereof - Google Patents
Transistor vertical cavity surface emitting lasers and preparation method thereof Download PDFInfo
- Publication number
- CN110011181A CN110011181A CN201910437330.XA CN201910437330A CN110011181A CN 110011181 A CN110011181 A CN 110011181A CN 201910437330 A CN201910437330 A CN 201910437330A CN 110011181 A CN110011181 A CN 110011181A
- Authority
- CN
- China
- Prior art keywords
- emitter
- vertical cavity
- emitting lasers
- emitter region
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 32
- 239000012528 membrane Substances 0.000 claims abstract description 29
- 229910052593 corundum Inorganic materials 0.000 claims abstract description 24
- 229910001845 yogo sapphire Inorganic materials 0.000 claims abstract description 24
- 239000000126 substance Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 230000000737 periodic effect Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 15
- 238000005137 deposition process Methods 0.000 claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 238000009279 wet oxidation reaction Methods 0.000 description 5
- 238000001451 molecular beam epitaxy Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000011265 semifinished product Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
- H01S5/18369—Structure of the reflectors, e.g. hybrid mirrors based on dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
- H01S5/18377—Structure of the reflectors, e.g. hybrid mirrors comprising layers of different kind of materials, e.g. combinations of semiconducting with dielectric or metallic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
- H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
The invention discloses a kind of transistor vertical cavity surface emitting lasers, substrate, lower end surface distributed bragg reflector mirror, collecting zone, base area, emitter region, the upper surface distributed bragg reflector mirror successively arranged including the order according to epitaxial growth, and the electrode be connected respectively with collecting zone, base area, emitter region: collector, base stage, emitter；Quantum well active district is provided in the base area；Surface region on base area, emitter region, upper surface distributed bragg reflector mirror except for the electrodes is coated with Al2O3Protective film, and the upper surface distributed bragg reflector mirror is by Al2O3Membrane structure and at least one other dielectric substance membrane structure are in the sub-wavelength high contrast grating that periodic arrangement is constituted.The invention also discloses the preparation methods of above-mentioned transistor vertical cavity surface emitting lasers.The present invention also reduces the technology difficulty of device manufacture while greatly improving the reliability of T-VCSEL device.
Description
Technical field
The present invention relates to a kind of transistor vertical cavity surface emitting lasers (Transistor Vertical-Cavity
Surface-Emitting Laser, abbreviation T-VCSEL), belong to integrated opto-electronic device technical field.
Background technique
Photoelectric device and the development trend that System on Chip/SoC is extensive, singualtion is integrated, propose chip of laser performance
Diversified high request needs novel chip of laser to have both low-power consumption, big bandwidth in the application scenarios of optic communication and 5G
The characteristics of.For the straight tune bandwidth bottleneck that conventional vertical cavity surface emitting lasers (VCSEL) face, it will equally be based on iii-v
Transistor (Transistor) structure and VCSEL design combine together, theoretically can be based on the high bandwidth of operation of transistor
Realize that VCSEL directly adjusts the promotion of bandwidth.1980, integrated optoelectronics founder, California Institute of Technology prominent professors A.Yariv
Deng just hetero-junction bipolar transistor (HBT) and edge-emission semiconductor laser are integrated on same chip.By two kinds of devices
Part structure fusion, using transistor base as the active area of laser, explores novel transistor laser (T- to together
Laser trial) starts from 1985.2004, Illinois, America found college professor, the inventor N. Holonyak of LED
It is put forward for the first time the base region that Quantum well active district is introduced to GaAs material HBT, and was obtained under first room temperature in 2005 and has light
The T-laser of output.Compared with T-laser, it is peculiar that transistor vertical cavity surface emitting lasers (T-VCSEL) inherit VCSEL
Such as circular exit light beam be easy to couple, threshold current is low, detects on supporting pieces, it is easy to accomplish two-dimensional array, production cost
The advantages such as cheap theoretically have higher modulation bandwidth, are the trend of VCSEL future development evolution compared with traditional VCSEL
One of.
The main challenge of high-performance VCSEL industrialization field face at present includes following three aspect:
1. how to realize the exact growth of up to a hundred layers of epitaxial structure of VCSEL；
2. how to realize the accurate control of on piece electrical confined aperture size；
3. how to solve the integrity problem of VCSEL device under the conditions of non-hermetically sealed encapsulation.
T-VCSEL will certainly equally encounter above-mentioned three while inheriting VCSEL advantage in the process of Mirae Corp.
The technical problem of aspect.
Summary of the invention
Technical problem to be solved by the present invention lies in overcoming the shortcomings of the prior art, it is vertical to provide a kind of transistor
Straight cavity surface-emitting laser and preparation method thereof also reduces device while greatly improving the reliability of T-VCSEL device
The technology difficulty of manufacture.
The present invention specifically uses following technical scheme to solve above-mentioned technical problem:
A kind of transistor vertical cavity surface emitting lasers, the substrate successively arranged including the order according to epitaxial growth, lower end surface
Distributed bragg reflector mirror, collecting zone, base area, emitter region, upper surface distributed bragg reflector mirror, and respectively with current collection
The electrode that area, base area, emitter region are connected: collector, base stage, emitter；Quantum well active district is provided in the base area；In base
Area, emitter region, the surface region on the distributed bragg reflector mirror of upper surface except for the electrodes are coated with Al2O3Protective film, and
And the upper surface distributed bragg reflector mirror is by Al2O3Membrane structure is in at least one other dielectric substance membrane structure
The sub-wavelength high contrast grating that periodic arrangement is constituted.
Further, the emitter region include one layer with atom layer deposition process be prepared by Al2O3The electricity constituted
Ductility limit preparative layer, the current-limiting layer middle part are provided with the current-confining apertures passed through for electric current.
Further, the Al2O3Protective film and Al2O3Membrane structure is prepared using atom layer deposition process.
Preferably, other dielectric substance membrane structures include SiO2Membrane structure, Si3N4Membrane structure and amorphous Si film
Structure.
The transistor vertical cavity surface emitting lasers can be GaAs base or InP-base or GaN base transistor vertical chamber
Surface-emitting laser.
Preferably, the collector is set to the back side of substrate.
The preparation method of transistor vertical cavity surface emitting lasers as described above, comprising the following steps:
Step 1, on substrate successively epitaxial growth with understructure: lower end surface distributed bragg reflector mirror, collecting zone, base
Area, emitter region；
The electrode that step 2, preparation are connected with collecting zone, base area, emitter region respectively: collector, base stage, emitter；
Step 3, other dielectric substance membrane structures that the sub-wavelength high contrast grating is constituted in the preparation of emitter region upper surface；
Step 4 prepares Al on base area, emitter region, upper surface distributed bragg reflector mirror surface2O3Film；
Step 5, the Al that electrode surface will be covered on2O3Film removal.
Preferably, during epitaxial growth emitter region, emitter layer structure is carried out first in base layer structure
Then first time epitaxial growth removes the surface layer of peripheral part emitter layer structure, then with atom layer deposition process in institute
It states peripheral part emitter layer body structure surface and carries out Al2O3Regrowth, finally sent out on the surface of entire emitter layer structure
Penetrate second of epitaxial growth of region layer structure.
Preferably, the electrode is prepared using metal evaporation technique in step 2；Plasma enhancing is used in step 3
Learn other dielectric substance membrane structures that vapour deposition process preparation constitutes the sub-wavelength high contrast grating；It is used in step 5
Reactive ion etching process will be covered on the Al of electrode surface2O3Film removal.
Compared with prior art, technical solution of the present invention has the advantages that
The present invention by improving to T-VCSEL structure, adopt by upper surface distributed bragg reflector mirror (Top-DBR) therein
With by including Al2O3Sub-wavelength high contrast grating (HCG) design that a variety of dielectric substance membrane structures inside are constituted, together
When use Al2O3Film is to the surface district on base area, emitter region, upper surface distributed bragg reflector mirror (Top-DBR) except for the electrodes
Domain is coated, and alumina material therein is both one of dielectric substance for constituting HCG and entire device chip
Moisture-resistant protective film, to can greatly improve the reliability of device chip, further, since the Al in HCG2O3Membrane structure and whole
The Al of body2O3Protective film can be prepared simultaneously, so as to effectively reduce process flow, reduce production cost.
The present invention realizes current-limiting layer institute using the process of the high aluminium layer of wet oxidation further directed to existing T-VCSEL
The defects of bring electrical confined aperture is difficult to control accurately, and the material stress of introducing is excessive, using atomic layer deposition (ALD) work
Skill not only realizes the accurate of full wafer chip upper limiting layer aperture by the scheme of regrowth to carry out the preparation of current-limiting layer
Control, it is small that the alumina layer of ALD technique growth also possesses stress, and compactness is high, the advantage of film thickness controllable precise.In addition, oxidation
Aluminium is also beneficial to the limitation of optical mode field relative to the low-refraction feature of III-V material.
Detailed description of the invention
Fig. 1 is the principle schematic diagram of first preferred embodiment of T-VCSEL of the present invention, is collector and transmitting
The coplanar positive-negative-positive structure of pole, base stage；
Fig. 2 is the principle schematic diagram of second preferred embodiment of T-VCSEL of the present invention, be collector and emitter,
The coplanar NPN type structure of base stage；
Fig. 3 is the principle schematic diagram of the third preferred embodiment of T-VCSEL of the present invention, for collector and emitter,
The positive-negative-positive structure of base stage antarafacial；
Fig. 4 is the principle schematic diagram of the 4th preferred embodiment of T-VCSEL of the present invention, be collector and emitter,
The NPN type structure of base stage antarafacial；
Fig. 5 is the structural schematic diagram of Top-DBR used in the present invention；
Fig. 6 a~Fig. 6 h is the flow diagram of one specific embodiment of preparation method of the present invention.
Specific embodiment
For integrity problem of existing T-VCSEL device under the conditions of non-hermetically sealed encapsulation, resolving ideas of the invention is
Use Al2O3Film coats the surface region on base area, emitter region, upper surface distributed bragg reflector mirror except for the electrodes,
And using by including Al2O3The sub-wavelength high contrast grating that a variety of dielectric substance membrane structures inside are constituted is as Top-
DBR, alumina material therein are both the moisture-resistant of one of dielectric substance for constituting HCG and entire device chip
Protective film, to can greatly improve the reliability of device chip, further, since the Al in HCG2O3Membrane structure and entirety
Al2O3Protective film can be prepared simultaneously, so as to effectively reduce process flow, reduce production cost.
Specifically, transistor vertical cavity surface emitting lasers of the invention, successively including the order according to epitaxial growth
Substrate, lower end surface distributed bragg reflector mirror, collecting zone, base area, emitter region, the upper surface Distributed Bragg Reflection of arrangement
Mirror, and the electrode be connected respectively with collecting zone, base area, emitter region: collector, base stage, emitter；It is provided in the base area
Quantum well active district (it should be noted that: " Quantum well active district is set to base area " is that T-VCSEL is different from other types
The intrinsic characteristics of laser device, any structure that Quantum Well is placed in emitter region or collecting zone are all not belonging to transistor VCSEL
Definition scope)；Surface region on base area, emitter region, upper surface distributed bragg reflector mirror except for the electrodes is wrapped
It is covered with Al2O3Protective film, and the upper surface distributed bragg reflector mirror is by Al2O3Membrane structure with it is at least one other
Dielectric substance membrane structure is in the sub-wavelength high contrast grating that periodic arrangement is constituted.
The preparation method of transistor vertical cavity surface emitting lasers as described above, comprising the following steps:
Step 1, on substrate successively epitaxial growth with understructure: lower end surface distributed bragg reflector mirror, collecting zone, base
Area, emitter region；
The electrode that step 2, preparation are connected with collecting zone, base area, emitter region respectively: collector, base stage, emitter；
Step 3, other dielectric substance membrane structures that the sub-wavelength high contrast grating is constituted in the preparation of emitter region upper surface；
Step 4 prepares Al on base area, emitter region, upper surface distributed bragg reflector mirror surface2O3Film；
Step 5, the Al that electrode surface will be covered on2O3Film removal.
There are many conceptual designs for current-limiting layer in existing T-VCSEL design, wherein most mainstream is using oxide
Material (such as aluminium oxide), and the process of the AlGaAs layer using wet oxidation high aluminium content without exception is realized.It is such
Implementation method can not only introduce significant material stress, be unfavorable for life of product；More important is wet oxidation process at present can not
The size of accurate control electrical confined aperture and the aperture consistency of full wafer chip.To solve this problem, the present invention abandons
Traditional wet oxidation preparation process, and the preparation of current-limiting layer is carried out using ald (ALD) technique, by again
The scheme of growth, not only realizes the accurate control in full wafer chip upper limiting layer aperture, and the alumina layer of ALD technique growth also possesses
Stress is small, and compactness is high, the controllable advantage of film thickness.To realize this scheme, correspondingly, in the process of epitaxial growth emitter region
In, the first time epitaxial growth of emitter layer structure is carried out first in base layer structure, then by peripheral part emitter layer
The surface layer of structure removes, and is then prepared with atom layer deposition process and carries out Al in the peripheral part emitter layer body structure surface2O3
Regrowth, finally entire emitter layer structure surface carry out emitter layer structure second of epitaxial growth.
Similar with transistor arrangement, T-laser and T-VCSEL include two kinds of structure types of PNP and NPN.It is sent out in the former
Penetrating area and collecting zone is P-type material, and base area is n type material；Emitter region and collecting zone are n type material in the latter, and base area is p-type material
Material.Structure most of existing T-VCSEL coplanar with emitter, base stage using collector, while there is also collectors in chip
The back side (back side of substrate), the i.e. structure with emitter, base stage antarafacial.Since technical solution of the present invention only relates to Top-DBR
And the structure and process modification of current-limiting layer, therefore its T-VCSEL either to PNP and NPN type, or to collector
The structure of coplanar or collector and emitter, base stage antarafacial, applicable with emitter, base stage.In addition, technical solution of the present invention
The T-VCSEL of existing various different materials systems is applicable in, such as GaAs base (GaAs), indium phosphide (InP), nitrogen
Change the T-VCSEL of material systems such as gallium base (GaN).
For convenient for public understanding, technical solution of the present invention is described in detail with reference to the accompanying drawing:
FIG. 1 to FIG. 4 shows the basic structure of four preferred embodiments of T-VCSEL of the present invention, wherein Fig. 1 be collector with
The coplanar positive-negative-positive structure of emitter, base stage, Fig. 2 are the collector NPN type structure coplanar with emitter, base stage, and Fig. 3 is current collection
The positive-negative-positive structure of pole and emitter, base stage antarafacial, Fig. 4 are the NPN type structure of collector and emitter, base stage antarafacial.Such as Fig. 1
Shown in~Fig. 4, T-VCSEL of the invention is same as the prior art, includes the lining successively arranged according to the order of epitaxial growth
Bottom, lower end surface distributed bragg reflector mirror, collecting zone, base area, emitter region, upper surface distributed bragg reflector mirror, and
The electrode be connected respectively with collecting zone, base area, emitter region: collector, base stage, emitter；Quantum Well is provided in the base area
Active area.
Unlike the prior art, the base area of T-VCSEL of the invention, emitter region, on Top-DBR except for the electrodes
Surface region is coated with Al2O3Protective film has the function that protective film so that the isolation of external portion's steam can be realized, improves core
The reliability of piece.Meanwhile the Top-DBR in T-VCSEL of the present invention uses structure as shown in Figure 5, i.e., by Al2O3Membrane structure with
At least one other dielectric substance (such as SiO2、Si3N4Or amorphous Si) membrane structure is in the sub- wave that is constituted of periodic arrangement
Long high contrast grating, by adjusting the size design of pellumina structure and other dielectric substance membrane structure (in Fig. 5
W1、W2、d1、d2Etc. parameters), can be realized to it is specific outgoing wavelength high reflectance support.Due to Al2O3It is both Top-DBR's
Component part be again the entire base area of package, emitter region, Top-DBR protective film, therefore can disposably be prepared, so as to have
Effect reduces process flow, reduces production cost.In addition, preparing current-limiting layer not using wet oxidation process with existing T-VCSEL
Together, Al of the invention2O3Material current limiting layer is prepared with atom layer deposition process, and wherein electric current on the one hand may be implemented
The accurate control of pore size is limited, on the other hand Al generated2O3It is small that current-limiting layer also possesses stress, and compactness is high, film thickness
The advantage of controllable precise.
Below by taking the positive-negative-positive T-VCSEL of the coplanar electrodes based on GaAs (GaAs) material as an example, it is specifically described the present invention
The manufacturing method thereof of T-VCSEL, the epitaxial growth of entire device can both be prepared by metal-organic chemical vapor deposition equipment (MOCVD),
Also it is prepared by molecular beam epitaxy system (MBE), a length of 980nm of outgoing wave, the optical thickness of entire resonant cavity is outgoing half-wavelength
Integral multiple, each layer optical thickness of lower end surface DBR be a quarter outgoing wavelength integral multiple, concrete technology flow process is such as
Under:
1, (layer 1) grows Intrinsical lower end surface DBR on the GaAs substrate that semi-insulating or p-type is adulterated, under growing on layer 1
End face DBR is made of the AlGaAs/GaAs material in 36.5 periods, and middle layer 2 is gradation type AlGaAs, and the component of Al is in 0-
Change between 0.875, doped chemical is Zn or C；Layer 3 is the GaAs for mixing Zn or C.
2, lower end surface above is collecting zone (layer 4), by the p-type GaAs and gradation type AlGaAs material structure that mix Zn or C
At；Layer 5, layer 6 and layer 7 together constitute base area, middle layer 5 and layer 7 and are made of the N-type GaAs material for mixing Si, and layer 6 is active area
Layer, is made of undoped eigen I n0.17Ga0.83As/GaAs, and periodicity is 3 to 5；In0.17Ga0.83As is Quantum Well
Layer, GaAs is barrier layer.
3, layer 8 is emitter region, is made of the p-type GaAs and gradation type AlGaAs material for mixing Zn or C, device half at this time
Finished product is as shown in Figure 6 a.
4, after above-mentioned MOCVD or MBE epitaxial layer structure growth is complete, following processing process is taken: logical first
Dry method (ICP or RIE technique) or wet etching are crossed, the layer 8 of part is removed, then as shown in Figure 6 b, is carried out by ALD technique
Al3O3The regrowth of material, to define electrical confined aperture.
5, the secondary recycling finally by MOCVD or MBE is long, completes integrally-built manufacture, as fig. 6 c.
6, base stage sum aggregate electrode step as shown in fig 6d, is defined using dry etch process.
7, the N-type alloy electrode (ingredient Pd/Ge/Ti/Pd/Ti/Au) and p-type of metal evaporation technique production base stage are used
Alloy electrode (alloying component Zn/Pd/Ti/Au) obtains the semi-finished product of state as shown in fig 6e.
8, the surface of other dielectric substance membrane structures in Top-DBR than alumina is carried out using pecvd process
Deposition, as shown in Figure 6 f.
9, Al as shown in figure 6g, is carried out using ALD technique3O3The deposition of film layer.
10, the Al of surface of metal electrode will be covered on using dry etch process (ICP or RIE)3O3Film layer removal, obtains
T-VCSEL of the present invention as shown in figure 6h.
Claims (9)
1. a kind of transistor vertical cavity surface emitting lasers, the substrate successively arranged including the order according to epitaxial growth, lower end
EDS maps formula Bragg mirror, collecting zone, base area, emitter region, upper surface distributed bragg reflector mirror, and respectively with collection
The electrode that electric area, base area, emitter region are connected: collector, base stage, emitter；Quantum well active district is provided in the base area；Its
It is characterized in that, the surface region on base area, emitter region, upper surface distributed bragg reflector mirror except for the electrodes is coated with
Al2O3Protective film, and the upper surface distributed bragg reflector mirror is by Al2O3Membrane structure and at least one other electricity are situated between
Material membrane structure is in the sub-wavelength high contrast grating that periodic arrangement is constituted.
2. transistor vertical cavity surface emitting lasers as described in claim 1, which is characterized in that the emitter region includes one layer of use
Atom layer deposition process be prepared by Al2O3The current-limiting layer constituted, be provided in the middle part of the current-limiting layer for
The current-confining apertures that electric current passes through.
3. transistor vertical cavity surface emitting lasers as claimed in claim 1 or 2, which is characterized in that the Al2O3Protective film and
Al2O3Membrane structure is prepared using atom layer deposition process.
4. transistor vertical cavity surface emitting lasers as described in claim 1, which is characterized in that other dielectric substance films
Structure includes SiO2Membrane structure, Si3N4Membrane structure and amorphous Si membrane structure.
5. transistor vertical cavity surface emitting lasers as described in claim 1, which is characterized in that it is GaAs base or InP-base,
Or GaN base transistor vertical cavity surface emitting lasers.
6. transistor vertical cavity surface emitting lasers as described in claim 1, which is characterized in that the collector is set to substrate
The back side.
7. the preparation method of transistor vertical cavity surface emitting lasers as described in claim 1, which is characterized in that including following step
It is rapid:
Step 1, on substrate successively epitaxial growth with understructure: lower end surface distributed bragg reflector mirror, collecting zone, base
Area, emitter region；
The electrode that step 2, preparation are connected with collecting zone, base area, emitter region respectively: collector, base stage, emitter；
Step 3, other dielectric substance membrane structures that the sub-wavelength high contrast grating is constituted in the preparation of emitter region upper surface；
Step 4 prepares Al on base area, emitter region, upper surface distributed bragg reflector mirror surface2O3Film；
Step 5, the Al that electrode surface will be covered on2O3Film removal.
8. the preparation method of transistor vertical cavity surface emitting lasers as claimed in claim 7, which is characterized in that in epitaxial growth
During emitter region, the first time epitaxial growth of emitter layer structure is carried out first in base layer structure, it then will be peripheral
The surface layer of part emitter layer structure removes, then with atom layer deposition process in the peripheral part emitter layer body structure surface
Carry out Al2O3Regrowth, second of extension for finally carrying out emitter layer structure on the surface of entire emitter layer structure be raw
It is long.
9. the preparation method of transistor vertical cavity surface emitting lasers as described in claim 7 or 8, which is characterized in that in step 2
The electrode is prepared using metal evaporation technique；Institute is constituted using plasma enhanced chemical vapor deposition method preparation in step 3
State other dielectric substance membrane structures of sub-wavelength high contrast grating；It will be covered in step 5 using reactive ion etching process
In the Al of electrode surface2O3Film removal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910437330.XA CN110011181A (en) | 2019-05-24 | 2019-05-24 | Transistor vertical cavity surface emitting lasers and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910437330.XA CN110011181A (en) | 2019-05-24 | 2019-05-24 | Transistor vertical cavity surface emitting lasers and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110011181A true CN110011181A (en) | 2019-07-12 |
Family
ID=67177830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910437330.XA Pending CN110011181A (en) | 2019-05-24 | 2019-05-24 | Transistor vertical cavity surface emitting lasers and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110011181A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110429473A (en) * | 2019-08-06 | 2019-11-08 | 中国科学院半导体研究所 | Vertical cavity surface emitting laser and preparation method thereof |
| CN110676689A (en) * | 2019-10-12 | 2020-01-10 | 长春理工大学 | Vertical cavity surface emitting semiconductor laser and preparation method thereof |
| CN111585164A (en) * | 2020-05-14 | 2020-08-25 | 苏州长瑞光电有限公司 | Rapid aging method and device for vertical cavity surface emitting laser |
| CN111799654A (en) * | 2020-09-09 | 2020-10-20 | 常州纵慧芯光半导体科技有限公司 | Laser device and manufacturing method and application thereof |
| WO2021142962A1 (en) * | 2020-01-16 | 2021-07-22 | 浙江博升光电科技有限公司 | High-contrast grating vertical-cavity surface-emitting laser and manufacturing method therefor |
| US11973315B2 (en) | 2019-02-21 | 2024-04-30 | Apple Inc. | VCSEL with integrated electrodes |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667716A (en) * | 2008-09-03 | 2010-03-10 | 中国科学院半导体研究所 | Double-sided bonding long-wavelength vertical cavity surface emitting laser and manufacturing method thereof |
| CN104078843A (en) * | 2013-03-29 | 2014-10-01 | 新科实业有限公司 | Multimode vertical-cavity surface emitting laser with narrow laser emission angle |
| CN104319626A (en) * | 2014-10-11 | 2015-01-28 | 北京工业大学 | Microwave carrier directly modulated vertical-cavity surface-emitting laser |
| CN104488148A (en) * | 2012-07-11 | 2015-04-01 | 皇家飞利浦有限公司 | Vcsel with intracavity contacts |
| CN105932542A (en) * | 2016-07-13 | 2016-09-07 | 南京航空航天大学 | Transistor vertical-cavity surface-emitting laser |
| US20170302059A1 (en) * | 2014-09-25 | 2017-10-19 | Koninklijke Philips N.V. | Vertical cavity surface emitting laser |
| CN209608089U (en) * | 2019-05-24 | 2019-11-08 | 苏州长瑞光电有限公司 | Transistor vertical cavity surface emitting lasers |
-
2019
- 2019-05-24 CN CN201910437330.XA patent/CN110011181A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101667716A (en) * | 2008-09-03 | 2010-03-10 | 中国科学院半导体研究所 | Double-sided bonding long-wavelength vertical cavity surface emitting laser and manufacturing method thereof |
| CN104488148A (en) * | 2012-07-11 | 2015-04-01 | 皇家飞利浦有限公司 | Vcsel with intracavity contacts |
| CN104078843A (en) * | 2013-03-29 | 2014-10-01 | 新科实业有限公司 | Multimode vertical-cavity surface emitting laser with narrow laser emission angle |
| US20170302059A1 (en) * | 2014-09-25 | 2017-10-19 | Koninklijke Philips N.V. | Vertical cavity surface emitting laser |
| CN104319626A (en) * | 2014-10-11 | 2015-01-28 | 北京工业大学 | Microwave carrier directly modulated vertical-cavity surface-emitting laser |
| CN105932542A (en) * | 2016-07-13 | 2016-09-07 | 南京航空航天大学 | Transistor vertical-cavity surface-emitting laser |
| CN209608089U (en) * | 2019-05-24 | 2019-11-08 | 苏州长瑞光电有限公司 | Transistor vertical cavity surface emitting lasers |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11973315B2 (en) | 2019-02-21 | 2024-04-30 | Apple Inc. | VCSEL with integrated electrodes |
| CN110429473A (en) * | 2019-08-06 | 2019-11-08 | 中国科学院半导体研究所 | Vertical cavity surface emitting laser and preparation method thereof |
| CN110676689A (en) * | 2019-10-12 | 2020-01-10 | 长春理工大学 | Vertical cavity surface emitting semiconductor laser and preparation method thereof |
| WO2021142962A1 (en) * | 2020-01-16 | 2021-07-22 | 浙江博升光电科技有限公司 | High-contrast grating vertical-cavity surface-emitting laser and manufacturing method therefor |
| CN111585164A (en) * | 2020-05-14 | 2020-08-25 | 苏州长瑞光电有限公司 | Rapid aging method and device for vertical cavity surface emitting laser |
| CN111799654A (en) * | 2020-09-09 | 2020-10-20 | 常州纵慧芯光半导体科技有限公司 | Laser device and manufacturing method and application thereof |
| CN111799654B (en) * | 2020-09-09 | 2021-01-22 | 常州纵慧芯光半导体科技有限公司 | Laser device and manufacturing method and application thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110011181A (en) | Transistor vertical cavity surface emitting lasers and preparation method thereof | |
| US5363397A (en) | Integrated short cavity laser with bragg mirrors | |
| US7680162B2 (en) | Long wavelength vertical cavity surface emitting laser device and method of fabricating the same | |
| JPH0974219A (en) | Surface light-emission type diode and its manufacture | |
| CN103872580B (en) | Dielectric film current-limiting type vertical cavity surface emitting laser and preparation method thereof | |
| CN105932542B (en) | A kind of transistor vertical cavity surface emitting lasers | |
| JPH04225588A (en) | Semiconductor laser structure | |
| CN115461944A (en) | Integrated vertical emitter structure with controlled wavelength | |
| CN110112653B (en) | Vertical external cavity surface emitting semiconductor laser | |
| KR20030038072A (en) | Long wavelength vertical-cavity surface emitting laser having oxide-aperture and method for fabricating the same | |
| CN114649742A (en) | Novel efficient vertical cavity surface EML chip and preparation method thereof | |
| JPH0555713A (en) | Light emitting semiconductor element | |
| CN209608089U (en) | Transistor vertical cavity surface emitting lasers | |
| KR20090077167A (en) | Micro-lens integrated single-mode vertical cavity surface emitting laser and method for manufacturing thereof | |
| CN110197993A (en) | The VCSEL chip and its manufacturing method of high combined efficiency | |
| WO2024067760A1 (en) | Integrated laser and preparation method therefor | |
| CN113422295A (en) | Multi-junction distributed feedback semiconductor laser and preparation method thereof | |
| TWI251270B (en) | Carbon doped GaAsSb suitable for use in tunnel junctions of long-wavelength VCSELs | |
| CN116683288A (en) | Fundamental mode low divergence angle vertical cavity surface emitting laser and preparation method thereof | |
| JPH08340132A (en) | Surface light emitting diode | |
| CN109494285A (en) | Tunable optical transmitter part and preparation method thereof | |
| CN211456209U (en) | Vertical cavity surface emitting laser | |
| US20070127533A1 (en) | Long-wavelength vertical cavity surface emitting lasers having oxide aperture and method for manufacturing the same | |
| CN210040877U (en) | Vertical cavity surface emitting laser with horizontal air column current injection aperture structure | |
| KR20080098574A (en) | Long wavelength vertical cavity surface emitting laser device and method for fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |