CN110197993B - VCSEL chip with high recombination efficiency and manufacturing method thereof - Google Patents
VCSEL chip with high recombination efficiency and manufacturing method thereof Download PDFInfo
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- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 13
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
- H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/30—Structure or shape of the active region; Materials used for the active region
- H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
- H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
- H01S5/34313—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs
- H01S5/3432—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer having only As as V-compound, e.g. AlGaAs, InGaAs the whole junction comprising only (AI)GaAs
Abstract
The invention relates to the technical field of laser chips, in particular to a VCSEL chip with high composite efficiency and a manufacturing method thereof, wherein the VCSEL chip comprises a substrate, an epitaxial layer and an N-contact, the epitaxial layer comprises an N-DBR, a quantum well, an oxide layer and a P-DBR, the oxide layer and the quantum well are etched to the surface of the N-DBR to form a mesa, the quantum well comprises a plurality of pairs of quantum well composite layers, and the quantum well composite layers comprise Al which grows in an overlapping way x GaAs potential barrier, inGaAs potential well and Al x The GaAs barrier is divided into a central region, a middle region and an edge region on the P-DBR, the central region is a light outlet hole, a first SiNx layer grows on the P-DBR at a position corresponding to the central region, a P-contact is evaporated on the P-DBR at a position corresponding to the middle region, and a second SiNx layer grows on the P-DBR at a position corresponding to the edge region. The potential barrier in the quantum well in the VCSEL chip has higher forbidden bandwidth, lattice matching is easy to achieve, more electrons are intensively bound in the quantum well, the excitation probability is increased, the recombination efficiency is improved, and therefore stimulated radiation with higher efficiency is achieved.
Description
Technical Field
The invention relates to the technical field of laser chips, in particular to a VCSEL chip with high composite efficiency and a manufacturing method thereof.
Background
A vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser) chip, also known as a VCSEL chip or a vertical resonant cavity surface emitting laser chip, is a gallium arsenide semiconductor material-based laser emitting chip with laser light emitted perpendicular to the top surface, unlike edge-emitting lasers which are typically manufactured by a separate chip process with dicing. The VCSEL chip has the advantages of small volume, round output light spots, single longitudinal mode output, small threshold current, low price, easy integration into a large-area array and the like, and is widely applied to the fields of optical communication, optical interconnection, optical storage and the like.
A laser resonator is formed by a two-sided Distributed Bragg Reflector (DBR) parallel to the surface of an active reaction region of a chip, the reaction region being formed by one to several quantum wells (MQWs) in which laser light bands are present. A planar DBR is made up of several layers of lenses of different high and low refractive indices. Each layer of lenses is one quarter of the laser wavelength thick and gives a reflection intensity of more than 99%. In order to balance the short axis length of the gain region in a VCSEL, a high reflectivity lens is necessary. In a typical VCSEL, the upper and lower lenses are plated with p-type material and n-type material, respectively, to form a junction diode. In more complex structures, the p-type and n-type regions may be buried in the lens, allowing more complex semiconductors to be fabricated as circuit connections over the reaction region and removing the loss of electron energy in the DBR structure.
As shown in fig. 1, a cross-sectional structure of a VCSEL chip in the prior art mainly includes a gaas substrate 10 and an N-type DBR 20 (Distributed Bragg Reflection, distributed bragg reflector) disposed on the gaas substrate 10, a quantum well layer 30, a confinement layer 40, a P-type DBR 50, a gaas contact layer 60, and an electrode structure 70, wherein the confinement layer 40 includes a conductive structure 41 and oxide structures 42 disposed on both sides of the conductive structure 41, so as to collect current, thereby forming a purpose of exciting laser light in the high-current injection quantum well layer 30; the electrode structure 70 includes a first electrode 71 and a second electrode 72, the first electrode 71 and the second electrode 72 are respectively located at two ends of the gallium arsenide contact layer 60, and a region between the first electrode 71 and the second electrode 72 is a light emitting region of the VCSEL chip.
A VCSEL is a semiconductor laser in which electrons exciting the semiconductor jump from the valence band to the conduction band, and when the electrons jump from the conduction band back to the valence band, energy is released in the form of optical energy. The quantum wells in the VCSEL chip in the prior art are mostly collocated with InGaAs/GaAs as potential wells and potential barriers respectively, and the allocation of the MQW composite efficiency determining the same level number is basically only influenced by the GaAs potential barriers, so that the quantum well design composite efficiency in the prior art is lower, and the stimulated emissivity is always not high.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a VCSEL chip with high recombination efficiency and a method for manufacturing the same, in which a potential barrier in a quantum well in the manufactured VCSEL chip has a high forbidden bandwidth, so that lattice matching is easy to achieve, more electrons are intensively bound in the quantum well, the excitation probability is increased, the recombination efficiency is improved, and thus, stimulated radiation with higher efficiency is achieved.
The invention solves the technical problems by the following technical means:
an aspect of the present invention provides a high recombination efficiency VCSEL chip comprising a substrate, and an epitaxial layer and an N-contact grown on opposite sides of the substrate, respectively, the epitaxial layer comprising an N-DBR, a quantum well, an oxide layer and a P-DBR grown in this order from bottom to top on the substrate surface, the P-DBR, the oxide layer, the quantum well being etched to the N-DBR surface to form a mesa, the quantum well comprising a plurality of pairs of quantum well composite layers grown in overlapping fashion, the quantum well composite layers comprising Al grown in overlapping fashion x GaAs potential barrier, inGaAs potential well and Al x GaAs potential barrier, the P-DBR is divided into a central area, a middle area and an edge area from the center to the outer side in sequence, the central area is a light outlet hole, and a first SiN grows on the P-DBR at the corresponding position of the central area x A layer, wherein a P-contact is evaporated on the P-DBR at the corresponding position of the middle region, and a second SiN is grown on the P-DBR at the corresponding position of the edge region x A layer.
Al as described above x The Al component of the GaAs barrier is adjusted according to the magnitude of the VCSEL working current: when the current is 5mA, the Al component is 0.1, when the current is 10mA, the Al component is 0.2, the current is proportional to the Al component, and when the current is doubled, the Al component is doubled.
Optionally, the quantum well comprises 2-5 pairs of quantum well composite layers which are grown in an overlapping mode.
Optionally, al of each pair of the quantum well composite layers x The GaAs barrier is 10 angstroms thick and the InGaAs well is 10 angstroms thick.
Optionally, the surface from the table top to the P-contact is covered with a protective layer, and the section of the protective layer is zigzag and completely covers the table top and partially covers the P-contact surface.
Alternatively, the N-DBR includes 40 pairs of reflective elements grown in layers, and the P-DBR includes 30 pairs of reflective elements grown in layers, the reflective elements being AlGaAs layers.
Optionally, the oxide layer comprises an unoxidized segment and an oxidized segment surrounding the unoxidized segment, the unoxidized segment is composed of Al 0.98 The GaAs material is grown.
Another aspect of the present invention provides a method for manufacturing the VCSEL chip, including the steps of:
the epitaxial layer is grown, firstly, an N-DBR using AlGaAs as a material is grown on the surface of a substrate, then a quantum well is grown on the surface of the N-DBR, and Al is grown on the quantum well 0.98 GaAs layer, finally at Al 0.98 Growing a P-DBR (distributed Bragg reflector) taking AlGaAs as a material on the GaAs layer, namely obtaining an epitaxial layer on the substrate;
the VCSEL chip is formed, the surface of the P-DBR is divided into a central area, a middle area, an edge area and an outer edge area from the center to the outside in sequence, and a layer of SiN is grown on the P-DBR x Etching SiN corresponding to the positions of the middle region and the outer edge region x A layer to the P-DBR surface to form a first SiN corresponding to the central region x Layer and edge region location corresponding second SiN x A layer, a metal is then deposited as P-contact on the P-DBR surface at a position corresponding to the middle region, along the second SiN x Etching the P-DBR, oxide layer and quantum well at the edge of the layer to form mesa, and then forming a mesa on the surface of the N-DBR 0.98 Partially oxidizing the GaAs layer to obtain Al 0.98 The GaAs layer is divided into an unoxidized section and an oxidized section, a growth protection layer is deposited on the table top until the surface of the P-contact is partially covered, and finally the substrate is thinned and plated with metal to serve as the N-contact.
Optionally, the growth of the quantum well is made as follows: first, a layer of Al with the thickness of 10 angstroms is grown on an N-DBR x GaAs barrier, then at Al x Growing an InGaAs potential well with the thickness of 10 angstroms on the GaAs potential barrier, and finally growing an Al layer on the InGaAs potential well x GaAs barrier.
Alternatively, 40 pairs of N-DBRs made of AlGaAs are grown on the surface of the substrate, and 30 pairs of P-DBRs made of AlGaAs are grown on the quantum well.
Optionally, the protective layer adopts SiN x And (5) vapor deposition.
The VCSEL chip of the invention uses N-DBR and P-DBR as laser cavity mirrors, and quantum wells as active areas, and changes the traditional GaAs material into Al x GaAs, when the potential barrier is Al x GaAs will be more lattice matched than other semiconductor materials and Al 0.1 The GaAs forbidden band width is 1.55, which is higher than GaAs forbidden band width, as shown in fig. 2, and is higher as the Al composition increases. When electrons are excited, the relatively higher forbidden bandwidth enables more electrons to be bound in the quantum well, so that the recombination efficiency is improved, and the stimulated radiation with higher efficiency is achieved. The potential barrier in the VCSEL chip of the invention adopts Al x GaAs, relative to GaAs, al x The GaAs forbidden band width is higher and lattice matching is easily achieved. The relatively higher forbidden bandwidth enables more electrons to be intensively bound in the quantum well, and a large number of electrons increase the excitation probability and the recombination efficiency, so that the stimulated radiation with higher efficiency is achieved.
Drawings
Fig. 1 is a schematic diagram of a prior art VCSEL chip structure;
FIG. 2 is a band gap diagram of barriers of different materials;
FIG. 3 is a schematic diagram of the epitaxial layer structure in a high recombination efficiency VCSEL chip of the present invention;
fig. 4 to 7 are schematic structural views corresponding to steps in the method for manufacturing a VCSEL chip with high recombination efficiency according to the present invention;
wherein the substrate 100, N-contact 210, P-contact 220, N-DBR 310, quantum well 320, al x GaAs potential barrier 321, inGaAs potential well 322, al x GaAs barrier 323, oxide layer 330, unoxidized section 331, oxide section 332, P-DBR340, mesa 4, light exit hole 5, siN x Layer 600, first SiN x Layer 610, second SiN x Layer 620, protective layer 700, central region 81, intermediate region 82, edge region 83, outer edge region 84, al 0.98 GaAs layer 9.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It should be noted that in the drawings or description, similar or identical parts are provided with the same reference numerals, and that implementations not shown or described in the drawings are in forms known to those of ordinary skill in the art. Additionally, although examples of parameters including particular values may be provided herein, it should be appreciated that the parameters need not be exactly equal to the corresponding values, but may be approximated to the corresponding values within acceptable error margins or design constraints. The directional terms mentioned in the embodiments, such as "upper", "lower", "top", "bottom", "left", "right", etc., are only with reference to the directions of the drawings, and are not intended to limit the scope of the present invention. Relational terms such as first and second, and the like may be used solely to distinguish one entity from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
As shown in fig. 7, the VCSEL chip with high recombination efficiency of the present embodiment includes a substrate 100, and an epitaxial layer and an N-contact 210 grown on opposite sides of the substrate 100, wherein the substrate 100 is manufactured from a material including, but not limited to, gaAs, and the epitaxial layer includes an N-DBR 310, a quantum well 320, an oxide layer 330, and a P-DBR340 grown on a surface of the substrate in this order from bottom to top, and the P-DBR340, the oxide layer 330, and the quantum well 320 are etched to the surface of the N-DBR 310 to form a mesa 4. Quantum well 320 comprises multiple pairs of quantum well composite layers grown in an overlapping manner, preferably the quantum well comprises 2-5 pairs of quantum well composite layers grown in an overlapping manner, and more preferably the quantum well comprises 3 pairs of quantum well composite layers grown in an overlapping manner, which is beneficial to enabling more electrons to be bound in the quantum well and improving the recombination efficiency. Specifically, the quantum well composite layer comprises Al grown in an overlapping manner x GaAs potential barrier 321, inGaAs potential well 322, and Al x GaAs barrier 323, al in each pair of quantum well composite layers x GaAs barrier 321 and Al x The GaAs barrier 323 is 10 angstroms thick and the InGaAs potential well 322 is 10 angstroms thick.
When the potential barrier isBy Al x GaAs materials will be more lattice matched than other semiconductor materials, and Al 0.1 The GaAs forbidden band width is 1.55, which is higher than GaAs forbidden band width, as shown in fig. 2, and is higher as the Al composition increases. When electrons are excited, the relatively higher forbidden bandwidth enables more electrons to be bound in the quantum well, so that the recombination efficiency is improved, and the stimulated radiation with higher efficiency is achieved. Wherein the potential barrier Al x The Al component of GaAs is adjusted according to the working current of the VCSEL: that is, when the current is 5mA, x is 0.1, when the current is 10mA, x is 0.2, the current is proportional to the Al component, and when the current is doubled, the Al component is doubled.
Specifically, the N-DBR 310 includes 40 pairs of stacked grown reflective elements, and the P-DBR340 includes 30 pairs of stacked grown reflective elements, which are AlGaAs layers. The oxide layer 330 includes an unoxidized segment 331 and an oxidized segment 332 surrounding the unoxidized segment 331, the unoxidized segment 331 being composed of Al 0.98 GaAs material is grown and formed, and oxidation section 332 is formed by oxidation of Al 0.98 GaAs formation.
The P-DBR340 is divided into a central region, a middle region and an edge region from the center to the outside, the central region is a light outlet 5, and a first SiN grows on the P-DBR340 at the corresponding position of the central region x The layer 610, the P-contact 220 is formed by evaporating a metal material on the P-DBR340 at a position corresponding to the middle region, the P-contact 220 is formed by using materials including but not limited to Ti, pt, au, and the P-DBR340 is grown with a second SiN on the edge region at a position corresponding to the edge region x A layer 620 having a surface of the mesa 4 to the P-contact 220 covered with a protection layer 700, the protection layer 700 having a zigzag cross section and completely covering the mesa 4, the quantum well 320, the oxide layer 330, the sides of the P-DBR340, and the first SiN x The protective layer 700 also partially covers the surface of the P-contact 220 to partially expose the surface of the P-contact 220 for subsequent bonding wires to conduct current, and the protective layer 700 is made of materials including, but not limited to SiN x 、SiO 2 。
The manufacturing method of the VCSEL chip comprises the following steps:
as shown in fig. 3:
s1, growing 40 pairs of N-DBRs 210 made of AlGaAs on the surface of a substrate 100 made of GaAs according to a conventional method.
S2, growing a quantum well 320 on the surface of the N-DBR, wherein the method specifically comprises the steps of firstly growing a layer of Al with the thickness of 10 angstroms on the N-DBR x GaAs barrier 321, then at Al x A 10 angstrom thick InGaAs potential well 322 is grown on the GaAs barrier, and finally an Al layer is grown on the InGaAs potential well x GaAs barrier 323. Potential barrier Al x The Al component of GaAs is adjusted according to the working current of the VCSEL: when the current is 5mA, the Al component is 0.1, when the current is 10mA, the Al component is 0.2, the current is proportional to the Al component, and when the current is doubled, the Al component is doubled.
S3, growing Al on the quantum well 320 0.98 GaAs layer 9 is used to form oxide layer 330 later, and then Al 0.98 A 30 pair AlGaAs P-DBR340 is grown on the GaAs layer, i.e., an epitaxial layer is obtained on the substrate 100.
S4, forming a VCSEL chip, and dividing the surface of the P-DBR340 into a central region 81, a middle region 82, an edge region 83 and an outer edge region 84 from the center to the outer side. As shown in FIG. 4, a layer of SiN is grown on the P-DBR340 according to conventional methods x Layer 600; as shown in fig. 5, siN is etched in the middle region 82 and the outer edge region 84 at corresponding positions x A layer formed on the surface of the P-DBR340 to form a first SiN corresponding to the position of the central region 81 x Second SiN corresponding to the positions of layer 610 and edge region 83 x A layer 620, where a metal including but not limited to Ti, pt, au is then deposited as P-contact 220 on the P-DBR surface at a location corresponding to the middle region; as shown in fig. 6, along the second SiN x The outer edge of layer 620 ICP etches the P-DBR, oxide layer and quantum well to the N-DBR surface to form mesa 4, ensuring current concentration injection, and oxidizing Al according to conventional wet method 0.98 Partially oxidizing the GaAs layer to obtain Al 0.98 The GaAs layer is divided into an unoxidized section 331 and an oxidized section 332 to form an oxidized layer 330; as shown in fig. 7, a growth protection layer 700 is then deposited on the mesa 4 to partially cover the P-contact 220 surface, the protection layer 700 having a zigzag cross section and completely covering the mesa 4, the quantum well 320, the oxide layer 330, the sides of the P-DBR340 and the first SiN x The protective layer 700 also partially covers the P-contact surface to partially expose the P-contact surface for subsequent bonding wires to conduct current, the protective layer being made of materials including but not limited to SiN x 、SiO 2 Finally, the substrate is thinned to 110um and plated with metal as N-contact 210, which is a metallic material including, but not limited to AuGe, au.
When the VCSEL chip manufactured by the above-described manufacturing method is used with P-contact and N-contact on currents, the quantum well serves as an active region, and the composite light emission is started and the laser light is emitted from the light emitting hole.
Electrons exciting a semiconductor jump from the valence band to the conduction band when the electrons are excited, and when the electrons jump from the conduction band back to the valence band, energy is released in the form of optical energy. The VCSEL chip of the embodiment changes the traditional GaAs material into Al x GaAs, relative to GaAs, al x The GaAs forbidden band width is higher and lattice matching is easily achieved. The relatively higher forbidden bandwidth enables more electrons to be intensively bound in the quantum well, and a large number of electrons increase the excitation probability and the recombination efficiency, so that the stimulated radiation with higher efficiency is achieved.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention. The technology, shape, and construction parts of the present invention, which are not described in detail, are known in the art.
Claims (9)
1. A VCSEL chip with high recombination efficiency is characterized in that the VCSEL chip comprises a substrate, and an epitaxial layer and an N-contact which are respectively grown on two opposite sides of the substrate, wherein the epitaxial layer comprises an N-DBR, a quantum well, an oxide layer and a P-DBR which are sequentially grown on the surface of the substrate from bottom to top, the P-DBR, the oxide layer and the quantum well are etched to the surface of the N-DBR to form a table surface, and the quantum well comprises a plurality of pairs of quantum well composites which are grown in an overlapping mannerA quantum well composite layer comprising an overlapped grown Al x GaAs potential barrier, inGaAs potential well and Al x The GaAs barrier is characterized in that the P-DBR is sequentially divided into a central region, a middle region and an edge region from the center to the outer side, the central region is a light outlet hole, a first SiNx layer grows on the P-DBR at a position corresponding to the central region, a P-contact is evaporated on the P-DBR at a position corresponding to the middle region, and a second SiNx layer grows on the P-DBR at a position corresponding to the edge region;
the Al is x The Al component of the GaAs barrier is adjusted according to the magnitude of the VCSEL working current, the VCSEL working current is in direct proportion to the Al component, and the Al component is doubled when the current is doubled.
2. A high recombination efficiency VCSEL chip as claimed in claim 1, wherein the quantum wells comprise 2-5 pairs of quantum well recombination layers grown one above the other.
3. A high recombination efficiency VCSEL chip as claimed in claim 2, wherein each pair of said quantum well composite layers of Al x The GaAs barrier is 10 angstroms thick and the InGaAs well is 10 angstroms thick.
4. The high recombination efficiency VCSEL chip of claim 1, wherein the mesa-to-P-contact surface is covered with a protective layer having a cross section that completely covers the mesa and partially covers the P-contact surface in a zig-zag shape.
5. The high recombination efficiency VCSEL chip of claim 1, wherein the N-DBR comprises 40 pairs of stacked grown reflective elements and the P-DBR comprises 30 pairs of stacked grown reflective elements, the reflective elements being AlGaAs layers.
6. A high recombination efficiency VCSEL chip as claimed in any of claims 1 to 5, characterized in that the oxide layer comprises unoxidized segments and oxidized segments surrounding the unoxidized segments, the unoxidized segments being grown from al0.98gaas material.
7. A method of fabricating a VCSEL chip with high recombination efficiency, comprising the steps of:
the epitaxial layer is grown, firstly, an N-DBR using AlGaAs as a material is grown on the surface of a substrate, then a quantum well is grown on the surface of the N-DBR, and Al is grown on the quantum well 0.98 GaAs layer, finally at Al 0.98 Growing a P-DBR (distributed Bragg reflector) taking AlGaAs as a material on the GaAs layer, namely obtaining an epitaxial layer on the substrate;
forming a VCSEL chip, dividing the surface of the P-DBR into a central region, a middle region, an edge region and an outer edge region from the center to the outside in sequence, growing a SiNx layer on the P-DBR, etching the SiNx layer corresponding to the positions of the middle region and the outer edge region to the surface of the P-DBR, forming a first SiNx layer corresponding to the position of the central region and a second SiNx layer corresponding to the position of the edge region, evaporating metal at the position corresponding to the middle region on the surface of the P-DBR as P-contact, etching the P-DBR, the oxide layer and the quantum well along the edge of the second SiNx layer to the surface of the N-DBR to form a table top, and then performing Al 0.98 Partially oxidizing the GaAs layer to obtain Al 0.98 The GaAs layer is divided into an unoxidized section and an oxidized section, a growth protection layer is deposited on the table top until the surface of the P-contact is partially covered, and finally the substrate is thinned and plated with metal to serve as the N-contact.
8. The method of fabricating a high recombination efficiency VCSEL chip as claimed in claim 7, wherein 40 pairs of AlGaAs-based N-DBRs are grown on the substrate surface, and 30 pairs of AlGaAs-based P-DBRs are grown on the quantum well.
9. The method of fabricating a high recombination efficiency VCSEL chip as claimed in claim 7, wherein the protective layer is formed using SiNx deposition.
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