CN208538898U - A kind of reversed polarity LED chip with mask layer - Google Patents
A kind of reversed polarity LED chip with mask layer Download PDFInfo
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Abstract
The utility model relates to a kind of reversed polarity LED chip with mask layer, including substrate layer, bonded layer, bonding protective layer, composite construction layer, epitaxial layer, mask layer, N electrode and passivation layer；The upper surface of substrate layer is from bottom to up successively bonded layer, bonds protective layer, composite construction layer；For epitaxial layer in the upper surface of composite construction layer, epitaxial layer is successively p-type layer, luminescent layer, n-layer, roughened layer, ohmic contact layer from bottom to up；Mask layer, N electrode and passivation layer are equipped on epitaxial layer, mask layer is and corresponding with N electrode figure on ohmic contact layer, is looped around around N electrode.The utility model can solve in roughening process, and N electrode caused by ohmic contact layer wet etching course sidetracking falls off problem, and effectively improve LED chip prepares yield.
Description
Technical field
The utility model relates to light emitting semiconductor devices, more particularly, to a kind of reversed polarity LED chip with mask layer.
Background technique
Light emitting diode (LED) is developed so far, and is used widely in various lighting areas.With gallium arsenide substrate lattice
Matched AlGaInP material can cover the visible wavelength of the range from 560nm to 650nm, be prepare it is dark red, red, orange, yellow
The excellent material of green LED.AlGaInP light emitting diode is in the fields such as solid-state lighting, display, city lighting, plant growth
There is important application, it is raw to be widely used in full color screen display, automobile signal light, traffic lights, stage light projecting lamp, plant
In the products such as long headlamp and high color rendering index (CRI) white-light illuminating lamps and lanterns.
In recent years, people have made great progress on AlGaInP LED epitaxial material growing technology, interior amount
Sub- efficiency can reach 90% or more.But AlGaInP LED epitaxial material is grown directly in gallium arsenide substrate, then directly
It connects and is absorbed there are substrate and complete in the back side of gallium arsenide substrate preparation N electrode, in the LED chip of upper surface preparation P electrode preparation
Reflection loss, it is very low so as to cause chip electro-optical efficiency, generally less than 10%.
It absorbed to reduce substrate, inhibit transfer efficiency of the total reflection to improve electric light, a kind of very effective method is system
Standby reversed polarity LED chip.This method is that AlGaInP LED epitaxial material is first grown in gallium arsenide substrate, then will
Epitaxial film is transferred on the substrates such as silicon, germanium, sapphire, then epitaxial growth substrate is removed, and then makes N electrode, goes forward side by side
Row roughing in surface reduces the loss at total reflection of light gasing surface, and this reversed polarity AlGaInP LED chip can be by the electric light of LED
Transfer efficiency promotes 3~6 times, reaches 30~60%.In the face the N technical process of reversed polarity LED chip after the transfer, N electrode system
Standby is the key that realize electric current injection, and n-layer roughing in surface is the key that then to improve chip light extraction efficiency.N electrode preparation
Process is related to the removal of sacrificial layer, and the coarsening process of n-layer is related to the removal of sacrificial layer and ohmic contact layer.In general, adopting
Realize that material removes with the mode of wet etching.The wet etching course of sacrificial layer and ohmic contact layer in corrosive liquid be it is each to
The same sex.It is to need to do graphical for sacrificial layer and ohmic contact layer, and selectively removes, rather than entire removal.
It needs to use photoetching process by designed graph copying to sacrificial layer and Ohmic contact layer surface.For currently existing technology,
It is realized in sacrificial layer and ohmic contact layer patterning process using photoetching process, due to viscous between photoresist and the material that is corroded
Attached property is insufficient, and the material that is corroded in wet etching course has sidetracking.To affect technological effect, it is good to reduce manufacture
Rate.In order to solve this problem, the utility model proposes a kind of reversed polarity LED chip with mask layer.
Utility model content
To overcome defect in the prior art, the utility model provides a kind of reversed polarity LED chip with mask layer,
The chip includes substrate layer, bonded layer, bonding protective layer, composite construction layer, epitaxial layer, mask layer, N electrode and passivation layer；
The substrate layer sequentially consists of contact layer, reverse side protective layer, supporting substrate, front protecting layer；
The upper surface of described substrate layer is from bottom to up successively bonded layer, bonds protective layer, composite construction layer；
For the epitaxial layer in the upper surface of composite construction layer, the epitaxial layer is successively p-type layer, luminescent layer, N-shaped from bottom to up
Layer, roughened layer, ohmic contact layer；
On said epitaxial layer there face be equipped with mask layer, N electrode and passivation layer, the mask layer on ohmic contact layer,
And it is corresponding with N electrode figure, it is looped around around N electrode.
Wherein, the mask layer thickness is 0.1um~5um；
The bonded layer with a thickness of 1um~10um；
It is described bonding protective layer with a thickness of 0.1um~10um；
The composite construction layer with a thickness of 0.05um~2um；
The substrate front side protective layer with a thickness of 0.5um~10um；
The substrate back side protective layer with a thickness of 0.5um~10um；
The supporting substrate with a thickness of 60um~600um；
The contact layer with a thickness of 0.1um~10um.
Wherein, the material of the mask layer is silica, in silicon nitride, nitrogen-oxygen-silicon, Kapton dielectric material
It is a kind of.
It wherein, further include sacrificial layer on the ohmic contact layer.
Wherein, the composite construction layer includes complementary structure layer, metal contact layer and reflecting layer.
In conclusion the utility model grows mask layer structure by the material surface that is corroded, realized using mask layer wet
Method corrosion process is corroded material not by sidetracking, improves selectivity when being corroded material wet etching, increases chip preparation
The graphical precision of process realizes increase process window, improves the purpose of chip manufacturing yield, also can solve roughening process
In, N electrode caused by ohmic contact layer wet etching course sidetracking falls off problem, and it is good to effectively raise preparing for LED chip
Rate.
Detailed description of the invention
Fig. 1 is the diagrammatic cross-section of the utility model epitaxial layer and growth substrates structure；
Fig. 2 is the diagrammatic cross-section prepared after composite construction layer and bonding protective layer on the utility model epitaxial layer；
Fig. 3 is to prepare the diagrammatic cross-section after adhesive layer on the utility model supporting substrate；
Fig. 4 is the diagrammatic cross-section after the utility model epitaxial layer and substrate layer bonding；
Fig. 5 is to remove the diagrammatic cross-section after growth substrates and buffer layer in Fig. 4；
Fig. 6 is that the diagrammatic cross-section after mask layer is grown on Fig. 5 sacrificial layer；
Diagrammatic cross-section on the basis of Fig. 7 is Fig. 6 after N electrode preparation；
Fig. 8 is by the diagrammatic cross-section after the coarsening surface of epitaxial layer of Fig. 7；
Fig. 9 is N electrode partial enlarged view in Fig. 8
Figure 10 is reversed polarity LED chip trimming in the embodiments of the present invention 1 and the diagrammatic cross-section after passivation；
Figure 11 is diagrammatic cross-section after reversed polarity LED chip trimming in the embodiments of the present invention 2 and passivation；
Figure 12 is to remove the diagrammatic cross-section after growth substrates, buffer layer and sacrificial layer in Fig. 4；
Figure 13 is that Figure 12 grows the diagrammatic cross-section after mask layer on ohmic contact layer；
Diagrammatic cross-section on the basis of Figure 14 is Figure 13 after N electrode preparation；
Figure 15 is by the diagrammatic cross-section after the coarsening surface of epitaxial layer of Figure 14；
Figure 16 is reversed polarity LED chip trimming in the embodiments of the present invention 3 and the diagrammatic cross-section after passivation；
Figure 17 is a kind of preparation flow figure of reversed polarity LED chip with mask layer of the utility model.
It illustrates:
In embodiment 1,101: growth substrates；102: buffer layer；103: sacrificial layer；104: ohmic contact layer；105:n type
Layer；106: luminescent layer；107:p type layer；201: supporting substrate；202: substrate front side protective layer；203: adhesive layer；204: substrate is anti-
Face protective layer；205: contact layer；301: composite construction layer；302: bonding protective layer；401: bonded layer；501: mask layer；601:N
Electrode；701: roughened layer；801: passivation layer.
In embodiment 2,802: passivation layer；(other are same as Example 1).
In embodiment 3,901: mask layer；111:N electrode；121: roughened layer；(other are same as Example 1).
Specific embodiment
It is practical new below in conjunction with this to keep the objectives, technical solutions, and advantages of the embodiments of the present invention clearer
Attached drawing in type embodiment, the technical scheme in the utility model embodiment is clearly and completely described, it is clear that is retouched
The embodiment stated is a part of the embodiment of the utility model, instead of all the embodiments.Based on the reality in the utility model
Apply example, those of ordinary skill in the art's every other embodiment obtained without making creative work, all
Belong to the range of the utility model protection.It should be noted that the attached drawing of the utility model is all made of the non-accurate ratio simplified very much
Example, only to convenient, apparent aid illustration the utility model.
The utility model is described in detail with reference to the accompanying drawings and examples.
Embodiment 1
Fig. 1 is the epitaxial layer of the utility model and the diagrammatic cross-section of growth substrates structure.As shown in Figure 1, growth substrates
101, growth substrates 101 can be gallium arsenide substrate, gallium phosphide substrate, silicon substrate, Sapphire Substrate and existing AlGaInP
Any one of film growth substrates in base LED technology field.The growth substrates 101 of the present embodiment are gallium arsenide substrate.
AlGaInP base epitaxial layer is obtained using the method for Metallo-Organic Chemical Vapor deposition, since growth substrates 101, outside
Prolonging layer successively includes: buffer layer 102, sacrificial layer 103, ohmic contact layer 104, n-layer 105, luminescent layer 106, p-type layer 107.?
In one embodiment of the utility model, sacrificial layer 103 is removed in chip fabrication process, therefore buffer layer 102 and ohm
There is no sacrificial layer 103 between contact layer 104.
Fig. 2 show the epi-layer surface in the utility model and prepares composite construction layer 301, then deposition bonding protective layer
Diagrammatic cross-section after 302.
Composite construction layer 301 includes complementary structure layer, metal contact layer and reflecting layer.Complementary structure layer preparation method be
The insulating dielectric materials such as growing silicon oxide or silicon nitride；Or, using plasma etches, the surface of epitaxial film materials is destroyed, p is made
Ohmic contact resistance between 107 surface of type layer and metal contact layer becomes larger；Or epitaxial film materials are etched away using etching technics
P-type layer 107, keep the current expansion of epitaxial layer less able.Metal contact layer is that lower Europe can be formed layer by layer with extension
The metal single layer or lamination of nurse contact resistance, the material of metal contact layer is Au, Ag, NiAg, NiAu, AuBe, Ag/Ni/Ag,
One of Ni/Al, Ni/Ag/Ni/Ag.Reflecting layer be monolayer material or sandwich with high reflectance, instead
The material for penetrating layer is one of Au, Ag, NiAg, NiAu, AuBe, Ag/Ni/Ag, Ni/Al, Ni/Ag/Ni/Ag, reflecting layer
Material can be with are as follows: one of Au, Ag, NiAg, NiAu, AuBe, Ag/Ni/Ag, Ni/Al, Ni/Ag/Ni/Ag and medium material
Expect that one of silica, silicon nitride, ITO combination are formed.The material for bonding protective layer 302 is with antiacid caustic corrosion ability
Metal single layer is Cr, Pt, Ti, W, Au；Or bonding protective layer 302 is laminated construction, the material of laminated construction is Cr/Pt/Au,
Cr/Pt/Ag, Cr/Pt/Cr/Pt/Au/Ag, Ti/Pt/Au, Ti/W/Ti/Pt/Au.Bond another effect of protective layer 302
It is to be bound together with substrate bonding layer 203, it is desirable that bonding protective layer 302 is that the last layer material of laminated construction is not easy oxygen
Change, and there is preferable wellability, material Au, Ag, Cu, Pt, Au/Pt/Au with 203 material of adhesive layer.Preferably, this implementation
Bonding protective layer 302 uses Cr/Pt/Cr/Pt.../Au/Ag in example.Preferably, bond protective layer 302 with a thickness of 0.5~
10um, Cr/Pt period lamination with a thickness of 0.3~1um, Au/Ag with a thickness of 0.2~5um.
Fig. 3 is in substrate layer diagrammatic cross-section.Substrate layer includes supporting substrate 201, substrate front side protective layer 202, bonding
Layer 203, substrate back side protective layer 204 and contact layer 205.By the way of electron beam evaporation, first supporting substrate 201 just
Then face deposition substrate front protecting layer 202 is sequentially depositing substrate back side protective layer 204 in the reverse side of supporting substrate 201 and connects
Contact layer 205 finally deposits adhesive layer 203 on substrate front side protective layer 202.The supporting substrate 201 is silicon substrate, gold
Belong to any one of substrate, ceramic substrate or other composite substrates, the supporting substrate 201 of the present embodiment is silicon substrate, branch support group
Plate 201 with a thickness of between 60um~600um.Preferably, supporting substrate 201 with a thickness of between 80um~200um.It is preferred that
Ground, substrate front side protective layer 202 and substrate back side protective layer 204 are using the metal material with antiacid caustic corrosion ability.It is preferred that
Ground, using Cr, Pt, Au, W elemental metals or the laminated construction of alloy, material Cr/Pt/Cr/Au, Cr/Pt/Au, Pt/Au/
Pt/Au, Cr/Pt/TiW.With a thickness of 0.5um~10um.Preferably, contact layer 205 is using a kind of physical chemistry such as Pt, Au, Cu
The two or more metal laminated or conjunction such as the stable and single-layer metal with good heat conductive conductive material of property or Pt/Au/Pt/Au
Golden AuSn, AgSn etc., with a thickness of 0.1um~10um.Preferably, material used in adhesive layer 203 have lower fusing point or
With stronger diffusivity；Preferably, the material of the adhesive layer 203 is Sn, In, Pb, Bi, Sb, Zn low-melting-point metal
Or specific one kind in low-melting-point metal and the alloy (such as AuIn, AuSn, AgIn, AgSn) of Ag, Cu, Au, Al formation, structure are
The lamination that a kind of metal single layer or multiple layer metal are constituted, such as Sn, In, Au/AuSn, Ag/Sn, Ag/In, Au/Au.Preferably,
Adhesive layer 203 with a thickness of 0.5um~5um.
Fig. 4 is the diagrammatic cross-section after epitaxial layer is bonded with substrate layer.Epitaxial layer is using crystalline substance with being bonded for substrate layer
The mode of circle thermocompression bonding.For using Sn as 203 material of adhesive layer, it is preferable that the temperature of 2 inch wafer thermocompression bondings exists
230 DEG C~280 DEG C, pressure is in 100Kg~1000Kg.Being bonded is exactly that epitaxial layer and substrate is stacked together, by specific
Equipment applies temperature and pressure, and under temperature and pressure effect, adhesive layer 203 and bonding protective layer 302 are backmost between one layer
Metal phase counterdiffusion fuse to form alloy, thus realize epitaxial layer and substrate layer bonding purpose.Adhesive layer 203 and bonding
Protective layer 302 backmost passes through bonding, formation bonded layer 401 for one layer.Fig. 5 is to remove former growth substrates and the section of buffer layer shows
It is intended to.Growth substrates 101 in the present embodiment are gallium arsenide substrates, and removal gallium arsenide substrate is typically employed in NH4OH/H2O2It is molten
The method of wet etching is carried out in liquid.Removal growth substrates 101 and buffer layer 102, which are realized, is turned epitaxial layer by former growth substrates
Move to the process of the film transfer of substrate layer.
Fig. 6 is the diagrammatic cross-section that mask layer 501 is grown on sacrificial layer 103.501 material of mask layer is silica, nitrogen
One of thin film dielectrics material such as SiClx, nitrogen-oxygen-silicon, polyimides, plays N electrode preparation and chip surface roughening wet process is rotten
The effect of 103 material of sacrificial layer and 104 material of ohmic contact layer immediately below the protection of erosion process.Wherein, prepared by the mask layer 501
Method is one of the methods of chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or collosol and gel.Mask layer 501
With a thickness of 0.1um~5um.
Fig. 7 is the diagrammatic cross-section that N electrode preparation is completed.Its preparation process flow is: by photoetching process, in mask layer
501 surfaces obtain required 601 pattern counter structure of N electrode, are corroded by mask layer 501 and sacrificial layer 103, and patterning is turned
Move on to mask layer 501 and sacrificial layer 103.Wherein mask layer 501 and sacrificial layer 103 are prepared using the method for wet etching；It is preferred that
Ground, SiO2 mask layer are removed using buffer oxide (BOE) corrosive liquid, and for the epitaxial layer chip of AlGaInP base, removal is sacrificed
Layer 103 is using the progress wet etching acquisition in HCl/H2O solution.Then, N electrode 601 is carried out using electron beam evaporation to prepare.
The material of N electrode 601 can form low ohmic contact resistance with ohmic contact layer 104, and special with stable physical chemistry
Property and preferable thermal conductivity characteristic；Preferably, the N electrode 601 is the various metals in Au, Ge, Ni, Cr, Ti, Pt, Al
The laminated construction of composition, such as: Au/Ge/Ni/Au, Cr/Pt/Au, Al/Ti/Au, Al/Ti/Ni/Au.
In 601 preparation process of N electrode, mask layer 501 plays the role of wet etching exposure mask, can improve photoresist and sacrificial
601 lines low precision problem of N electrode caused by domestic animal 103 sidetracking of layer.
Fig. 8 is the diagrammatic cross-section that roughened layer preparation is completed.Its preparation process flow is: by photoetching process, in exposure mask
The corresponding structure of roughening pattern needed for 501 surface of layer obtain, it is rotten by mask layer 501, sacrificial layer 103 and ohmic contact layer 104
Erosion, is transferred to mask layer 501, sacrificial layer 103 and ohmic contact layer 104 for patterning, then, to the n-layer 105 of exposing into
Row roughening treatment obtains roughened layer 701.Wherein mask layer, sacrificial layer 103 and ohmic contact layer 104 use the side of wet etching
Method preparation；For example, SiO2Mask layer is removed using buffer oxide (BOE) corrosive liquid, and removal sacrificial layer 103 is using in HCl/H2O
Wet etching acquisition is carried out in solution, removal ohmic contact layer 104 is using in H3PO4/H2O2/H2Wet etching is carried out in O solution
It obtains.The method preparation that 105 roughing in surface of n-layer is combined using wet etching or dry etching or both, obtains roughened layer
701；Preferably, the epitaxial layer chip of AlGaInP base, 105 roughing in surface of n-layer are used in H2SO4/CH3COOH/NH4F、HCl/
Wet etching acquisition is carried out in aqueous solution, or is formed using chloro or fluorine-based plasma dry etching.
Fig. 9 show N electrode position partial enlargement diagram, it can be seen that leading in 103 corrosion process of sacrificial layer
The protective effect of mask layer 501 is crossed, the sidetracking of sacrificial layer 103 can be effectively avoided.In turn, it is possible to prevente effectively from Ohmic contact
Sidetracking in 104 corrosion process of layer, it can solve the problems, such as that 104 sidetracking bring N electrode 601 of ohmic contact layer falls off.
Figure 10 is a kind of reversed polarity LED with mask layer that n-layer 105 obtains after the completion by trimming and passivation technology
Chip profile schematic diagram.105 trimming of n-layer forms Cutting Road and is all made of the side that wet etching or dry etching or both combine
Method preparation；Trimming forms Cutting Road and uses HIO3/HCl/H2O solution, HBrO3/Br/H2The side of wet etching is carried out in O solution
Method, or using the method for carrying out dry etching in chloro or fluorine-based plasma.Passivation layer 801 is usually insulating dielectric materials,
Play the role of protecting semiconductor film material.For example, the materials such as silica, nitrogen-oxygen-silicon, silicon nitride and polyimides, passivation layer
801 using the preparation of the methods of chemical vapor deposition, physical vapour deposition (PVD), atomic layer deposition or collosol and gel.
In the preparation of N electrode 601 and 105 coarsening process of n-layer, mask layer 501 plays the role of wet etching exposure mask, can
To improve 601 lines precision controlling difference problem of N electrode caused by 601 preparation process photoresist of N electrode or 103 sidetracking of sacrificial layer,
Importantly, can solve in roughening process, N caused by 104 wet etching course sidetracking of sacrificial layer 103 and ohmic contact layer
Electrode 601 falls off problem, and effectively raise LED chip prepares yield.
Embodiment 2
Passivation layer structure can change, and as shown in figure 11, difference from Example 1 is, passivation layer 802 covers
In other all mesa regions in addition to 601 pad locations of N electrode.
Embodiment 3
The difference is that, mask layer 901 is grown on ohmic contact layer 104 with embodiment 1 or 2.As shown in figure 12, it goes
After growth substrates 101 and buffer layer 102, direct wet etching removes sacrificial layer 103.
Figure 13 show the diagrammatic cross-section that mask layer 901 is grown on ohmic contact layer 104.
Figure 14 show diagrammatic cross-section after the completion of prepared by N electrode 111, the difference is that, prepares with embodiment one
Process flow is: by photoetching process, obtaining required 111 pattern counter structure of N electrode on 901 surface of mask layer, passes through exposure mask
Layer 901 and sacrificial layer 103 corrode, and patterning is transferred to and sacrificial layer 103.Then, N electrode is carried out using electron beam evaporation
111 preparations.In N electrode preparation process, mask layer 901 plays the role of wet etching exposure mask, can improve photoresist sidetracking and lead
The N electrode lines low precision problem of cause.
Figure 15 is the diagrammatic cross-section that roughened layer preparation is completed.Its preparation process flow is: by photoetching process, in exposure mask
The corresponding structure of roughening pattern, is corroded by exposure mask 901 and ohmic contact layer 104, by patterning needed for 901 surface of layer obtain
It is transferred to mask layer 901 and ohmic contact layer 104, then, roughening treatment is carried out to the n-layer 105 of exposing, obtains roughened layer
121.In roughened layer preparation process, mask layer 901 plays the role of wet etching exposure mask, it is possible to prevente effectively from ohmic contact layer
N electrode 111 caused by 104 sidetrackings falls off problem.
Figure 16 is a kind of reversed polarity LED with mask layer that n-layer 105 obtains after the completion by trimming and passivation technology
Chip profile schematic diagram the difference is that, in finally obtained LED chip structure, does not include sacrificial layer with embodiment one
103。
As shown in figure 17, the utility model also proposes the reversed polarity with mask layer of a kind of embodiment 1 and embodiment 2
The preparation method of LED chip, comprising:
A, form epitaxial layer in the growth substrates 101, the epitaxial layer successively include from bottom to up buffer layer 102,
Sacrificial layer 103, ohmic contact layer 104, n-layer 105, luminescent layer 106 and p-type layer 107；
B, composite construction layer 301, bonding protective layer 302 are sequentially formed on the epitaxial layer；
C, supporting substrate 201 is provided, sequentially forms substrate front side protective layer 202, viscous in the front of the supporting substrate 201
Layer 203 is tied, sequentially forms substrate back side protective layer 204, contact layer 205 in the reverse side of the supporting substrate 201；
D, using wafer thermocompression bonding method, by adhesive layer 203 and protective layer 302 is bonded by the epitaxial layer and substrate
Layer is bound together；
E, the growth substrates 101, buffer layer 102 and sacrificial layer 103 are removed, the epitaxial layer of reverse polarity configuration is obtained, from
Top to bottm is followed successively by ohmic contact layer 104, n-layer 105, luminescent layer 106 and p-type layer 107；Or, removing the growth substrates 101
And buffer layer 102, the epitaxial layer of reverse polarity configuration is obtained, is followed successively by sacrificial layer 103, ohmic contact layer 104, N-shaped from top to bottom
Layer 105, luminescent layer 106 and p-type layer 107；
F, mask layer 901 is prepared on 104 surface of ohmic contact layer；Or, being prepared on 103 surface of sacrificial layer
Mask layer 901；
G, the corresponding mask layer 901 in removal 111 region of N electrode, prepares N electrode 111；Or, removal 111 region pair of N electrode
The mask layer 901 and sacrificial layer 103 answered prepare N electrode 111；
H, the corresponding mask layer 901 in removal 121 region of roughened layer, prepares roughened layer 121；Or, removal 121 region of roughened layer
Corresponding mask layer 901 and sacrificial layer 103, prepare roughened layer 121；
I, Cutting Road and passivation are formed by trimming, reversed polarity LED chip is made.
Finally, it should be noted that above embodiments are only to illustrate the technical solution of the utility model, rather than its limitations；
Although the utility model is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that:
It is still possible to modify the technical solutions described in the foregoing embodiments, or part of technical characteristic is carried out etc.
With replacement；And these are modified or replaceed, various embodiments of the utility model technology that it does not separate the essence of the corresponding technical solution
The spirit and scope of scheme.
Claims (5)
1. a kind of reversed polarity LED chip with mask layer, it is characterised in that: including substrate layer, bonded layer, bonding protective layer,
Composite construction layer, epitaxial layer, mask layer, N electrode and passivation layer；
The substrate layer sequentially consists of contact layer, substrate back side protective layer, supporting substrate, substrate front side protective layer；
The upper surface of described substrate layer sequentially consists of the bonded layer, bonding protective layer, composite construction layer；
The epitaxial layer sequentially consists of p-type layer, luminescent layer, N-shaped in the upper surface of described composite construction layer, the epitaxial layer
Layer, roughened layer and ohmic contact layer；
The mask layer, N electrode and passivation layer be set above the epitaxial layer, the mask layer the ohmic contact layer it
On, and it is corresponding with the N electrode figure, it is looped around around N electrode.
2. a kind of reversed polarity LED chip with mask layer according to claim 1, it is characterised in that:
The mask layer thickness is 0.1um~5um；
The bonded layer with a thickness of 1um~10um；
It is described bonding protective layer with a thickness of 0.1um~10um；
The composite construction layer with a thickness of 0.05um~2um；
The substrate front side protective layer with a thickness of 0.5um~10um；
The substrate back side protective layer with a thickness of 0.5um~10um；
The supporting substrate with a thickness of 60um~600um；
The contact layer with a thickness of 0.1um~10um.
3. a kind of reversed polarity LED chip with mask layer according to claim 1, it is characterised in that: the mask layer
Material be one of silica, silicon nitride, nitrogen-oxygen-silicon, Kapton dielectric material.
4. a kind of reversed polarity LED chip with mask layer according to claim 1, it is characterised in that: described ohm connects
It further include sacrificial layer in contact layer.
5. a kind of reversed polarity LED chip with mask layer according to claim 1, which is characterized in that the composite junction
Structure layer includes complementary structure layer, metal contact layer and reflecting layer.
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| CN201821327985.9U CN208538898U (en) | 2018-08-16 | 2018-08-16 | A kind of reversed polarity LED chip with mask layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037412A (en) * | 2018-08-16 | 2018-12-18 | 南昌大学 | A kind of reversed polarity LED chip and preparation method thereof with mask layer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109037412A (en) * | 2018-08-16 | 2018-12-18 | 南昌大学 | A kind of reversed polarity LED chip and preparation method thereof with mask layer |
| CN109037412B (en) * | 2018-08-16 | 2023-08-29 | 南昌大学 | Reverse polarity LED chip with mask layer and preparation method thereof |
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Address after: 999 No. 330000 Jiangxi province Nanchang Honggutan University Avenue Co-patentee after: NANCHANG GUIJI SEMICONDUCTOR TECHNOLOGY Co.,Ltd. Patentee after: Nanchang University Address before: 999 No. 330000 Jiangxi province Nanchang Honggutan University Avenue Co-patentee before: NANCHANG HUANGLYU LIGHTING Co.,Ltd. Patentee before: Nanchang University |