WO2020232587A1

WO2020232587A1 - Method for manufacturing semiconductor light-emitting element

Info

Publication number: WO2020232587A1
Application number: PCT/CN2019/087487
Authority: WO
Inventors: 贾月华; 吴俊毅; 王笃祥
Original assignee: 天津三安光电有限公司
Priority date: 2019-05-17
Filing date: 2019-05-17
Publication date: 2020-11-26
Also published as: CN111164766A; TWI719759B; CN111164766B; TW202044625A

Abstract

A method for manufacturing a semiconductor light-emitting element, comprising: acquiring a semiconductor sequence layer, comprising a first conduction type semiconductor layer, a light-emitting layer, a second conduction type semiconductor layer, and a third semiconductor layer, the third semiconductor layer serving as a first sacrificial layer on one side of the second conduction type semiconductor layer; etching the first sacrificial layer to form a plurality of openings; manufacturing ohmic contact blocks in the openings; manufacturing a second sacrificial block above each ohmic contact block; etching off the first sacrificial layer; manufacturing a fluoride insulating layer covering the second type conduction semiconductor layer and the second sacrificial blocks; and removing the plurality of second sacrificial blocks to form a fluoride insulating layer and a plurality of ohmic contact blocks covering the side of the second type conduction semiconductor layer. Using the third semiconductor layer as the first sacrificial layer in combination with using an insulating layer manufactured by CVD for the second sacrificial blocks can effectively control the size of the wide-top and narrow-bottom sacrificial blocks within a reasonable range, in order to obtain a fluoride insulating layer with uniform openings and a flat fluoride insulating layer.

Description

Method for manufacturing semiconductor light-emitting element

Technical field

It relates to a semiconductor light emitting element.

Background technique

Existing light-emitting diodes include a vertical type of light-emitting diode, which is obtained by a process of transferring semiconductor light-emitting sequences to other substrates such as silicon, silicon carbide or metal substrates, and removing the original epitaxial growth substrate, compared to horizontal Type, can effectively improve the technical problems of light absorption, current crowding or poor heat dissipation caused by the growth substrate. The transfer of the substrate is generally a bonding process, and the bonding is mainly metal-metal high-temperature and high-pressure bonding, forming a metal bonding layer between the side of the semiconductor light-emitting sequence and the substrate. The other side of the semiconductor sequence provides a light-emitting side, and the light-emitting side is equipped with a wire electrode to provide current injection or flow, and the substrate under the semiconductor sequence provides current flow and heat dissipation functions.

In order to improve the efficiency of light extraction, a metal reflective layer or a combination of a metal reflective layer and a current blocking layer are often designed on the side of the metal bonding layer to form an ODR reflective structure, which reflects the light from the metal bonding layer to the light exit side to improve the light output. effectiveness. The current blocking layer is usually silicon nitride, silicon oxide, magnesium fluoride or calcium fluoride. The fluoride has a lower refractive index and can promote reflection more, and has been widely used.

The electrically insulating layer is usually designed with openings to provide an ohmic contact area from one side of the reflective layer. The ohmic contact is usually a metal ohmic contact or a transparent conductive layer forming an ohmic contact. However, the current method is to make the fluoride insulating layer first and then make the metal ohmic contact. Designing the metal ohmic contact in the opening of the fluoride insulating layer will easily cause the edge of the metal ohmic contact block and the edge of the fluoride insulating layer to form a boundary. Area, causing light absorption, on the other hand, fluoride is difficult to etch with chemical solutions.

The CN2017106685523 patent discloses a method for peeling off magnesium fluoride: a sacrificial layer is formed on the first area of the upper surface of the substrate, and the sacrificial layer is wide in the top and narrow in the bottom; and deposited on the top surface of the substrate to be stripped The material layer of the material layer, because the sacrificial layer is wide at the top and narrow at the bottom, the part of the material layer covering the sacrificial layer is disconnected from the part covering the second area on the upper surface of the substrate; The sacrificial layer is thereby peeled off the material layer on the surface of the sacrificial layer. However, the cost of evaporating the metal sacrificial layer in this process is relatively high, the sacrificial layer requires two etching processes, and the selected metal etching solution is likely to have an etching effect on the ohmic contact block. If it is directly replaced with two CVD two different insulating layers, the two insulating layers are prone to etching reactions at different rates in the same etching solution, the side etching rate is difficult to control, and the shape and size of the hat with a wide top and a narrow bottom is not easy to control.

Summary of the invention

technical problem

The solution to the problem

Technical solutions

Based on the object of the present invention, the present invention provides a method for manufacturing a semiconductor light emitting element as follows, which includes:

Obtain a semiconductor light emitting sequence layer, including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;

Forming an ohmic contact block and a sacrificial block on the ohmic contact block on one side of the second conductive type semiconductor layer, wherein the ohmic contact block and the sacrificial block extend horizontally, and the horizontal area of the ohmic contact block is smaller than the horizontal area of the sacrificial block;

Growing a fluoride insulating layer to cover the ohmic contact block, the sacrificial block on the ohmic contact block, and one side of the second conductivity type semiconductor layer;

The sacrificial block is removed, and an insulating layer and a plurality of ohmic contact blocks are formed to cover the side of the second conductive type semiconductor layer.

Preferably, the steps of the ohmic contact block and the sacrificial block on the ohmic contact block are to first fabricate an ohmic contact layer, then fabricate multiple sacrificial blocks on the ohmic contact layer, and etch the ohmic contact layer to form multiple ohmic contact blocks.

Preferably, the material of the sacrificial block can be removed by an etching process different from that of the ohmic contact layer.

Preferably, one side of the second conductivity type semiconductor layer is a p-type semiconductor layer.

Preferably, the ohmic contact layer includes at least two metals.

Preferably, the method for removing the sacrificial block is BOE.

Preferably, the sacrificial block is a single layer or multiple layers.

Preferably, the sacrificial block is oxide and or nitride.

Preferably, the fluoride insulating layer is formed on the side of the second conductive type semiconductor layer in a form surrounding the ohmic contact block.

Preferably, the ohmic contact block is subjected to high temperature fusion treatment before the fluoride insulating layer is vaporized.

Preferably, the first electrode is made to be connected to the first conductivity type semiconductor layer, and the second electrode is made to be connected to the second conductivity type semiconductor layer.

Preferably, the second electrode is located on the same side of the fluoride insulating layer and the ohmic contact block.

Preferably, the second electrode includes a mirror layer, and the mirror layer covers the same side of the fluoride insulating layer and the ohmic contact block.

Preferably, the height of the sacrificial block is 2 to 4 times the height of the ohmic contact block.

The present invention also provides the following method for manufacturing a semiconductor light-emitting element, which includes:

Obtain a semiconductor sequence layer, including a first conductivity type semiconductor layer, a light emitting layer, a second conductivity type semiconductor layer, and a third semiconductor layer, the third semiconductor layer serving as the first sacrificial layer on the side of the second conductivity type semiconductor layer;

Etching the first sacrificial layer to form a plurality of openings;

Make an ohmic contact block in the opening;

Make a second sacrificial block above the ohmic contact block;

Etching and removing the first sacrificial layer;

Fabricating a fluoride insulating layer to cover the second conductive type semiconductor layer and the second sacrificial block;

A plurality of second sacrificial blocks are removed to form a fluoride insulating layer and a plurality of ohmic contact blocks covering the side of the second conductive type semiconductor layer.

Preferably, a second mask layer is made to cover the first sacrificial layer and the ohmic contact block; the second mask layer is etched to form a second sacrificial block above each ohmic contact block.

Preferably, the horizontal width or area of the second sacrificial block is larger than the horizontal width or area of the ohmic contact block.

Preferably, the materials of the first sacrificial layer, the second sacrificial block and the ohmic contact block are removed by different etching processes.

Preferably, the height of the second sacrificial block is 2 to 4 times the height of the ohmic contact block.

Preferably, the second sacrificial block is made of at least one layer of material different from the first sacrificial layer.

Preferably, the second sacrificial block is a material that can withstand the temperature of forming the local fluoride insulating layer.

Preferably, the material of the second mask block is at least one of nitride or oxide.

Preferably, the semiconductor light-emitting sequence layer is obtained by the MOCVD method.

Preferably, the first sacrificial layer is aluminum gallium arsenide or gallium arsenide.

Preferably, the ohmic contact block includes gold germanium, gold beryllium, gold germanium nickel or gold zinc.

Preferably, the ohmic contact block is subjected to high temperature fusion treatment before the formation of the fluoride insulating layer.

Preferably, the third semiconductor layer is grown on the P-type conductivity type semiconductor layer.

Preferably, the material of the second mask block is a combination of nitride and oxide.

Preferably, the thickness of the third semiconductor layer is at least 800 angstroms.

Preferably, the first electrode is made to be connected to the first conductivity type semiconductor layer, and the second electrode is made to be connected to the second conductivity type semiconductor layer. There is a mirror layer between the second electrode and the second conductivity type semiconductor layer, and the mirror layer covers On the same side of the fluoride insulating layer and the ohmic contact block.

The present invention also provides the following multi-layer semiconductor light-emitting sequence layer for manufacturing semiconductor light-emitting elements, which includes a multi-layer semiconductor light-emitting sequence layer, and the multi-layer semiconductor light-emitting sequence layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer;

The third semiconductor layer is arranged on the side of the P-type semiconductor layer, and the third semiconductor layer is aluminum gallium arsenide or gallium arsenide.

Preferably, the thickness of the third semiconductor layer is at least 800A.

The present invention also provides the following semiconductor light emitting element, which is characterized in that it comprises a semiconductor light emitting sequence layer, and the semiconductor light emitting sequence layer comprises a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;

One side of the semiconductor light emitting sequence layer includes a fluoride insulating layer, the fluoride insulating layer has a plurality of openings, the openings include ohmic contact blocks, and the sidewalls of the openings are inclined.

Preferably, the difference in the horizontal width of the ohmic contact block filled in each opening and an adjacent ohmic contact block is not more than ±0.5 μm or the difference between the ohmic contact block filled in each opening and an adjacent ohmic contact block The size difference does not exceed ±10% of the former.

Preferably, the inclination angle of the sidewall of the opening is 110° to 170° with respect to the side away from the semiconductor light emitting sequence layer.

Preferably, there is an ohmic contact block in the opening, and the size of the ohmic contact block is 2-10 μm.

Preferably, the electrical insulating layer is formed on the side of the p-type semiconductor layer.

Preferably, part of the semiconductor light-emitting sequence layer can be exposed in the opening of the fluoride insulating layer, and the width of the exposed semiconductor light-emitting sequence layer is 0 to 1 m.

The present invention also provides the following light emitting device, which includes the semiconductor light emitting element of the present invention and a circuit drive to obtain light radiation.

The beneficial effects of the invention

Beneficial effect

(1) The ohmic contact block and the sacrificial block above it are used to form a sacrificial block with a wide top and a narrow bottom to obtain a flat fluoride insulation layer. The sacrificial block is preferably a CVD insulation layer, which is easy to obtain in process, low cost, and etching process There is no damage to the ohmic contact block, and the size of the sacrifice block is easier to control.

(2) Using the third semiconductor layer as the first sacrificial layer can effectively control the uniformity of the width and size of the ohmic contact block, and combining the insulating layer made by CVD as the second sacrificial block, can effectively control the size of the sacrificial block with a wide upper and a narrow bottom Within a reasonable range, a fluoride insulating layer with uniform openings and a flat fluoride insulating layer can be obtained, and the third mask layer can be removed by wet etching.

Brief description of the drawings

Description of the drawings

Fig. 1 is a schematic flow chart of the manufacturing method of the first embodiment.

2 to 12 are schematic diagrams of structures obtained in each step of the manufacturing method of Embodiment 1.

FIG. 13 is a schematic structural diagram of the manufacturing method of the second embodiment.

14-25 are schematic diagrams of structures obtained in each step of the third embodiment.

Invention embodiment

Embodiments of the invention

The structure of the semiconductor light-emitting element of the present invention will be described in detail below in conjunction with the schematic diagram. Before further introducing the present invention, it should be understood that since specific embodiments can be modified, the present invention is not limited to the following specific Examples. It should also be understood that, since the scope of the present invention is only limited by the appended claims, the adopted embodiments are only for introduction, not for limitation. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art.

Example one

The embodiment of the present application provides a method for manufacturing a semiconductor light-emitting element, which can provide a simpler and low-cost process for forming an ohmic contact block and a fluoride insulating layer on the side of the semiconductor light-emitting sequence. The technical solutions provided by the embodiments of the present application are as follows, and the technical solutions provided by the embodiments of the present application will be described in detail with reference to FIG. 1. The embodiment of the present application provides the following method for manufacturing an LED chip with a roughened surface, including:

S1, obtaining a semiconductor light emitting sequence layer, including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;

S2, forming an ohmic contact block and a sacrificial block on the ohmic contact block, wherein the ohmic contact block and the sacrificial block extend horizontally, and the horizontal area of the ohmic contact block is smaller than the horizontal area of the sacrificial block;

S3, growing a fluoride insulating layer to cover the ohmic contact block, the sacrificial block on the ohmic contact block, and the second conductivity type semiconductor layer side;

S4, the sacrificial block is removed, and an insulating layer and a plurality of ohmic contact blocks are formed to cover the side of the second conductive type semiconductor layer.

The manufacturing method provided by the present application will be described in detail below with reference to the accompanying drawings, as shown in Fig. 2-Fig. 11 corresponding structural schematic diagrams of each step.

It should be noted that the following embodiments of the present application take a quaternary aluminum gallium indium phosphorous based light-emitting diode chip as an example for description, but the present application is not limited to this. In other embodiments of the present application, the light-emitting diode chip may also be a chip of other material systems, such as a ternary LED chip, which is not specifically limited in this application, such as aluminum gallium arsenide.

S1, obtaining a semiconductor light emitting sequence layer, including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer.

The semiconductor light emitting sequence is formed on the growth substrate 201. As shown in FIG. 2, the corresponding growth substrate 201 may be formed of at least one of sapphire (Al ₂ O ₃ ), SiC, GaAs, GaN, ZnO, Si, GaP, InP, Ge, and Ga ₂ O ₃ , but is not limited to this. The semiconductor light emitting sequence includes a first conductivity type semiconductor layer 108, a light emitting layer 107, and a second conductivity type semiconductor layer 106. In order to ensure the quality of epitaxial growth, a buffer layer is usually fabricated on the growth substrate, or for subsequent removal of the growth substrate, an over layer, an etching stop layer, etc. can be fabricated on the growth substrate. In this embodiment, the growth substrate 201 is a gallium arsenide substrate, in which the first conductivity type semiconductor layer 108, the light emitting layer 107, and the second conductivity type semiconductor layer 106 are aluminum indium phosphorus, aluminum gallium indium phosphorus, aluminum gallium arsenide, and Multilayer materials of any combination of gallium arsenide materials, emitting wavelengths of red light or infrared. In this embodiment, the growth substrate 201 is a gallium arsenide substrate, in which the first conductivity type semiconductor layer 108, the light emitting layer 107, and the second conductivity type semiconductor layer 106 are aluminum indium phosphorus, aluminum gallium indium phosphorus, aluminum gallium arsenide, and Multilayer materials of any combination of gallium arsenide materials, emitting wavelengths of red light or infrared.

This application can use MOCVD, metal organic compound chemical vapor deposition technology to obtain semiconductor light-emitting sequence. The first conductivity type and the second conductivity type are n-type or p-type conductivity types, respectively.

Taking this embodiment as an example, the first conductivity type is a conventional n-type, and the second conductivity type is a conventional p-type, but it is not limited to this, and is also the opposite doping type.

The first conductivity type semiconductor layer 108 includes at least an n-type capping layer to provide electrons, and may further include an n-type window layer, an n-type gallium arsenide providing electrode and an ohmic contact on one side of the first conductivity type semiconductor layer, and a second conductivity type semiconductor layer 106 It includes at least a p-type capping layer to provide holes, and may further include a window layer of p-type gallium phosphide to provide current expansion and ohmic contact.

Specifically, the functions and parameters of each layer can refer to Table 1 below.

S2, forming an ohmic contact block and a sacrificial block on the ohmic contact block.

The ohmic contact block provided in the present application may be at least one of a metal composition of gold zinc, gold germanium, gold germanium nickel, or gold beryllium, which functions to provide an ohmic contact with one side of the second conductive type semiconductor layer 106. In this embodiment, the ohmic contact block 105 is formed by forming a gold-zinc layer first, and the gold-zinc layer can be obtained by a conventional evaporation process. The material thickness of the gold-zinc layer is 50-500 nm, more preferably 50-150 nm, and 100 nm in this embodiment.

As shown in FIG. 4, a mask layer for making the sacrificial block 204 is formed on the gold-zinc layer of the ohmic contact block 105, and the mask layer is further etched to form the sacrificial block. The material of the mask layer can be It is removed by an etching process different from the ohmic contact block. More preferably, the material can withstand the subsequent evaporation temperature of magnesium fluoride.

The material of the mask layer in this embodiment is nitride or oxide. As an implementation mode, the mask layer may be a layer of silicon nitride or silicon oxide grown by CVD, or a combination of silicon nitride and silicon oxide, It is more preferable to grow a silicon oxide layer and then grow a silicon nitride layer. The thickness of this layer is 100 to 500 nm. Preferably, the thickness of the layer is 2 to 4 times that of the ohmic contact layer.

As shown in FIG. 5, a photoresist pattern 203 is then formed on the surface of the mask layer 204. Using the photoresist pattern 203 as a mask, BOE etching is performed on the mask layer of silicon nitride or silicon oxide to form multiple sacrificial blocks 204. More preferably, the mask layer 204 is silicon nitride. The etching rate of silicon nitride is lower than that of silicon nitride. Therefore, the etching time can be effectively controlled under the photoresist pattern 203 to ensure that the remaining width of the mask layer 204 forms a sacrificial block 204. Or the mask layer 204 is a layer of a silicon oxide layer laminated with a silicon nitride layer. The horizontal width of the mask layer is preferably at least 2 μm larger than the horizontal width of the ohmic contact layer.

As shown in FIG. 6, using the combination of the sacrificial block 204 and the photoresist pattern 203 as a mask, a conventional etching solution such as a gold etching solution (the main component is potassium iodide) is selected to etch gold and zinc to obtain an ohmic contact block 105. The ohmic contact block 105 can be Distributed in many places. The horizontal width dimension of the ohmic contact block 105 is 1-10 μm, more preferably 2-7 μm, and more preferably an average size of 5 μm. The thickness of the ohmic contact block is 80-200 μm.

The photoresist pattern 203 is removed, and the sacrificial block 204 is exposed.

In order to form an ohmic contact between the ohmic contact block and one side of the second conductivity type semiconductor layer, it is annealed to form an ohmic contact fusion. The conditions of the high temperature treatment are 400-520°C, the preferred temperature is 460-500°C, and the time is 1-60 min, preferably 10-20 min. Before growing the fluoride insulating layer, the ohmic contact block is fused to form an ohmic contact.

S3, growing a fluoride insulating layer to cover the ohmic contact block, the sacrificial block on the ohmic contact block, and one side of the second conductivity type semiconductor layer.

As shown in FIG. 7, the fluoride insulating layer 104 is obtained by a common process such as evaporation technology, and the evaporation conditions are at least 120°C, or about 200°C or higher, about 300°C. The higher the temperature, the denser the film. The better the sex. The material of the fluoride insulating layer is magnesium fluoride or calcium fluoride, and the thickness is preferably 50-500 nm, and more preferably 100-200 nm.

The BOE etching technique is used to remove the mask layer 204 and the fluoride insulating layer on its surface. As shown in FIG. 8, the ohmic contact block 105 and the fluoride insulating layer 104 surrounding the ohmic contact block are left to cover the surface side of the second conductive type semiconductor layer 106. That is, the fluoride insulating layer 104 forms an opening, and there is an ohmic contact block 105 in the opening. The ohmic contact block 105 and the fluoride insulating layer 104 divide the surface side of the second conductive type semiconductor layer 106 into an ohmic contact area and an electrical insulating area.

In this embodiment, since the ohmic contact block and the sacrificial block have a wide upper and a narrow shape, combined with the evaporation process, the automatic fracture of the fluoride insulating layer on the sidewall is promoted to obtain a flat fluoride insulating layer covering the second Conductive type surface, and an opening with a flat surface is formed around the ohmic contact block.

In order to form an external electrical connection for the semiconductor light-emitting sequence, it also includes making the first electrode and the second electrode to form electrical connections with the first conductive type semiconductor layer and the second conductive type semiconductor layer of the semiconductor light-emitting sequence. The usual steps of making to obtain:

S5, as shown in FIG. 9, the mirror layer 103, the diffusion barrier layer and the bonding layer 102 are sequentially grown on the side of the ohmic contact block and the fluoride insulating layer.

The mirror layer 103 may be formed of a metal or alloy containing at least one of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, and Hf. The function of the mirror layer 103 is to reflect the light on one side of the semiconductor light-emitting sequence back into the semiconductor light-emitting sequence and emit light from the opposite side or side. The metal bonding layer 102 usually uses metals such as gold, tin, titanium, nickel, platinum, etc. The metal bonding layer itself may be a combination of multiple layers of materials. A metal barrier layer (not shown in the figure) may also be included between the mirror layer 103 and the metal bonding layer 102. The function of the metal barrier layer is to prevent the metal of the reflective layer, such as silver, from spreading to the bonding metal layer side. To affect the reflection effect, the material of the metal barrier layer can be selected from barrier metal materials such as titanium, platinum, and chromium. The above-mentioned mirror layer 103, diffusion barrier layer and bonding layer 102 can be obtained in sequence through a conventional evaporation process.

S6, bonding the substrate and removing the growth substrate.

As shown in FIG. 10, a conductive support substrate 101 is prepared. The metal bonding layer 102 is used as an adhesive layer to adhere the conductive support substrate 101 to the surface of the semiconductor light emitting sequence. Although a high temperature bonding process may be used to couple the conductive support substrate through a bonding layer in the current embodiment, the conductive support substrate may be formed using a plating or deposition process.

The growth substrate 201 is removed. The growth substrate 201 can be removed by grinding, laser lift-off, or wet etching according to actual materials. The gallium arsenide substrate of this embodiment can be removed by wet etching to expose the surface of the second conductive type semiconductor layer 108.

S7, fabricating the first electrode and the second electrode.

As shown in FIG. 11, the first electrode 109 and the second electrode 100 are fabricated. The first electrode 109 includes a main pad electrode 1091 and an extension electrode 1092 on the surface of the second conductivity type semiconductor layer 108, wherein the main pad electrode 1091 is fixed With a block-like area, the extension electrode 1093 extends on the surface of the second conductive type semiconductor layer 108 along the periphery of the main pad electrode 1091, and extends to the edge side. In order to form a good ohmic contact between the main pad electrode 1091 and the extension electrode 1093 and the surface of the second conductivity type semiconductor layer 108, the second conductivity type semiconductor layer 108 may include a doped epitaxial ohmic contact layer such as gallium arsenide or For gallium phosphide, the epitaxial ohmic contact layer can be selectively retained only in the part below the extension electrode, and the remaining part is etched away to prevent the light absorption effect of the layer.

The second electrode 100 is located on the back side of the substrate, and can optionally be formed by evaporation of elements such as gold and platinum.

S8, separate and form a single semiconductor light-emitting element.

The exposed surface of the second conductive type semiconductor layer 108 is roughened or patterned to facilitate light emission.

The semiconductor light-emitting sequence is separated into unit chip areas by a chip separation process, and a passivation layer can be formed at least on the sidewall and the light-emitting side of the semiconductor light-emitting sequence, and then separated by a subsequent cutting process to form multiple independent chips.

This process realizes that gold-zinc is made first, and the insulating layer made of gold-zinc and CVD is used as the top width and the bottom narrow shape. The process is simple. Compared with the process of vapor deposition of metal, the mask layer made by CVD is simpler and takes less time. Cost advantage, no additional process of stripping the ohmic contact block.

Example two

As an alternative implementation of the first embodiment, the mask layer 204 is a layer of silicon oxide layer laminated with a silicon nitride layer, wherein the etching process of the silicon nitride layer is slower than that of the silicon nitride layer, such as As shown in FIG. 13, the formed sacrificial block 204 is wide at the bottom and narrow at the bottom. Through this design, it is easier to realize the automatic fracture of the magnesium fluoride on the sidewall of the sacrificial block, and promote the flatness of the magnesium fluoride layer. In addition, silicon nitride and silicon oxide can be obtained by two consecutive growth steps in the same growth furnace, the process is simple, and the feasibility is high.

Example three

As described in the first embodiment, the mask layer is made by CVD, and then the sacrificial block produced by CVD is etched with the photoresist pattern as a mask, which can effectively control the size of the sacrificial block, and use the sacrificial block as a mask to perform the ohmic contact layer Horizontal etching and lateral etching obtain the ohmic contact block under the sacrificial block. However, the ohmic contact block is obtained through a wet etching process. Because the ohmic contact block is usually thin, such as 100 nm, it is difficult to control the side etching. The etched ohmic contact block is prone to uneven size and size, which will cause uneven photoelectric parameters.

The method provided in this embodiment is further improved, and the size of the ohmic contact block can be further uniformly controlled, so as to control the ohmic contact block and the sacrificial block to form a uniform size mask pattern with a wide upper and a narrow lower surface, which is beneficial to obtain a uniform opening and surface The flat fluoride insulating layer improves the photoelectric performance.

The manufacturing method of this embodiment is shown in a flowchart of operation steps in FIG. 14.

S1, obtaining a semiconductor sequence layer, including a first conductivity type semiconductor layer, a light emitting layer, a second conductivity type semiconductor layer and a third semiconductor layer, the third semiconductor layer being formed as a first sacrificial layer on the side of the second conductivity type semiconductor layer.

In this embodiment, as shown in FIG. 15, the growth substrate 201 is a gallium arsenide substrate, in which the distribution, parameters and functions of the first conductivity type semiconductor layer 108, the light emitting layer 107 and the second conductivity type semiconductor layer 106 are shown in the table One. After the growth of the second conductive type semiconductor layer 106 is completed, the third semiconductor layer 306 is continuously grown.

Preferably, the third semiconductor layer 306 is gallium arsenide or aluminum gallium arsenide. The aluminum gallium arsenide and gallium arsenide can be obtained by conventional epitaxial production methods. For example, the production process conditions of the gallium arsenide can be the same as the first conductivity type semiconductor layer. The n-type ohmic contact layer in is close to or the same, and gallium arsenide and aluminum gallium arsenide do not need to be doped. The third semiconductor layer 306 is used as a mask and a sacrificial layer later, so the etching process of this layer will not damage the second conductive semiconductor layer 106 at least. In this embodiment, gallium arsenide is preferred. The thickness of the gallium arsenide is at least 80 nm. In this embodiment, it is 150 nm, which can be directly removed by a wet etching process.

S2, etching the first sacrificial layer to form a plurality of openings.

As shown in FIG. 16, a photoresist pattern 305 is formed on the surface of the third semiconductor layer 306. Using the photoresist pattern 305 as a mask, the third semiconductor layer 306 is wet-etched, and the third semiconductor layer 306 obtains a plurality of open regions. Etching liquid can choose to use a diluent mixed with H ₃ PO ₄ and H ₂ O ₂ .

S3, making an ohmic contact block in the opening.

As shown in FIG. 17, a layer of the ohmic contact block 105 is fabricated, and the selection of the material and thickness of the ohmic contact block 105 is the same as in the first embodiment.

As shown in FIG. 18, the photoresist pattern 305 is removed, and a plurality of opening regions of the third semiconductor layer 306 are filled with a plurality of ohmic contact blocks 105. Since the ohmic contact block in the first embodiment is formed by wet etching using a silicon nitride or silicon oxide sacrificial block as a mask. In the wet etching process of the ohmic contact layer, due to the uneven side etching, it is difficult to control the lateral etching rate under the sacrificial block to be uniform, which will easily cause the sacrificial block and the ohmic contact block to be asymmetry up and down, resulting in a fluoride insulating layer Uneven. In this embodiment, the ohmic contact block 105 is filled in the opening of the first sacrificial layer and the photoresist stripping technology can avoid the problem of uneven side etching rate of the ohmic contact block. The thickness of the ohmic contact block 105 is preferably at least 80 nm, and is 150 nm in this embodiment. Preferably, the thickness of the ohmic contact block 105 and the third semiconductor layer are the same, or a difference of ±10% in thickness at most.

S4, forming a second sacrificial block above the ohmic contact block.

As shown in FIG. 19, a mask layer 304 of silicon nitride or silicon oxide is CVD on the surface of the ohmic contact block 105 and the third semiconductor layer 306. The thickness of this layer is 100-500 nm, and the thickness of the CVD is the third The thickness of the semiconductor layer is preferably 2 to 4 times, and more preferably about 400 nm. Among them, CVD silicon nitride or silicon oxide can be used, but since the etching rate of silicon oxide is faster and it is difficult to control the etching time, the silicon nitride material is preferred.

Then a photoresist pattern 303 is formed above the ohmic contact block 105. The photoresist is located above the ohmic contact block 105 as symmetrically as possible.

As shown in FIG. 20, the mask layer 304 of silicon nitride or silicon oxide is BOE etched with the photoresist 303 as a mask, and a second sacrificial block 304 is formed above the ohmic contact block. Since the photoresist pattern 303 is easily aligned with the position of the ohmic contact block 105 in the vertical direction, the degree of overlap is high. Therefore, it is easy to obtain an overlapping and symmetrical alignment of the second sacrificial block 304 with the ohmic contact block 105 in the vertical direction. Preferably, the horizontal width or area of the second sacrificial block 304 is larger than that of the ohmic contact block 105.

Preferably, the horizontal width dimension of the second sacrificial block 304 is at least 2 μm larger than the horizontal width dimension of the ohmic contact block 105, preferably greater than 2 to 3 μm, and smaller than this width dimension will cause the slope to be reduced and the fluoride electrical insulating layer covers It is not easy to automatically form a fracture surface at the part of the side wall of the second sacrifice fast, and it is easy to cause burrs to form on the edge of the opening of the fluoride electrical insulating layer after the second sacrifice block is removed. More preferably, the thickness of the second sacrificial block 304 is greater than the thickness of the ohmic contact block 105, and more preferably, the former is 2 to 4 times the thickness of the latter. And preferably, the thickness of the ohmic contact block is greater than or equal to the thickness of the fluoride insulating layer. This height difference is beneficial to the area covered by the fluoride insulating layer on the sidewall of the second sacrificial block 304 and directly covering the second conductive layer. The fluoride insulating layer on the side of the type semiconductor layer automatically breaks, which can effectively avoid the angle of the edge of the fluoride opening, and at the same time, the inclination angle of the inner side wall of the fluoride insulating layer opening can be obtained, which is beneficial to obtain a flat fluoride electrical insulating layer The smooth surface of the mirror layer and the subsequent evaporation of the mirror layer.

The horizontal width dimension of the second sacrificial block 304 in this embodiment is at least larger than the ohmic contact block 105 and controlled to be about 2 μm, wherein the thickness of the second sacrificial block 304 is 400 nm.

As shown in FIG. 21, the third semiconductor layer 306 is removed by wet etching, and then the photoresist 303 is removed, exposing the side of the second sacrificial block 304 and the second conductive semiconductor layer 106. The thickness of GaAs is at least 100 nm, preferably 150 nm. Too thin causes the cross-sectional area to be too small and the solution cannot be immersed, which makes the GaAs easy to be side-etched and not clean, and it is easy to leave GaAs on the side of the second conductivity type semiconductor layer 106. GaAs should not be too thick. Too thick will cause too long etching time and waste cost.

S5, growing a fluoride insulating layer to cover one side of the second sacrificial block and the second conductive type semiconductor layer.

As shown in FIG. 22, the fluoride insulating layer 104 is grown on the side of the second conductive semiconductor layer 106 and on the surface of the second sacrificial block 304, and the growth conditions and thickness are the same as in the first embodiment.

The BOE etching technique is used to remove the second mask layer 304 of silicon nitride or silicon oxide and the fluoride insulating layer on its surface. As shown in FIG. 23, the ohmic contact block 105 and the fluoride insulating layer 104 surrounding the ohmic contact block are left to cover the surface side of the second conductive type semiconductor layer 106. The ohmic contact block 105 and the fluoride insulating layer 104 divide the surface side of the second conductive type semiconductor layer 106 into an ohmic contact area and an electrical insulating area.

In order to form an external electrical connection for the semiconductor light-emitting sequence, it also includes making the first electrode and the second electrode to form electrical connections with the first conductive type semiconductor layer and the second conductive type semiconductor layer of the semiconductor light-emitting sequence, which can be specifically implemented. The S5-S8 of Example 1 were obtained by the same process.

In this embodiment, the third semiconductor layer is used as the first sacrificial layer, preferably gallium arsenide. An opening is provided on the first sacrificial layer, and an ohmic contact block 105 is formed in the opening, which can more accurately control the size uniformity of the sacrificial block. The technical problems of uneven size and uneven photoelectric characteristics of the ohmic contact block of the first embodiment can be avoided, and the uniformity of the photoelectric characteristics can be effectively improved. In addition, the first sacrificial layer and the second sacrificial block need to use different materials, and use different etching processes to ensure that the first sacrificial layer will not be etched when the second sacrificial block is produced by subsequent etching, and the first sacrificial layer will not be etched when the first sacrificial layer is removed. The second sacrificial block will be etched. The second sacrificial block is made by CVD process, which has low cost and short process time.

The ohmic contact block is located in the opening of the fluoride insulating layer, and it is easy to control the vertical symmetry of the second sacrificial block and the ohmic contact block, and it is easy to realize that the ohmic contact block is symmetrically located in the opening of the fluoride insulating layer. Through the design of the ohmic contact block and the second sacrificial block with a wide top and a narrow bottom, as shown in FIG. 23, it can be obtained that the inner sidewall of the opening of the fluoride insulating layer is inclined, which is beneficial to subsequently obtain a flat reflective layer. Preferably, the angle of inclination is between 110° and 170°. FIG. 24 is a top view of the structure shown in FIG. 23 from the side of the electrical insulating layer 104, and FIG. 25 is a partial enlarged schematic view of FIG. 24.

The horizontal width of the ohmic contact block can be uniformly controlled by the opening design of the first sacrificial layer. Specifically, the horizontal width dimension D1 of the ohmic contact block is 1-10 μm, more preferably 2-7 μm, this embodiment It is 5μm. By controlling the width of the second sacrificial block to be at least 2μm larger than the horizontal width of the ohmic contact block, the horizontal width dimension D2 of the opening of the insulating layer 104 can be controlled to be greater than D1 by at least 0.5μm. In this embodiment, it is about 2μm, and each opening is filled The size difference between the ohmic contact block and the adjacent ohmic contact block does not exceed ±10% of the former.

There may be a certain distance D3 between the bottom edge of the sidewall of the opening and the edge of the ohmic contact block 105, so that a part of the second conductive type semiconductor layer 106 is exposed. Generally, D3 is 0˜1 um. The exposed part of the area is small and directly contacted by the reflective layer, which will not have a significant impact on the photoelectric performance.

The cross-sectional shape of the opening is usually made into a circle or an ellipse according to the shape of the ohmic contact block, and can also be made into a square or polygon.

The semiconductor light-emitting element obtained by the present invention can be packaged, such as a ceramic or EMC bracket, to obtain a package body, or directly mounted on a circuit substrate of an application product to obtain a light-emitting device, which can be widely used in lighting, display, identifier and other fields.

Example four

As an alternative embodiment, the third semiconductor may be aluminum gallium arsenide (AlxGa1-xAs), 0<x<1. Preferably, the maximum value of x is 0.45 and the minimum value is 0.25. Preferably, the thickness is at least 100 nm, preferably 150 nm. The aluminum content and thickness can also be conventionally adjusted according to the etching rate. The etching solution can be H ₃ PO ₄ and H ₂ O ₂ .

Example five

As an alternative to the third embodiment, the second sacrificial block 304 is obtained by further BOE etching with a layer of silicon nitride layer laminated on a silicon oxide layer. Since the etching process of the silicon nitride layer is slower than that of the silicon nitride layer, the second sacrificial block 304 itself can be formed by etching in the same BOE step. As an embodiment, the thickness of silicon nitride is 400 nm and the thickness of silicon dioxide is 200 nm. The thickness of the ohmic contact block is 150 nm, and the thickness of the insulating layer fluoride is 100 nm. Through this design, it is easier to realize that the magnesium fluoride forms a fracture on the sidewall of the sacrificial block, promotes the flatness of the magnesium fluoride layer, and silicon nitride and silicon oxide can be obtained by two consecutive growth steps in the same growth furnace. The process is simple and feasible.

The above-mentioned embodiments only exemplarily illustrate the principles and effects of the present invention, and are not used to limit the present invention. Anyone familiar with this technology can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims

A method of manufacturing a semiconductor light-emitting element, which includes:

Obtain a semiconductor light emitting sequence layer, including a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;

Forming an ohmic contact block and a sacrificial block on the ohmic contact block on one side of the second conductive type semiconductor layer, wherein the ohmic contact block and the sacrificial block extend horizontally, and the horizontal area of the ohmic contact block is smaller than the horizontal area of the sacrificial block;

Growing a fluoride insulating layer to cover the ohmic contact block, the sacrificial block on the ohmic contact block, and one side of the second conductivity type semiconductor layer;

The sacrificial block is removed, and an insulating layer and a plurality of ohmic contact blocks are formed to cover the side of the second conductive type semiconductor layer.
The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the material of the sacrificial block can be removed by an etching process different from that of the ohmic contact layer.
The method of manufacturing a semiconductor light-emitting element according to claim 1, wherein the step of the ohmic contact block and the sacrificial block on the ohmic contact block is to first fabricate the ohmic contact layer, and then fabricate multiple sacrificial blocks on the ohmic contact layer. Above, etch the ohmic contact layer to form multiple ohmic contact blocks.
The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the ohmic contact layer includes at least two metals.
The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the method for removing the sacrificial block is BOE.
A method of manufacturing a semiconductor light emitting element according to claim 1, wherein the sacrificial block is a single layer or multiple layers.
A method of manufacturing a semiconductor light-emitting element according to claim 1, wherein the sacrificial block is oxide and or nitride.
A method of manufacturing a semiconductor light emitting element according to claim 1, wherein the fluoride insulating layer is formed on the side of the second conductivity type semiconductor layer in a form surrounding the ohmic contact block.
The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the ohmic contact block is subjected to a high temperature fusion process before the fluoride insulating layer is vapor-grown.
The method of manufacturing a semiconductor light-emitting element according to claim 1, wherein the first electrode is made to be connected to the first conductivity type semiconductor layer, and the second electrode is made to be connected to the second conductivity type semiconductor layer.
10. The method of manufacturing a semiconductor light emitting element according to claim 10, wherein the second electrode is located on the same side of the fluoride insulating layer and the ohmic contact block.
10. The method of manufacturing a semiconductor light emitting element according to claim 10, wherein the second electrode comprises a mirror layer, and the mirror layer covers the same side of the fluoride insulating layer and the ohmic contact block.
A method of manufacturing a semiconductor light emitting element according to claim 1, wherein the height of the sacrificial block is 2 to 4 times the height of the ohmic contact block.
A method of manufacturing a semiconductor light-emitting element, which includes:

Obtain a semiconductor sequence layer, including a first conductivity type semiconductor layer, a light emitting layer, a second conductivity type semiconductor layer, and a third semiconductor layer, the third semiconductor layer serving as the first sacrificial layer on the side of the second conductivity type semiconductor layer;

Etching the first sacrificial layer to form a plurality of openings;

Make an ohmic contact block in the opening;

Make a second sacrificial block above the ohmic contact block;

Etching and removing the first sacrificial layer;

Fabricating a fluoride insulating layer to cover the second conductive type semiconductor layer and the second sacrificial block;

A plurality of second sacrificial blocks are removed to form a fluoride insulating layer and a plurality of ohmic contact blocks covering the side of the second conductive type semiconductor layer.
According to a method of manufacturing a semiconductor light-emitting element, it is characterized in that: a second mask layer is made to cover the first sacrificial layer and the ohmic contact block; the second mask layer is etched to form a second sacrificial layer above each ohmic contact block Piece.
A method for manufacturing a semiconductor light emitting element according to claim 14, wherein the horizontal width or area of the second sacrificial block is larger than the horizontal width or area of the ohmic contact block.
A method of manufacturing a semiconductor light emitting element according to claim 14, wherein the materials of the first sacrificial layer, the second sacrificial block, and the ohmic contact block are removed by different etching processes.
A method of manufacturing a semiconductor light emitting element according to claim 14, wherein the height of the second sacrificial block is 2 to 4 times the height of the ohmic contact block.
14. The method of manufacturing a semiconductor light emitting element according to claim 14, wherein the second sacrificial block is made of at least one layer of material different from the first sacrificial layer.
14. The method of manufacturing a semiconductor light emitting element according to claim 14, wherein the second sacrificial block is a material that can withstand the temperature of forming the local fluoride insulating layer.
18. The method for manufacturing a semiconductor light emitting element according to claim 19, wherein the material of the second mask block is at least one of nitride or oxide.
The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein the semiconductor light-emitting sequence layer is obtained by the MOCVD method.
The method of manufacturing a semiconductor light emitting element according to claim 14, wherein the first sacrificial layer is aluminum gallium arsenide or gallium arsenide.
The method of manufacturing a semiconductor light emitting element according to claim 14, wherein the ohmic contact block is made of gold germanium, gold beryllium, gold germanium nickel or gold zinc.
14. The method for manufacturing a semiconductor light emitting element according to claim 14, wherein the ohmic contact block is subjected to high temperature fusion treatment before the fluoride insulating layer is formed.
A manufacturing method for manufacturing a semiconductor light emitting element according to claim 14, wherein the third semiconductor layer is grown on the P-type conductivity type semiconductor layer.
A manufacturing method for manufacturing a semiconductor light-emitting element according to claim 14, wherein the material of the second mask block is a combination of nitride and oxide.
The manufacturing method for manufacturing a semiconductor light emitting element according to claim 14, wherein the thickness of the third semiconductor layer is at least 800 angstroms.
The method for manufacturing a semiconductor light-emitting element according to claim 14, wherein the first electrode is made to be connected to the first conductive type semiconductor layer, the second electrode is made to be connected to the second conductive type semiconductor layer, and the second electrode is connected to There is a mirror layer between the second conductive type semiconductor layers, and the mirror layer covers the same side of the fluoride insulating layer and the ohmic contact block.
A multi-layer semiconductor light-emitting sequence layer for manufacturing a semiconductor light-emitting element, which includes a multi-layer semiconductor light-emitting sequence layer, and the multi-layer semiconductor light-emitting sequence layer includes an N-type semiconductor layer, a light-emitting layer and a P-type semiconductor layer;

The third semiconductor layer is arranged on the side of the P-type semiconductor layer, and the third semiconductor layer is aluminum gallium arsenide or gallium arsenide.
The multilayer semiconductor light-emitting sequence layer for manufacturing a semiconductor light-emitting element according to claim 30, wherein the thickness of the third semiconductor layer is at least 800A.
A semiconductor light emitting element, characterized in that it comprises a semiconductor light emitting sequence layer, and the semiconductor light emitting sequence layer comprises a first conductivity type semiconductor layer, a light emitting layer and a second conductivity type semiconductor layer;

One side of the semiconductor light emitting sequence layer includes a fluoride insulating layer, the fluoride insulating layer has a plurality of openings, the openings include ohmic contact blocks, and the sidewalls of the openings are inclined.
A semiconductor light-emitting element according to claim 32, wherein the opening has an ohmic contact block, and the size of the ohmic contact block is 2-10 μm.
The semiconductor light-emitting element according to claim 33, wherein the difference in the horizontal width of the ohmic contact block filled in each opening and the adjacent ohmic contact block is not more than ±0.5 μm or each opening The size difference between the ohmic contact block filled in the middle and an adjacent ohmic contact block does not exceed ±10% of the former.
A semiconductor light emitting element according to claim 32, wherein the fluoride insulating layer is inclined at an angle of 110 to 170° on the side wall of the opening.
A semiconductor light emitting element according to claim 32, wherein said electrically insulating layer is formed on the side of the p-type semiconductor layer.
A semiconductor light emitting element according to claim 32, wherein a part of the semiconductor light emitting sequence layer can be exposed in the opening of the fluoride insulating layer, and the width of the exposed semiconductor light emitting sequence layer is 0 to 1 μm.
A light emitting device, which comprises adopting the semiconductor light emitting element according to any one of claims 32 to 37 and a circuit drive to obtain light radiation.