CN109037412B - Reverse polarity LED chip with mask layer and preparation method thereof - Google Patents
Reverse polarity LED chip with mask layer and preparation method thereof Download PDFInfo
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- CN109037412B CN109037412B CN201810937533.0A CN201810937533A CN109037412B CN 109037412 B CN109037412 B CN 109037412B CN 201810937533 A CN201810937533 A CN 201810937533A CN 109037412 B CN109037412 B CN 109037412B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
Abstract
The invention relates to a reverse polarity LED chip with a mask layer, which comprises a substrate layer, a bonding protection layer, a composite structure layer, an epitaxial layer, the mask layer, an N electrode and a passivation layer; the upper surface of the substrate layer is provided with a bonding layer, a bonding protection layer and a composite structure layer from bottom to top in sequence; the epitaxial layer is arranged on the composite structural layer, and the epitaxial layer comprises a p-type layer, a luminescent layer, an n-type layer, a coarsening layer and an ohmic contact layer from bottom to top in sequence; and a mask layer, an N electrode and a passivation layer are arranged on the epitaxial layer, and the mask layer is arranged on the ohmic contact layer, corresponds to the N electrode pattern and surrounds the N electrode. The invention also provides a preparation method of the reversed polarity LED chip with the mask layer. The invention can solve the problem of N electrode falling caused by sidetrack in the wet etching process of the ohmic contact layer in the roughening process, and effectively improves the preparation yield of the LED chip.
Description
Technical Field
The invention relates to a semiconductor light-emitting device and a preparation method thereof, in particular to a reversed polarity LED chip with a mask layer and a preparation method thereof.
Background
Light Emitting Diodes (LEDs) have been developed to date and have been widely used in various lighting fields. AlGaInP material lattice matched with gallium arsenide substrate can cover visible light wavelength from 560nm to 650nm, and is excellent material for preparing dark red, orange and yellow-green LEDs. AlGaInP light-emitting diodes are important in the fields of solid-state lighting, display, city brightening, plant growth and the like, and are widely used in products such as full-color screen displays, automobile signal lamps, traffic signal lamps, stage projection lamps, plant growth illumination lamps, high-color-rendering-index white light illumination lamps and the like.
In recent years, great progress has been made in the epitaxial material growth technology of AlGaInP light-emitting diodes, and the internal quantum efficiency can reach more than 90%. But directly growing AlGaInP light-emitting diode epitaxial material on gallium arsenide substrate, then directly preparing N electrode on back of gallium arsenide substrate, and preparing P electrode on upper surface to obtain LED chip with substrate absorption and total reflection loss, so that the chip has low electro-optic conversion efficiency, generally less than 10%.
In order to reduce the absorption of the substrate and inhibit the total reflection so as to improve the electro-optical conversion efficiency, a very effective method is to prepare a reversed polarity LED chip. The method comprises the steps of firstly growing AlGaInP light-emitting diode epitaxial materials on a gallium arsenide substrate, transferring an epitaxial film to a substrate such as silicon, germanium and sapphire, removing the epitaxial growth substrate, manufacturing an N electrode, and roughening the surface to reduce total reflection loss of a light output surface, wherein the reverse polarity AlGaInP LED chip can improve the electro-optic conversion efficiency of an LED by 3-6 times to 30-60%. In the process of N-face after transfer of the reversed-polarity LED chip, N electrode preparation is a key for realizing current injection, and N-type layer surface roughening is a key for improving the light extraction efficiency of the chip. The preparation process of the N electrode involves the removal of the sacrificial layer, and the coarsening process of the N-type layer involves the removal of the sacrificial layer and the ohmic contact layer. Typically, material removal is achieved by wet etching. The wet etching process of the sacrificial layer and the ohmic contact layer in the etching liquid is isotropic. Patterning is required for the sacrificial layer and the ohmic contact layer, and selective removal is required instead of complete removal. A photolithographic process is required to replicate the designed pattern onto the sacrificial layer and ohmic contact layer surfaces. For the current prior art, in the process of realizing the patterning of the sacrificial layer and the ohmic contact layer by adopting a photoetching process, the side drilling problem exists in the corroded material in the wet etching process due to insufficient adhesiveness between the photoresist and the corroded material. Thereby influencing the process effect and reducing the manufacturing yield. In order to solve the problem, the invention provides a reverse polarity LED chip with a mask layer and a preparation method thereof.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a reverse polarity LED chip with a mask layer, wherein the chip comprises a substrate layer, a bonding protection layer, a composite structure layer, an epitaxial layer, the mask layer, an N electrode and a passivation layer;
the substrate layer is sequentially provided with a contact layer, a reverse protective layer, a supporting substrate and a front protective layer from bottom to top;
the upper surface of the substrate layer is sequentially provided with a bonding layer, a bonding protection layer and a composite structure layer from bottom to top;
the epitaxial layer is arranged on the composite structure layer, and the epitaxial layer comprises a p-type layer, a light-emitting layer, an n-type layer, a coarsening layer and an ohmic contact layer from bottom to top in sequence;
and a mask layer, an N electrode and a passivation layer are arranged on the epitaxial layer, wherein the mask layer is arranged on the ohmic contact layer, corresponds to the N electrode pattern and surrounds the N electrode.
Wherein the thickness of the mask layer is 0.1 um-5 um;
the thickness of the bonding layer is 1 um-10 um;
the thickness of the bonding protection layer is 0.1 um-10 um;
the thickness of the composite structure layer is 0.05 um-2 um;
the thickness of the front protective layer of the substrate is 0.5-10 um;
the thickness of the protective layer on the back surface of the substrate is 0.5-10 um;
the thickness of the supporting substrate is 60-600 um;
the thickness of the contact layer is 0.1 um-10 um.
The mask layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and polyimide film dielectric materials.
The mask layer is prepared by one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sol-gel.
And the ohmic contact layer further comprises a sacrificial layer.
The invention also provides a preparation method of the reversed polarity LED chip with the mask layer, which comprises the following specific steps:
(1) Forming an epitaxial layer on a growth substrate, wherein the epitaxial layer sequentially comprises a buffer layer, a sacrificial layer, an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from bottom to top;
(2) Sequentially forming a composite structure layer and a bonding protection layer on the epitaxial layer;
(3) Providing a supporting substrate, sequentially forming a substrate front protection layer and a bonding layer on the front surface of the supporting substrate, and sequentially forming a substrate back protection layer and a contact layer on the back surface of the supporting substrate;
(4) Binding the epitaxial layer and the substrate layer together through an adhesive layer and an adhesive protection layer by adopting a wafer hot-press bonding method;
(5) Obtaining an epitaxial layer with a reversed polarity structure, and preparing a mask layer, an N electrode and a roughened layer;
(6) Cutting the edges to form cutting channels and passivating to prepare a reversed-polarity LED chip;
wherein, the step (5) specifically comprises the following steps:
removing the growth substrate, the buffer layer and the sacrificial layer to obtain an epitaxial layer with a reversed polarity structure, wherein the epitaxial layer is an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from top to bottom in sequence; preparing a mask layer on the surface of the ohmic contact layer; removing the mask layer corresponding to the N electrode region to prepare an N electrode; removing the mask layer corresponding to the roughened layer region to prepare a roughened layer;
the step (5) is as follows:
removing the growth substrate and the buffer layer to obtain an epitaxial layer with a reversed polarity structure, wherein the epitaxial layer is a sacrificial layer, an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from top to bottom in sequence; preparing a mask layer on the surface of the sacrificial layer; removing the mask layer and the sacrificial layer corresponding to the N electrode region to prepare an N electrode; and removing the mask layer and the sacrificial layer corresponding to the roughened layer region to prepare the roughened layer.
Wherein the thickness of the mask layer is 0.1 um-5 um;
the thickness of the bonding layer is 1 um-10 um;
the thickness of the bonding protection layer is 0.1 um-10 um;
the thickness of the composite structure layer is 0.05 um-2 um;
the thickness of the front protective layer of the substrate is 0.5 um-10 um;
the thickness of the protective layer on the back surface of the substrate is 0.5-10 um;
the thickness of the substrate is 60-600 um;
the thickness of the contact layer is 0.1 um-10 um.
The mask layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and polyimide film dielectric materials.
The mask layer is prepared by one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sol-gel.
Wherein the composite structural layer comprises a complementary structural layer, a metal contact layer and a reflecting layer.
In summary, the mask layer structure grows on the surface of the corroded material, the mask layer is utilized to realize that the corroded material is not sidetracked in the wet corrosion process, the selectivity of the corroded material in the wet corrosion process is improved, the patterning precision of the chip preparation process is increased, the purposes of increasing a process window and improving the chip manufacturing yield are realized, the problem that an N electrode falls off due to sidetracked in the ohmic contact layer wet corrosion process in the roughening process can be solved, and the preparation yield of the LED chip is effectively improved.
Drawings
FIG. 1 is a schematic cross-sectional view of an epitaxial layer and growth substrate structure of the present invention;
FIG. 2 is a schematic cross-sectional view of the epitaxial layer of the present invention after preparation of a composite structural layer and a bond protection layer;
FIG. 3 is a schematic cross-sectional view of a support substrate of the present invention after an adhesive layer is formed thereon;
FIG. 4 is a schematic cross-sectional view of the epitaxial layer and substrate layer of the present invention after bonding;
FIG. 5 is a schematic cross-sectional view of FIG. 4 with the growth substrate and buffer layer removed;
FIG. 6 is a schematic cross-sectional view of the sacrificial layer of FIG. 5 after a mask layer has been grown thereon;
FIG. 7 is a schematic cross-sectional view of the N electrode of FIG. 6 after fabrication;
FIG. 8 is a schematic cross-sectional view of the epitaxial layer of FIG. 7 after roughening the surface thereof;
FIG. 9 is an enlarged view of a portion of the N electrode of FIG. 8
FIG. 10 is a schematic cross-sectional view of the LED chip with reversed polarity in embodiment 1 after trimming and passivation;
FIG. 11 is a schematic cross-sectional view of the LED chip with reversed polarity in embodiment 2 after trimming and passivation;
FIG. 12 is a schematic cross-sectional view of FIG. 4 with the growth substrate, buffer layer and sacrificial layer removed;
fig. 13 is a schematic cross-sectional view of fig. 12 after a mask layer is grown over the ohmic contact layer;
FIG. 14 is a schematic cross-sectional view of the N electrode of FIG. 13 after fabrication;
FIG. 15 is a schematic cross-sectional view of the epitaxial layer of FIG. 14 after roughening the surface thereof;
FIG. 16 is a schematic cross-sectional view of the LED chip with reversed polarity in embodiment 3 after trimming and passivation;
fig. 17 is a flowchart of a preparation of a reverse polarity LED chip with a mask layer according to the present invention.
Wherein, in example 1, 101: a growth substrate; 102: a buffer layer; 103: a sacrificial layer; 104: an ohmic contact layer; 105: an n-type layer; 106: a light emitting layer; 107: a p-type layer; 201: a support substrate; 202: a protective layer on the front surface of the substrate; 203: a bonding layer; 204: a protective layer on the back surface of the substrate; 205: a contact layer; 301: a composite structural layer; 302: bonding the protective layer; 401: a bonding layer; 501: a mask layer; 601: an N electrode; 701: coarsening the layer; 801: and a passivation layer.
In example 2, 802: a passivation layer; (otherwise, the same as in example 1).
In example 3, 901: a mask layer; 111: an N electrode; 121: coarsening the layer; (otherwise, the same as in example 1).
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. It should be noted that the drawings of the present invention are all to a very simplified, non-precise scale, and are only used for convenience and clarity in assisting in explaining the present invention.
The invention will now be described in detail with reference to the drawings and examples.
Example 1
Fig. 1 is a schematic cross-sectional view of an epitaxial layer and growth substrate structure of the present invention. As shown in fig. 1, the growth substrate 101 may be any one of a gallium arsenide substrate, a gallium phosphide substrate, a silicon substrate, a sapphire substrate, and a thin film growth substrate in the existing aluminum gallium indium phosphorus based LED technical field. The growth substrate 101 of the present embodiment is a gallium arsenide substrate. The AlGaInP-based epitaxial layer is obtained by a metal organic chemical vapor deposition method, and comprises, in order from the growth substrate 101: buffer layer 102, sacrificial layer 103, ohmic contact layer 104, n-type layer 105, light emitting layer 106, p-type layer 107. In one embodiment of the present invention, the sacrificial layer 103 is removed during the chip manufacturing process, and thus the sacrificial layer 103 is not present between the buffer layer 102 and the ohmic contact layer 104.
Fig. 2 is a schematic cross-sectional view of the epitaxial layer of the present invention after a composite structural layer 301 is prepared on the surface of the epitaxial layer and then a bond protection layer 302 is deposited.
The composite structural layer 301 includes a complementary structural layer, a metal contact layer, and a reflective layer. The preparation method of the complementary structure layer is to grow insulating dielectric materials such as silicon oxide or silicon nitride; or, plasma etching is adopted to destroy the surface of the epitaxial layer material, so that the ohmic contact resistance between the surface of the p-type layer 107 and the metal contact layer is increased; or the p-type layer 107 of the epitaxial layer material is etched away using an etching process, degrading the current spreading capability of the epitaxial layer. The metal contact layer is a metal single layer or a laminated layer which can form lower ohmic contact resistance with the epitaxial layer, and the material of the metal contact layer is one of Au, ag, niAg, niAu, auBe, ag/Ni/Ag, ni/Al and Ni/Ag/Ni/Ag. The reflecting layer is made of a single-layer material or a composite structure material with higher reflectivity, the reflecting layer is made of one of Au, ag, niAg, niAu, auBe, ag/Ni/Ag, ni/Al and Ni/Ag/Ni/Ag, and the reflecting layer can be made of the following materials: au, ag, niAg, niAu, auBe, ag/Ni/Ag, ni/Al, ni/Ag/Ni/Ag, and one of dielectric materials silicon oxide, silicon nitride, ITO. The material of the bonding protection layer 302 is a metal single layer with acid and alkali corrosion resistance, and is Cr, pt, ti, W, au; or the bonding protection layer 302 is in a laminated structure, and the material of the laminated structure is Cr/Pt/Au, cr/Pt/Ag, cr/Pt/Cr/Pt/Au/Ag, ti/Pt/Au, ti/W/Ti/Pt/Au. The other function of the bonding protection layer 302 is to bind with the substrate bonding layer 203, the last layer of material of the bonding protection layer 302 with a laminated structure is required to be not easy to oxidize, and has better wettability with the material of the bonding layer 203, and the material is Au, ag, cu, pt, au/Pt/Au. Preferably, the bond coat 302 in this embodiment is Cr/Pt/Cr/Pt../Au/Ag. Preferably, the thickness of the adhesion protection layer 302 is 0.5-10 um, the thickness of the Cr/Pt periodic stack is 0.3-1 um, and the thickness of the Au/Ag is 0.2-5 um.
Fig. 3 is a schematic cross-sectional view of a substrate layer. The substrate layer includes a support substrate 201, a substrate front side protective layer 202, an adhesive layer 203, a substrate back side protective layer 204, and a contact layer 205. By adopting an electron beam evaporation mode, firstly, a substrate front protection layer 202 is deposited on the front surface of a supporting substrate 201, then a substrate back protection layer 204 and a contact layer 205 are sequentially deposited on the back surface of the supporting substrate 201, and finally an adhesive layer 203 is deposited on the substrate front protection layer 202. The supporting substrate 201 is any one of a silicon substrate, a metal substrate, a ceramic substrate or other composite substrates, and the supporting substrate 201 in this embodiment is a silicon substrate, and the thickness of the supporting substrate 201 is between 60um and 600 um. Preferably, the thickness of the support substrate 201 is between 80um and 200 um. Preferably, the substrate front surface protective layer 202 and the substrate back surface protective layer 204 are made of a metal material having acid and alkali corrosion resistance. Preferably, a stacked structure of Cr, pt, au, W simple metal or alloy is adopted, and the materials are Cr/Pt/Cr/Au, cr/Pt/Au, pt/Au/Pt/Au and Cr/Pt/TiW. The thickness is 0.5 um-10 um. Preferably, the contact layer 205 is made of a single-layer metal, such as Pt, au, cu, or the like, or a single-layer metal, such as Pt/Au/Pt/Au, or the like, or two or more metal stacks, such as AuSn, agSn, or the like, having a thickness of 0.1um to 10um. Preferably, the material used for the adhesive layer 203 has a low melting point or a strong diffusion capability; preferably, the material of the adhesive layer 203 is a specific one of Sn, in, pb, bi, sb, zn low-melting metal or an alloy (such as AuIn, auSn, agIn, agSn) formed by the low-melting metal and Ag, cu, au, al, and the structure is a metal single-layer or multi-layer metal lamination, such as Sn, in, au/AuSn, ag/Sn, ag/In, au/Au. Preferably, the thickness of the adhesive layer 203 is 0.5um to 5um.
Fig. 4 is a schematic cross-sectional view of the epitaxial layer after bonding to the substrate layer. The bonding of the epitaxial layer and the substrate layer is by adopting a wafer hot-press bonding mode. Taking Sn as the material of the adhesive layer 203, the temperature of the 2-inch wafer thermal compression bonding is preferably 230-280 ℃ and the pressure is 100-1000 Kg. Bonding is to laminate the epitaxial layer and the substrate together, and apply temperature and pressure by a specific device, and under the action of the temperature and pressure, the metals between the bonding layer 203 and the last layer of the bonding protection layer 302 are mutually diffused and fused to form an alloy, so that the purpose of bonding the epitaxial layer and the substrate layer is achieved. The adhesive layer 203 and the adhesive protection layer 302 are bonded to each other at the rearmost layer to form a bonding layer 401. Fig. 5 is a schematic cross-sectional view of the removal of the original growth substrate and buffer layer. The growth substrate 101 in this embodiment is a gallium arsenide substrate, which is typically removed by NH 4 OH/H 2 O 2 Wet etching in solution. Removing the growth substrate 101 and the buffer layer 102 enables a thin film transfer process of transferring the epitaxial layer from the native growth substrate to the substrate layer.
Fig. 6 is a schematic cross-sectional view of a mask layer 501 grown on sacrificial layer 103. The mask layer 501 is made of one of film dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, polyimide and the like, and plays roles in protecting the material of the sacrificial layer 103 and the ohmic contact layer 104 under the N electrode preparation and the chip surface roughening wet etching process. The preparation method of the mask layer 501 is one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sol-gel. The thickness of the mask layer 501 is 0.1um to 5um.
Fig. 7 is a schematic cross-sectional view of the completion of N-electrode fabrication. The preparation process flow is as follows: the required N electrode 601 pattern corresponding structure is obtained on the surface of the mask layer 501 through a photoetching process, and the pattern structure is transferred to the mask layer 501 and the sacrificial layer 103 through corrosion of the mask layer 501 and the sacrificial layer 103. Wherein the mask layer 501 and the sacrificial layer 103 are prepared by adopting a wet etching method; preferably, the SiO2 mask layer is removed by using a Buffer Oxide (BOE) etchant, and for an AlGaInP-based epitaxial layer chip, the removal of the sacrificial layer 103 is obtained by performing wet etching in HCl/H2O solution. Then, N electrode 601 is prepared using electron beam evaporation. The material of the N electrode 601 can form a low ohmic contact resistance with the ohmic contact layer 104, and has stable physicochemical characteristics and good heat and electric conduction characteristics; preferably, the N electrode 601 is a stacked structure formed by a plurality of metals in Au, ge, ni, cr, ti, pt, al, such as: au/Ge/Ni/Au, cr/Pt/Au, al/Ti/Au, al/Ti/Ni/Au.
In the preparation process of the N electrode 601, the mask layer 501 plays a role of wet etching mask, so that the problem of poor line precision of the N electrode 601 caused by side drilling of photoresist and the sacrificial layer 103 can be solved.
Fig. 8 is a schematic cross-sectional view of the roughened layer. The preparation process flow is as follows: a structure corresponding to the required coarsening pattern is obtained on the surface of the mask layer 501 through a photoetching process, and the mask layer 501, the sacrificial layer 103 and the ohmic contact layer are used for forming a photoresist pattern104, transferring the pattern structure to the mask layer 501, the sacrificial layer 103 and the ohmic contact layer 104, and then roughening the exposed n-type layer 105 to obtain a roughened layer 701. Wherein the mask layer, the sacrificial layer 103 and the ohmic contact layer 104 are prepared by adopting a wet etching method; for example, siO 2 The mask layer is removed by using Buffer Oxide (BOE) corrosive liquid, and the sacrificial layer 103 is removed by using HCl/H 2 Wet etching in O solution to remove ohmic contact layer 104 3 PO 4 /H 2 O 2 /H 2 Wet etching in O solution. Roughening the surface of the n-type layer 105 by adopting a wet etching method or a dry etching method or a combination of the wet etching method and the dry etching method to obtain a roughened layer 701; preferably, alGaInP-based epitaxial layer chip, and the surface roughening of n-type layer 105 is performed by using a method comprising the steps of 2 8O 4 /CH 3 COOH/NH 4 F. Wet etching in HCl/water solution or dry etching with chlorine-based or fluorine-based plasma.
Fig. 9 is a schematic enlarged view of a portion of the N electrode, and it can be seen that during the etching process of the sacrificial layer 103, the sidetrack of the sacrificial layer 103 can be effectively avoided by the protection of the mask layer 501. Furthermore, the sidetrack of the ohmic contact layer 104 in the corrosion process can be effectively avoided, and the problem that the N electrode 601 falls off due to the sidetrack of the ohmic contact layer 104 can be solved.
Fig. 10 is a schematic cross-sectional view of an opposite polarity LED chip with a mask layer after the n-type layer 105 is subjected to a trimming and passivation process. The n-type layer 105 is removed to form cutting lines, and all the cutting lines are prepared by adopting a wet etching method or a dry etching method or a combination of the wet etching method and the dry etching method; removing edges to form cutting lines by HIO 3 /HCl/H 2 O solution, HBrO 3 /Br/H 2 Wet etching in O solution or dry etching in chlorine-based or fluorine-based plasma. Passivation layer 801 is typically an insulating dielectric material that serves to protect the semiconductor thin film material. For example, the passivation layer 801 is formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, sol-gel, or the like of materials such as silicon oxide, silicon oxynitride, silicon nitride, and polyimide.
In the preparation of the N electrode 601 and the roughening process of the N-type layer 105, the mask layer 501 plays a role of wet etching mask, so that the problem of poor line precision control of the N electrode 601 caused by photoresist or sidetrack of the sacrificial layer 103 in the preparation process of the N electrode 601 can be solved, more importantly, the problem of falling-off of the N electrode 601 caused by sidetrack in the wet etching process of the sacrificial layer 103 and the ohmic contact layer 104 in the roughening process can be solved, and the preparation yield of the LED chip is effectively improved.
Example 2
The passivation layer structure can be changed as shown in fig. 11, and is different from embodiment 1 in that the passivation layer 802 covers all mesa regions except the pad position of the N electrode 601.
Example 3
The difference from embodiment 1 or 2 is that a mask layer 901 is grown on the ohmic contact layer 104. As shown in fig. 12, after the growth substrate 101 and the buffer layer 102 are removed, the sacrificial layer 103 is removed by direct wet etching.
Fig. 13 is a schematic cross-sectional view of a mask layer 901 grown over an ohmic contact layer 104.
Fig. 14 is a schematic cross-sectional view of the N electrode 111 after the preparation, which is different from the first embodiment in that the preparation process comprises the following steps: and (3) obtaining a required N electrode 111 pattern corresponding structure on the surface of the mask layer 901 through a photoetching process, and transferring the pattern structure to the sacrificial layer 103 through etching the mask layer 901 and the sacrificial layer 103. Then, N electrode 111 is prepared using electron beam evaporation. In the preparation process of the N electrode, the mask layer 901 plays a role in wet etching mask, so that the problem of poor line precision of the N electrode caused by photoresist sidetracking can be solved.
Fig. 15 is a schematic cross-sectional view of the roughened layer after completion of the preparation. The preparation process flow is as follows: and (3) obtaining a structure corresponding to a required coarsened pattern on the surface of the mask layer 901 through a photoetching process, transferring the pattern structure to the mask layer 901 and the ohmic contact layer 104 through corrosion of the mask 901 and the ohmic contact layer 104, and coarsening the exposed n-type layer 105 to obtain a coarsened layer 121. In the roughened layer preparation process, the mask layer 901 plays a role in wet etching mask, so that the problem of falling of the N electrode 111 caused by sidetrack of the ohmic contact layer 104 can be effectively avoided.
Fig. 16 is a schematic cross-sectional view of an opposite polarity LED chip with a mask layer obtained after the n-type layer 105 is subjected to the trimming and passivation process, which is different from the first embodiment in that the sacrificial layer 103 is not included in the final LED chip structure.
As shown in fig. 17, the present invention further provides a method for manufacturing a reverse polarity LED chip with a mask layer in embodiment 1 and embodiment 2, which includes:
A. forming an epitaxial layer on the growth substrate 101, wherein the epitaxial layer comprises a buffer layer 102, a sacrificial layer 103, an ohmic contact layer 104, an n-type layer 105, a light emitting layer 106 and a p-type layer 107 from bottom to top in sequence;
B. sequentially forming a composite structure layer 301 and a bonding protection layer 302 on the epitaxial layer;
C. providing a supporting substrate 201, sequentially forming a substrate front protection layer 202 and an adhesive layer 203 on the front surface of the supporting substrate 201, and sequentially forming a substrate back protection layer 204 and a contact layer 205 on the back surface of the supporting substrate 201;
D. binding the epitaxial layer and the substrate layer together through the bonding layer 203 and the bonding protection layer 302 by adopting a wafer hot-press bonding method;
E. removing the growth substrate 101, the buffer layer 102 and the sacrificial layer 103 to obtain an epitaxial layer with a reversed polarity structure, wherein the epitaxial layer is sequentially provided with an ohmic contact layer 104, an n-type layer 105, a light-emitting layer 106 and a p-type layer 107 from top to bottom; or removing the growth substrate 101 and the buffer layer 102 to obtain an epitaxial layer with a reversed polarity structure, wherein the epitaxial layer is a sacrificial layer 103, an ohmic contact layer 104, an n-type layer 105, a light-emitting layer 106 and a p-type layer 107 from top to bottom in sequence;
F. preparing a mask layer 901 on the surface of the ohmic contact layer 104; or, preparing a mask layer 901 on the surface of the sacrificial layer 103;
G. removing the mask layer 901 corresponding to the N electrode 111 area to prepare an N electrode 111; or removing the mask layer 901 and the sacrificial layer 103 corresponding to the N electrode 111 area to prepare an N electrode 111;
H. removing the mask layer 901 corresponding to the roughened layer 121 region to prepare a roughened layer 121; or removing the mask layer 901 and the sacrificial layer 103 corresponding to the roughened layer 121 region to prepare the roughened layer 121;
I. and (5) cutting the edges to form cutting channels and passivating to prepare the reversed-polarity LED chip.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. The utility model provides a reverse polarity LED chip with mask layer which characterized in that: the chip comprises a substrate layer, a bonding layer, an adhesive protection layer, a composite structure layer, an epitaxial layer, a mask layer, an N electrode and a passivation layer;
the substrate layer sequentially comprises a contact layer, a substrate reverse side protective layer, a supporting substrate and a substrate front side protective layer from bottom to top;
the bonding layer, the bonding protection layer and the composite structure layer are sequentially arranged on the substrate layer from bottom to top;
the epitaxial layer is arranged on the composite structure layer, and the epitaxial layer comprises a p-type layer, a light-emitting layer, an n-type layer, a coarsening layer and an ohmic contact layer from bottom to top in sequence;
the mask layer, the N electrode and the passivation layer are arranged on the epitaxial layer, the mask layer is arranged on the ohmic contact layer and corresponds to the pattern of the N electrode, and the mask layer surrounds the periphery of the N electrode;
the preparation of the N electrode and the preparation of the roughened layer are formed by the following steps: preparing a mask layer on the surface of the ohmic contact layer; removing the mask layer corresponding to the region of the N electrode to prepare the N electrode; removing the mask layer corresponding to the region of the roughened layer to prepare the roughened layer; the mask layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and polyimide film dielectric materials.
2. The reverse polarity LED chip with masking layer of claim 1, wherein:
the thickness of the mask layer is 0.1 um-5 um;
the thickness of the bonding layer is 1 um-10 um;
the thickness of the bonding protection layer is 0.1 um-10 um;
the thickness of the composite structure layer is 0.05 um-2 um;
the thickness of the front protective layer of the substrate is 0.5-10 um;
the thickness of the protective layer on the back surface of the substrate is 0.5-10 um;
the thickness of the supporting substrate is 60-600 um;
the thickness of the contact layer is 0.1 um-10 um.
3. The reverse polarity LED chip with masking layer of claim 1, wherein: the mask layer is prepared by one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sol-gel.
4. The reverse polarity LED chip with masking layer of claim 1, wherein: the ohmic contact layer further includes a sacrificial layer thereon.
5. A reverse polarity LED chip with masking layer according to claim 3, wherein said composite structural layer comprises a complementary structural layer, a metal contact layer and a reflective layer.
6. The preparation method of the reversed polarity LED chip with the mask layer is characterized by comprising the following preparation steps of:
(1) Forming an epitaxial layer on a growth substrate, wherein the epitaxial layer sequentially comprises a buffer layer, a sacrificial layer, an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from bottom to top;
(2) Sequentially forming a composite structure layer and a bonding protection layer on the epitaxial layer;
(3) Providing a supporting substrate, sequentially forming a substrate front protection layer and a bonding layer on the front surface of the supporting substrate, and sequentially forming a substrate back protection layer and a contact layer on the back surface of the supporting substrate;
(4) Binding the epitaxial layer and the supporting substrate together through the bonding layer and the bonding protection layer by adopting a wafer hot-press bonding method;
(5) Obtaining an epitaxial layer with a reversed polarity structure, and preparing a mask layer, an N electrode and a roughened layer; the preparation of the N electrode and the preparation of the roughened layer are formed by the following steps: preparing a mask layer on the surface of the ohmic contact layer; removing the mask layer corresponding to the region of the N electrode to prepare the N electrode; removing a mask layer corresponding to the region of the roughened layer, wherein the remaining mask layer corresponds to the pattern of the N electrode and surrounds the periphery of the N electrode to prepare the roughened layer; the mask layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and polyimide film dielectric materials;
(6) And (5) cutting the edges to form cutting channels and passivating to prepare the reversed-polarity LED chip.
7. The method for manufacturing a reverse polarity LED chip with a mask layer according to claim 6, wherein the step (5) of obtaining the epitaxial layer with the reverse polarity structure comprises the following specific steps:
and removing the growth substrate, the buffer layer and the sacrificial layer to obtain an epitaxial layer with a reversed polarity structure, wherein the epitaxial layer is an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from top to bottom.
8. The preparation method of the reversed polarity LED chip with the mask layer is characterized by comprising the following preparation steps of:
(1) Forming an epitaxial layer on a growth substrate, wherein the epitaxial layer sequentially comprises a buffer layer, a sacrificial layer, an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from bottom to top;
(2) Sequentially forming a composite structure layer and a bonding protection layer on the epitaxial layer;
(3) Providing a supporting substrate, sequentially forming a substrate front protection layer and a bonding layer on the front surface of the supporting substrate, and sequentially forming a substrate back protection layer and a contact layer on the back surface of the supporting substrate;
(4) Binding the epitaxial layer and the supporting substrate together through the bonding layer and the bonding protection layer by adopting a wafer hot-press bonding method;
(5) Obtaining an epitaxial layer with a reversed polarity structure, and preparing a mask layer, an N electrode and a roughened layer; the preparation of the N electrode and the preparation of the roughened layer are formed by the following steps: preparing a mask layer on the surface of the sacrificial layer; removing the mask layer and the sacrificial layer corresponding to the region of the N electrode to prepare the N electrode; removing the mask layer and the sacrificial layer corresponding to the region of the roughened layer, wherein the residual mask layer and the sacrificial layer correspond to the patterns of the N electrode and surround the periphery of the N electrode to prepare the roughened layer; the mask layer is made of one of silicon oxide, silicon nitride, silicon oxynitride and polyimide film dielectric materials;
(6) And (5) cutting the edges to form cutting channels and passivating to prepare the reversed-polarity LED chip.
9. The method for manufacturing a reverse polarity LED chip with a mask layer according to claim 8, wherein the step (5) of obtaining the epitaxial layer with the reverse polarity structure comprises the following specific steps:
and removing the growth substrate and the buffer layer to obtain an epitaxial layer with a reversed polarity structure, wherein the epitaxial layer is a sacrificial layer, an ohmic contact layer, an n-type layer, a light-emitting layer and a p-type layer from top to bottom.
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| CN112885938B (en) * | 2019-11-29 | 2022-06-14 | 山东浪潮华光光电子股份有限公司 | Preparation method of silver-based bonded reversed-polarity GaAs-based AlGaInP red LED chip |
| CN111384216A (en) * | 2020-02-27 | 2020-07-07 | 扬州乾照光电有限公司 | LED chip and manufacturing method thereof |
| CN113497164B (en) * | 2020-03-20 | 2023-01-24 | 山东浪潮华光光电子股份有限公司 | Reversed-polarity GaAs-based AlGaInP red LED chip tube core structure and manufacturing method thereof |
| CN112490303A (en) * | 2020-10-28 | 2021-03-12 | 南昌大学 | AlGaInP thin film LED chip structure with n-surface light emitting in specific geometric figure |
| CN112786750B (en) * | 2021-02-22 | 2022-05-20 | 江苏大学 | Thin film type AlGaInP light-emitting diode structure and preparation method thereof |
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