CN1992359A - Light-emitting diode and method for manufacturing the same - Google Patents

Light-emitting diode and method for manufacturing the same Download PDF

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CN1992359A
CN1992359A CN 200610064047 CN200610064047A CN1992359A CN 1992359 A CN1992359 A CN 1992359A CN 200610064047 CN200610064047 CN 200610064047 CN 200610064047 A CN200610064047 A CN 200610064047A CN 1992359 A CN1992359 A CN 1992359A
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compound semiconductor
semiconductor layer
nitride based
substrate
based iii
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CN1992359B (en
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大前晓
盐见治典
风田川统之
网隆明
宫嵨孝夫
平松雄司
畑田出穗
冈野展贤
冨谷茂隆
簗嵨克典
日野智公
成井启修
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Sony Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract

A method for manufacturing a light-emitting diode (LED), which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate until making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.

Description

Light-emitting diode and manufacture method thereof
Technical field
The present invention relates to light-emitting diode and manufacture method thereof, integrated light-emitting diode and manufacture method thereof, the method that is used for growing nitride base III-V compound semiconductor, the substrate that is used for growing nitride base III-V compound semiconductor, light source battery unit (cell unit), LED backlight, light emitting diode illuminating apparatus, light emitting diode indicator, electronic instrument, electronic installation and manufacture method thereof.The present invention is fit to be applied to the various instruments or the device that for example adopt the light-emitting diode of nitride based III-V compound semiconductor and adopt this light-emitting diode.
Background technology
The GaN semiconductor epitaxial be grown under the situation on the so special-shaped substrate of Sapphire Substrate because therebetween lattice constant or thermal coefficient of expansion have very big difference, so can occur crystal defect, especially helical dislocation to high-density.
For fear of these problems, extensively adopted dislocation density to reduce technology so far based on the selectivity cross growth.In this technology, be grown on Sapphire Substrate etc. the GaN semiconductor epitaxial, afterwards substrate removed from crystal growing apparatus.By SiO 2The growth mask that film etc. are made is formed on the GaN semiconductor layer, and substrate is turned back to crystal growing apparatus, utilizes growth mask epitaxial growth GaN semiconductor layer subsequently once more.
According to this technology, though can reduce the dislocation density that goes up in the GaN semiconductor layer, need twice epitaxial growth, make cost very high.
In order to address this problem, a kind of method has been proposed, the indentation (patterned indentation) of wherein special-shaped substrate experience patterning also makes the GaN semiconductor epitaxial growth is (for example on the indentation substrate, referring to Mitsubishi Cable Industries Review No.98, in October calendar year 2001, name is called " Development of High Output UV LED Using an LEPS Technique " and TOHKEMY communique No.2004-6931 and 2004-6937).The overview of this method at Figure 77 A to shown in the 77C.According to this method, shown in Figure 77 A, the indentation of patterning is formed in the first type surface of c face of Sapphire Substrate 101.Recess represents that with Reference numeral 101a jut is represented with Reference numeral 101b.These recess 101a and jut 101b respectively along Sapphire Substrate 101＜1-100 direction extends.Next, GaN semiconductor layer 102 is formed on Sapphire Substrate 101 tops by the step shown in Figure 77 B and the 77C.Among Figure 77 C, dotted line is represented the growth interface in the growth course.Shown in Figure 77 C, find on the feature that specifically recess 101a forms space 103 unsuitablely between Sapphire Substrate 101 and GaN semiconductor layer 102.Distribution by the crystal defect in this method Grown GaN semiconductor layer 102 is schematically shown in Figure 78.Shown in Figure 78, helical dislocation 104 is along appearing at the upper section of the jut 101b of GaN semiconductor layer 102 perpendicular to the interface direction with the upper surface of jut 101b, thereby forms high defect concentration district 105.On the other hand, the zone of recess 101a top or the part of part between high defect concentration district 105 become fabricating low-defect-density district 106.
Notice that though in Figure 77 C, the GaN semiconductor layer 102 that is formed on 103 belows, space in the recess 101a of Sapphire Substrate 2101 is buried with rectangular in form, the form of burying can be triangle in some cases.In the latter case, the GaN semiconductor layer 102 that is buried in the recess 101a contacts with GaN semiconductor layer 102 from jut 101b cross growth, might form such as the same space of rectangle.
For reference, Figure 79 A to 79D show the bearing of trend of recess 101a and jut 101b for Sapphire Substrate 101＜1-100 direction with right angle intersection＜11-20 how GaN semiconductor layer 102 grows under the situation of direction.
Figure 80 A has schematically shown another conventional growing method (reference, for example, TOHKEMY communique No.2003-31441) to 80F.Shown in Figure 80 A, in this method, adopt the Sapphire Substrate 101 of the indentation of experience patterning, and GaN semiconductor layer 102 by Figure 80 B to the growth of the step shown in the 80F thereon.According to this method, need not form the space relevant with Sapphire Substrate 101 just can growing GaN semiconductor layer 102.
Another growing method has been proposed, wherein jut is formed on to adopt and is different from the substrate of backing material, nitride based III-V compound semiconductor from jut (referring to, for example, TOHKEMY communique No.2003-324069 and Japan Patent No.2830814) between recess begin the growth.Yet in this way Sheng Chang mode and mode of the present invention have very big difference.
Only be used for reference, sapphire oikocryst face and crystal orientation have been shown among Figure 81 A and the 81B.
Summary of the invention
Adopt Figure 77 A to the conventional method shown in the 77C, the formation in the space between Sapphire Substrate 101 and the GaN semiconductor layer 102 is as indicated above.According to the result that we test, the GaN semiconductor layer is formed under the situation of the light emitting diode construction on the GaN semiconductor layer 102 being formed with wherein, and the problem of existence is that the luminous efficiency of light-emitting diode is low.This is that 103 inside are reflected and final absorbed reason repeatedly in the space because of the light of having considered to send from active layer in the course of work of light-emitting diode, thereby makes the light extraction efficiency variation.
On the other hand, adopt 80A to the conventional growing method shown in the 80F, though between Sapphire Substrate 101 and GaN semiconductor layer 102, do not form space 103, but think, be difficult to the dislocation density in the GaN semiconductor layer 102 is reduced to the level of Figure 77 A to the conventional growing method shown in the 77C.For this reason, under the situation that forms the light emitting diode construction on the GaN semiconductor layer 102 that GaN semiconductor growth layer wherein has this high dislocation density, the dislocation density of these GaN semiconductor layers uprises, thereby luminous efficiency is reduced.
In addition, Figure 77 A to 77C and 80A in any conventional growing method shown in the 80F, usually adopt dry etching the surface of Sapphire Substrate 101 to be carried out the indentation of patterning, but Sapphire Substrate 101 is not easy to carry out dry etching very much, therefore etching not only will take a long time, and machining accuracy is low.
Therefore, be desirable to provide the method for a kind of light-emitting diode and this diode of manufacturing, so wherein owing to there is not foregoing this space light extraction efficiency obviously to improve, thereby being improved greatly, the degree of crystallinity that constitutes the nitride based III-V compound semiconductor of light-emitting diode has very high luminous efficiency, carrying out epitaxial growth by single can make this diode with low cost, and process substrate is to provide projection and recessed pattern thereon easily.
It would also be desirable to provide integrated light-emitting diode and reach the method for making diode in the identical mode of first hope, growth is suitable for making the method for the nitride based III-V compound semiconductor of above mentioned this light-emitting diode and integrated light-emitting diode, and the substrate of this nitride based III-V compound semiconductor that is used to grow.
It would also be desirable to provide high performance light source battery unit, LED backlight, light emitting diode illuminating apparatus, light emitting diode indicator and electronic installation, each all adopts above mentioned this diode.
It would also be desirable to provide such as the such electronic installation of light-emitting diode, semiconductor laser, transistor or the like, and the method for making this device, wherein owing to do not have foregoing this space and the degree of crystallinity of the layer material that is made of this apparatus structure obviously improves, so characteristic performance is fine, carrying out epitaxial growth by single can make this electronic installation with low cost, and the indentation of the patterning of substrate is simple.
In order to realize these hopes, first embodiment of the invention provides a kind of method of making light-emitting diode.This method comprises provides step, cross growth step and order growth step.Provide step to be provided at the substrate that has a plurality of juts on the one first type surface, wherein jut is by making with the dissimilar material of substrate, and by under the state that forms the triangular-section on each recess of substrate growth regulation mononitride base III-V compound semiconductor layer, wherein the basal surface of recess is the leg-of-mutton end.The cross growth step on substrate from the first nitride based III-V compound semiconductor layer growth second nitride based III-V compound semiconductor layer.On the second nitride based III-V compound semiconductor layer, the grow tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type of order growth step.
The first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer can be any conductivity types, can be p type, n type or i type, and can or can be different conductivity types for identical conductivity type.In addition, can there be the different two or more parts of conductivity type in the first nitride based III-V compound semiconductor layer or the second nitride based III-V compound semiconductor layer.
Typically, when growth regulation mononitride base III-V compound semiconductor layer, from the vertical direction with a first type surface of upper edge, the interface substrate of the basal surface of the recess of substrate dislocation appears.At this moment, when this dislocation arrived near the inclined-plane of the first nitride based III-V compound semiconductor layer under the state in above-mentioned triangular-section or its, dislocation was along the direction bending that is parallel to this first type surface, thereby away from gable.The triangular-section of triangular portion office or triangle not only refer to proper triangle, and refer to roughly can regard leg-of-mutton shape as and for example comprise, have herein and those shapes of the rounded vertex that hereinafter occurs Anywhere.Advantageously, early growth period at the first nitride based III-V compound semiconductor layer, a plurality of meticulous nuclears or micronucleus appear on the basal surface of recess of substrate, and dislocation to be being parallel to the direction alternating bending of a first type surface, and this dislocation occurs from the vertical direction with a first type surface of upper edge, the interface substrate of the basal surface of the recess of substrate in the process of these micronucleus growths and combination.Like this, can reduce the number of dislocations of passing to upside in the first nitride based III-V compound semiconductor layer growth stage.
Typically, on the alternate first type surface that alternately is formed on substrate of jut and recess.In this case, the alternate intervals of jut and recess is 3 to 5 μ m.Ratio between the base portion length of jut and the base portion length of recess is preferably 0.5 to 3, preferably near 0.5.From this first type surface of substrate, the height of jut be preferably 0.3 μ m or more than, be preferably 1 μ m or more than.Jut should preferably have the side that this first type surface with respect to substrate tilts (for example, with this side that first type surface contacts of the substrate).When the angle that constitutes between this first type surface of this side and substrate is θ, from the angle that improves light extraction efficiency preferably this angle in the scope of 100 °＜θ＜160 °, more preferably 132 °＜θ＜139 ° or 147 °＜θ＜154 ° most preferably are 135 ° or 152 °.The cross sectional shape of jut can be got different shape, its side is not only smooth, also and crooked, for example, n limit shape (n be 3 or above integer), particularly, triangle, rectangle, pentagon, hexagon or the like, their summit are or are not to be cut off or to be rounded off and circular, oval or the like, from this first type surface of substrate, the extreme higher position to have being shaped as of a summit preferred, triangle or have be cut off or the triangle on the summit of cavetto more preferably.Recess can be various cross sectional shapes, for example comprise that n-limit shape (n be 3 or above integer) is such as triangle, rectangle, pentagon, hexagon or the like, the shape of perhaps just having mentioned, their angle are cut off or for being rounded off and circular, oval or the like.From improving the angle of light extraction efficiency, recess is preferably down the shape of trapezoid cross section.Term " trapezoidal " not only refers to proper trapezoidal, also refer to herein and hereinafter occur Anywhere roughly can regard down trapezoidal shape as.In this case, from making the minimized angle of dislocation density of the second nitride based III-V compound semiconductor layer, preferably, when the degree of depth (equaling the height of jut) of recess is d, the base widths of recess is W g, when the angle that forms between the inclined-plane of the first nitride based III-V compound semiconductor layer of triangular-section and the first type surface of substrate is α, d, W gBe confirmed as 2d 〉=W with α gTan α.α is generally constant, thereby determines d and W like this gSo that formula is set up.When d was too big, material gas was not easy to be transported in the recess, thereby hindered the growth of the first nitride based III-V compound semiconductor layer from the basal surface of recess.On the contrary, when d too hour, the first nitride based III-V compound semiconductor layer is not only grown on the recess of substrate, and grows on the jut of its opposite flank.For fear of this problem, d is typically chosen in the scope of 0.5≤d≤5 μ m, is preferably in the scope of 1.0 ± 0.2 μ m.W gGeneral in the scope of 0.5 to 5 μ m, preferably in the scope of 2 ± 0.5 μ m, select.When jut is the triangular-section, the width W of the upper surface of jut tBe zero.If jut is the trapezoid cross section, then this jut just serves as the zone as the second nitride based III-V compound semiconductor layer cross growth, and for this reason, width is long more, and the area of the part that dislocation density reduces is big approximately.When jut is the trapezoid cross section, W tBe generally 1 to 1000 μ m, be preferably in the scope of 4 ± 2 μ m.
Jut or recess can be bar shaped and extend on a direction of substrate, when these parts are the bar shaped extension on cross one another at least first and second directions, jut can be arranged in the two-dimensional pattern of n limit shape (n be 3 or above integer), particularly, triangle, rectangle, pentagon, hexagon or the like or this n above-mentioned limit shape, but their turning is cut off or is rounded off, and circular, oval, point or the like.As a preferred exemplary, jut has the hexagon planar shaped that is arranged in the bi-dimensional cellular form, and recess forms with around single jut, thus 360 degree that effectively obtain to be transmitted into all directions from active layer around light.Replacedly, recess can have the hexagon planar shaped that is arranged in the bi-dimensional cellular form, and jut forms to center on single recess.Form the situation of bar shaped at the recess of substrate, for example, they can along the first nitride based III-V compound semiconductor layer＜1-100 direction extends, if perhaps substrate adopt Sapphire Substrate can along Sapphire Substrate＜11-20 direction extends.Jut can be, for example, n limit shape cone (n be 3 or above integer) is such as pyrometric cone, rectangle awl, pentagonal pyramid, hexagonal awl or the like, perhaps above mentioned this n limit shape cone, but their turning is cut off or is rounded off and circle is bored, ellipse is bored or the like.
The material of jut can be all kinds, can be that conduct electricity or non-conductive.Mentioned, for example, such as the such dielectric material of oxide, nitride, carbide or the like, such as the such electric conductor of metal, alloy or the like (comprising transparent conductive body).The example of oxide comprises silica (SiO x), titanium oxide (TiO x), tantalum oxide (TaO x), hafnium oxide (HfO 2), zirconia (ZrO x), zinc oxide (ZnO x), aluminium oxide (AlO x), gallium oxide (GaO x), magnesium oxide (MgO x), barium monoxide (BaO x), indium oxide (InO x), MgIn 2O 4, mix the tin oxide (SnO of fluoride 2: F (FTO)), tin oxide (SnO x), lithia (LiO x), calcium oxide (CaO x), cupric oxide (CuO x), CuAlO 2, SrCu 2O 2, yttrium oxide (IrO x), ruthenium-oxide (RhO x), Cu a(Al xGa yIn z) 1-aO 2, CdGeO, InGaZnO, ZnRhO, GaIn 2O 4, LaO, LaCuO or the like.These oxides can two or more be used in combination or can use with the form of stacked film.Aforementioned nitride for example is, silicon nitride (SiNx), TiN, WN, CN, BN, LiN, TiON, SiON, CrN, CrNO or the like, and these nitride can two or more be used in combination or can use with the form of stacked film.Aforesaid carbide for example is SiC, HfC, ZrC, WC, TiC, CrC or the like, and these carbide can two or more be used in combination or can use with the form of stacked film.Aforesaid metal or alloy is made by for example B, Al, Ga, In, W, Ni, Co, Pd, Pt, Ag, Hf, Zr, Au, Cu, Ru, Ir, AgNi, AgPd, AuNi, AuPd, AlCu, AlSi, AlSiCu or the like.These metal or alloy can be used in combination or can use with the form of stacked film.Transparent conductive body can adopt ITO (indium tin composite oxides), IZO (indium zinc composite oxide), ZO (zinc oxide), FTO (mixing the tin oxide of fluoride), tin oxide or the like.These can two or morely be used in combination or can use with the form of stacked film.In addition, dissimilar material above-mentioned can two or more be used in combination, and perhaps can use with the form of stacked film.Jut can be formed by metal etc., at least nitrogenize, oxidation or carbonization is carried out to form nitride, oxide or carbide in its surface.
If desired, the refractive index of jut depends on its design.Usually, substrate and the nitride based III-V compound semiconductor layer that is grown on the substrate are selected like this, make refractive index differ from one another.Typically, the type selecting of semiconductor layer is to have the refractive index lower than the refractive index of substrate.
If desired, jut can constitute scattering center, thereby in order to will improve light extraction efficiency from the light scattering of active layer emission and guarantee the height output of the light-emitting diode of gained.Used this scattering center can for example be the silicon fine granular, such as si-nanocrystals.In order to form this jut that combines with the silicon fine granular, the jut of being made by silica is formed on the substrate and by heat treatment.
From allowing the first nitride based III-V compound semiconductor layer only to be grown in the angle of the recess of substrate, amorphous layer can be formed on the surface of jut at least.Amorphous layer serves as the growth mask.The principle of this utilization is that growth phase is not easy to take place karyomorphism and becomes on amorphous layer.This amorphous layer can form by utilizing one of various film formation methods to form film on substrate, perhaps forms by forming jut with metal and oxidation being carried out on the surface of jut.Amorphous layer can be, for example, and SiO xFilm, SiN xFilm, amorphous Si (a-Si) film, the stacked film of amorphous CrN film or two or more these films, and be generally dielectric film.Under some situation, jut can be by first amorphous film that is formed on the substrate, and second amorphous film and the 3rd amorphous film form.In this case, for example, second amorphous film can be the relative first and the 3rd amorphous film be selectively etched a kind of.
After the second nitride based III-V compound semiconductor layer cross growth, the top of the jut of the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer and/or top to the small part of recess can be removed, grow in proper order at left part cross growth the 3rd nitride based III-V compound semiconductor layer of the second nitride based III-V compound semiconductor layer and on the 3rd nitride based III-V compound semiconductor layer subsequently active layer and tetrazotization thing base III-V compound semiconductor layer.Replacedly, after the second nitride based III-V compound semiconductor layer cross growth, the top of the jut of the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer and/or top to the small part of recess can be removed, subsequently left part cross growth the 5th nitride based III-V compound semiconductor layer of the second nitride based III-V compound semiconductor layer and on the 5th nitride based III-V compound semiconductor layer order growth regulation three nitride based III-V compound semiconductor layers, active layer and tetrazotization thing base III-V compound semiconductor layer.
In addition, because helical dislocation concentrates on the relevant portion of the second nitride based III-V compound semiconductor layer of jut upper section, so the dislocation of being made by insulator or space is propagated and suppressed the unit and be pre-formed above the jut of the part of serving as relevant portion.Do like this, propagate to suppress the propagation that the unit has suppressed in the second nitride based III-V compound semiconductor layer dislocation propagated along the direction of a first type surface that is parallel to substrate by dislocation.At last, can prevent that dislocation from passing the surface of the second nitride based III-V compound semiconductor layer and being converted into helical dislocation.
The 3rd nitride based III-V compound semiconductor layer forms thereon, and first conductivity type electrode is electrically connected with it.Equally, tetrazotization thing base III-V compound semiconductor layer is formed with second conductivity type electrode that is electrically connected with it.
Substrate can be made by various types of materials.For the substrate made from the material that is different from nitride based III-V compound semiconductor layer, object lesson comprises these substrates, sapphire (comprising c face, a face, r face etc. and surface smoothing (face off)), SiC (comprising 6H, 4H and 3C), Si, ZnS, LiMgO, GaAs, spinelle (MgAl 2O 4, ScAlMgO 4), garnet, CrN (for example, CrN (111) or the like.Best, the hexagon substrate or the cube substrate of these materials are preferred, and wherein the hexagon substrate more preferably.For substrate, can adopt such as GaN AlGaInN, AlN, the substrate that so nitride based III-V compound semiconductor layer such as GaInN is made.Replacedly, nitride based III-V compound semiconductor layer growth is on the substrate of being made by the material that is different from nitride based III-V compound semiconductor layer, and jut can be formed on this nitride based III-V compound semiconductor layer.
Notice that if used substrate is the substrate under the such situation of layer growth at substrate of nitride based III-V compound semiconductor layer, the material of jut is to be made by the material of the material that is different from the layer that is positioned at the jut below so.
Need, can remove substrate.
First to the 5th nitride based III-V compound semiconductor layer and the most common by Al as the nitride based III-V compound semiconductor layer of active layer xB yGa 1-x-y-zIn zAs uN 1-u-vP vMake, wherein 0≤x+y+z＜1,0≤u+v＜1 is set in 0≤x≤1,0≤y≤1,0≤z≤1,0≤u≤1,0≤v≤1, especially, and by Al xB yGa 1-x-y-zIn zN makes, and wherein 0≤x+y+z＜1 is set, typically by Al in 0≤x≤1,0≤y≤1,0≤z≤1 xGa 1-x-zIn zN makes, wherein 0≤x≤1,0≤z≤1.Object lesson comprises GaN, InN, AlN, AlGaN, InGaN, AlGaInN or the like.Wherein B or Cr are included among the GaN, for example, show the promotion effect of dislocation bending.Understand from this respect, first to the 5th nitride based III-V compound semiconductor layer and as the nitride based III-V compound semiconductor layer of active layer can be respectively by BGaN or such as the GaN that mixes B of GaN:B, such as the GaN that mixes Cr of GaN:Cr, or the like constitute.Especially, the first nitride based III-V compound semiconductor layer of initial growth on the recess of substrate should be preferably by GaN, In xGa 1-xN (0＜x＜0.5), Al xGa 1-xN (0＜x＜0.5) or Al xIn yGa 1-x-yN (0＜x＜0.5,0＜y＜0.2).First conductivity type can be n type or p type, and correspondingly, second conductivity type can be p type or n type.For the so-called low temperature buffer layer of initial growth on substrate, adopt the GaN resilient coating usually, AlN resilient coating, AlGaN resilient coating or the like.In addition, also can adopt those resilient coatings or the CrN resilient coating of the Cr of mixing above-mentioned.
The thickness of the second nitride based III-V compound semiconductor layer select as required and be typically several microns or below, according to the purpose of final use can be greatly some and can, for example be about tens microns to 300 microns.
For first to the 5th nitride based III-V compound semiconductor layer with as the growth of the nitride based III-V compound semiconductor layer of active layer, mentioned, for example, by such as Metalorganic chemical vapor deposition (MOCVD), hydride gas phase epitaxial growth, halide vapor phase epitaxial growth (HVPE), the so various epitaxial growth methods of molecular beam epitaxy (MBE) or the like are made.
Second embodiment of the invention, provide a kind of light-emitting diode.This diode is included in the substrate that has a plurality of juts on the one first type surface, and wherein jut is by making with the dissimilar material of substrate.This diode also comprises and is grown on the substrate and does not form the 6th nitride based III-V compound semiconductor layer in space and the tetrazotization thing base III-V compound semiconductor layer that is formed on the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type on the 6th nitride based III-V compound semiconductor layer at each recess of substrate.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that adopts recess is made the leg-of-mutton inclined-plane at the end or near it and to be parallel to the direction bending of this first type surface.
At second execution mode of the present invention, and describe later the of the present invention the 4th, in the 6th and the 7th to the 11 execution mode, the 6th nitride based III-V compound semiconductor layer is the first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer that is equivalent to first embodiment of the invention.
In second execution mode of the present invention of Miao Shuing and the 3rd to the 13 execution mode, the description of doing at first execution mode also is applicable to these execution modes, unless otherwise noted hereinafter.
According to the 3rd execution mode of the present invention, provide a kind of method of making integrated light-emitting diode, wherein integrated a plurality of light-emitting diodes.This method comprises provides step, cross growth step and order growth step.Provide step to be provided at the substrate that has a plurality of juts on the one first type surface, wherein jut is by making with the dissimilar material of substrate, and by under the state that forms the triangular-section on each recess of substrate growth regulation mononitride base III-V compound semiconductor layer, wherein the basal surface of recess is the leg-of-mutton end.The cross growth step on substrate from the first nitride based III-V compound semiconductor layer growth second nitride based III-V compound semiconductor layer.On the second nitride based III-V compound semiconductor layer, the grow tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type of order growth step.
According to the 4th execution mode of the present invention, provide a kind of integrated light-emitting diode, wherein integrated a plurality of light-emitting diodes.These a plurality of light-emitting diodes be included in one of at least the substrate that has a plurality of juts on the one first type surface, wherein jut is by making with the dissimilar material of substrate.Also comprising one of at least of these a plurality of light-emitting diodes: be grown on the substrate and do not form the 6th nitride based III-V compound semiconductor layer in space at each recess of substrate; And the tetrazotization thing base III-V compound semiconductor layer that is formed on the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type on the 6th nitride based III-V compound semiconductor layer.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that adopts recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
In third and fourth execution mode of the present invention, though the application scenario of integrated light-emitting diode without limits, but typical purposes comprises the LED backlight that is used for LCD, light emitting diode illuminating apparatus, light emitting diode indicator, light emitting diode light communication device (for example, visible light communication device), light emitting diode (LED) light instrument or the like.This integrated light-emitting diode with respect to the shape of arrangement mode and light-emitting diode without limits.Light-emitting diode can be for example, in order to directly or by other strutting piece (support substrates) such as the interior or outer surface of the such plate of terminal block or radiator or dull and stereotyped various devices of interconnection or housing, be arranged in two-dimensional array on plate (board) or dull and stereotyped (plate), perhaps can be arranged in the bar shaped light-emitting diode of a line or many lines.The form of integrated light-emitting diode not only can be carried out batch process to the semiconductor layer wafer that piles up for utilizing so-called semiconductor processing techniques, thereby it is meticulous and repeatedly that single light-emitting diode is integrated to press circuit pattern, and can be for a plurality of light-emitting diodes that wherein each all have been cut into small pieces integrated subtly and be arranged on the circuit board of composition.These light-emitting diodes can be driven by independence or collective, and perhaps one group of light-emitting diode in any selection zone can be by collective's drive (driving in the zone).
According to the 5th execution mode of the present invention, provide a kind of method of growing nitride base III-V compound semiconductor layer.This method comprises provides step and cross growth step.Provide step to be provided at the substrate that has a plurality of juts on the one first type surface, wherein jut is by making with the dissimilar material of substrate, and by under the state that forms the triangular-section on each recess of substrate growth regulation mononitride base III-V compound semiconductor layer, wherein the basal surface of recess is the leg-of-mutton end.
The cross growth step on substrate from the first nitride based III-V compound semiconductor layer growth second nitride based III-V compound semiconductor layer.
This growing method of nitride based III-V compound semiconductor layer can be used to make various types of semiconductor device except making light-emitting diode or integrated light-emitting diode.
According to the 6th execution mode of the present invention, provide a kind of substrate of growing nitride base III-V compound semiconductor layer.This substrate comprises: have the substrate of a plurality of juts on an one first type surface, wherein each jut is by making with the dissimilar material of substrate; And be grown on this substrate and in each recess of substrate, do not form the 6th nitride based III-V compound semiconductor layer in space.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that utilizes recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
According to the 7th execution mode of the present invention, provide a kind of light source battery unit.This unit comprises, is positioned at a plurality of unit on the printed circuit board (PCB), each unit comprise each red light emitting diodes, green LED and blue LED one of at least.Above-mentioned at least one light-emitting diode of selecting from red light emitting diodes, green LED and blue LED comprises having the substrate of a plurality of juts on an one first type surface, and wherein jut is by making with the dissimilar material of substrate.At least one diode that should select from above-mentioned diode also comprises: be grown on the substrate and do not form the 6th nitride based III-V compound semiconductor layer in space in each recess of substrate; And the tetrazotization thing base III-V compound semiconductor layer that is formed on the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type on the 6th nitride based III-V compound semiconductor layer.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that adopts recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
According to the 8th execution mode of the present invention, a kind of LED backlight is provided, wherein having arranged every kind all has a plurality of red light emitting diodes, green LED and blue LED.Above-mentioned at least one light-emitting diode of selecting from red light emitting diodes, green LED and blue LED comprises having the substrate of a plurality of juts on an one first type surface, and wherein jut is by making with the dissimilar material of substrate.At least one diode that should select from above-mentioned diode also comprises: be grown on the substrate and do not form the 6th nitride based III-V compound semiconductor layer in space in each recess of substrate; And the tetrazotization thing base III-V compound semiconductor layer that is formed on the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type on the 6th nitride based III-V compound semiconductor layer.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that adopts recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
According to the 9th execution mode of the present invention, a kind of light emitting diode illuminating apparatus is provided, wherein having arranged every kind all has a plurality of red light emitting diodes, green LED and blue LED.Above-mentioned from red light emitting diodes, at least one light-emitting diode that green LED and blue LED are selected comprises having the substrate of a plurality of juts on an one first type surface, and wherein jut is by making with the dissimilar material of substrate.At least one diode that should select from above-mentioned diode also comprises: be grown on the substrate and do not form the 6th nitride based III-V compound semiconductor layer in space in each recess of substrate; And the 3rd nitride based III-V compound semiconductor layer that is formed on first conductivity type on the 6th nitride based III-V compound semiconductor layer, the tetrazotization thing base III-V compound semiconductor layer of the active layer and second conductivity type.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that adopts recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
The tenth execution mode of the present invention provides a kind of light emitting diode indicator, and wherein having arranged every kind all has a plurality of red light emitting diodes, green LED and blue LED.Above-mentioned at least one light-emitting diode of selecting from red light emitting diodes, green LED and blue LED comprises having the substrate of a plurality of juts on an one first type surface, and wherein jut is by making with the dissimilar material of substrate.At least one diode that should select from above-mentioned diode also comprises: be grown on the substrate and do not form the 6th nitride based III-V compound semiconductor layer in space in each recess of substrate; And the 3rd nitride based III-V compound semiconductor layer that is formed on first conductivity type on the 6th nitride based III-V compound semiconductor layer, the tetrazotization thing base III-V compound semiconductor layer of the active layer and second conductivity type.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that adopts recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
In the 7th to the tenth execution mode of the present invention, used red light emitting diodes can be for example, to utilize the semi-conductive diode of AlGaP.
According to the 11 execution mode of the present invention, provide a kind of electronic installation with one or more light-emitting diodes.At least one light-emitting diode is included in the substrate that has a plurality of juts on the one first type surface, and wherein jut is by making with the dissimilar material of substrate.Above-mentioned at least one diode also comprises: be grown on the substrate and do not form the 6th nitride based III-V compound semiconductor layer in space in each recess of substrate; And the tetrazotization thing base III-V compound semiconductor layer that is formed on the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type on the 6th nitride based III-V compound semiconductor layer.In the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that adopts recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
In the 11 execution mode of the present invention, electronic installation comprises LED backlight (LCD etc. backlight), light emitting diode illuminating apparatus, light emitting diode indicator etc., and utilize light-emitting diode do the projecting apparatus of light source or rear projection television, grating light valve (Grating light valve, GLV) etc.Usually, the type of major limitation electronic installation not, as long as comprise therein at least one light-emitting diode be used to show, the purpose of illumination, optical communication, optical transmission etc., and portable and laptop these devices are also contained in the type of electronic installation.Except described object lesson these comprises cell phone, mobile device, robot device, personal computer, car-mounted device, various types of household electrical appliance, light-emitting diode optical communication equipment, light-emitting diode light transmitting device, such as such portable security device of electron key or the like.Electronic installation can also comprise the combination of two or more light-emitting diodes of the light of launching the different wave length district that is selected from far infrared wavelength zone, Infrared wavelength district, red wavelength region, yellow wavelengths district, green wavelength region, blue wavelength district, purple wavelength zone, ultraviolet wavelength district.Especially, for light emitting diode illuminating apparatus, two or more light-emitting diodes of launching the visible light in different wave length district can be made up, these wavelength zones differ from one another and are selected from red wavelength region, yellow wavelengths district, green wavelength region, blue wavelength district, purple wavelength zone or the like, will mix so that natural daylight or white light to be provided from two or more light that these light-emitting diodes send.In addition, utilization is sent the diode of the light of at least one wavelength zone and is made light source, and these wavelength zones are selected from blue wavelength district, purple wavelength zone, ultraviolet range or the like, and the rayed of sending from these light-emitting diodes is on phosphor, be used to excite, the light of gained is mixed to obtain natural daylight or white light.In addition, the light-emitting diode that sends the visible light of the wavelength zone that differs from one another is assembled into, for example such as battery unit, tetrad (quartet) unit, in such module units such as cluster (cluster) unit, (strictly speaking, assembled unit defines with respect to the quantity of the light-emitting diode that is included in a unit in these unit, and be meant in a plurality of peer group (equalgroup) and form and be installed in terminal block, the wiring encapsulation, a module units under the situation on the wiring shell wall etc., each is organized all by a plurality of light-emitting diodes that send the light of identical or different wavelength).More particularly, light-emitting diode is assembled as, for example, by three light-emitting diodes (for example, a red light emitting diodes, a green LED and a blue LED) in the unit formed, perhaps (for example by four light-emitting diodes, a red light emitting diodes, two green LEDs and a blue LED) in the unit formed, a plurality of this unit above-mentioned is with two-dimensional array, and the form of straight line or many straight lines is installed on plate or the coverboard.
According to the 12 execution mode of the present invention, provide a kind of method of making electronic installation.This method comprises the following steps: to be provided at the substrate that has a plurality of juts on the one first type surface, wherein jut is by making with the dissimilar material of substrate, and by under the state that forms the triangular-section on each recess of substrate growth regulation one deck, the basal surface that utilizes recess is the leg-of-mutton end; And on substrate from the ground floor cross growth second layer.
According to the 13 execution mode of the present invention, provide a kind of electronic installation.This device comprises: have the substrate of a plurality of juts on an one first type surface, wherein each jut is by making with the dissimilar material of substrate; And be grown on this substrate and in each recess of substrate, do not form the 3rd layer of space.In the 3rd layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that utilizes recess and does near the leg-of-mutton inclined-plane at the end or its, and to be parallel to the direction bending of this first type surface.
In the of the present invention the 12 and the 13 execution mode, except nitride based III-V compound semiconductor, first to the 3rd layer can be by having the especially semiconductor of other type of hexagonal crystallographic texture of wurtzite structure, and have such as, for example ZnO, α-ZnS, α-CdS, α-CdSe etc., and various types of semiconductors of other crystal structure of CrS (111) are made.The semi-conductive semiconductor device that utilizes these types is except comprising such as common light-emitting diode, interior subband (intrasubband) transition (quanta cascade) light-emitting diode, outside the light-emitting device of the luminescent device that general semiconductor laser and interior sub-band transition (quanta cascade) semiconductor laser are such, also comprise such as photodiode, optical pickup apparatus that solar cell is such or transducer, with the electron transfer device, this electron transfer device is typically and comprises transistor, transistor comprises the field-effect transistor (FET) such as High Electron Mobility Transistor and ties the bipolar transistor of bipolar transistor (HBT) such as abnormal shape.These devices are formed on same substrate or the single or multiple chip.If desired, these devices can be arranged as drive.If light-emitting device and electron transfer device are integrated on the same substrate, can be arranged in optoelectronic integrated circuit (OEIC) so.If desired, can form the photoconduction line.Utilize light source, can realize throw light on communication or optical communication by at least one light-emitting device (for example, light-emitting diode or semiconductor laser) flash of light.In this case, utilize the light in a plurality of different wave lengths district can realize throw light on communication or optical communication.
Electronic installation is except (for example comprising this semiconductor device above-mentioned, light-emitting device, optical pickup apparatus, electron transfer device or the like) outside, also comprise piezo-electric device, thermoelectric device, Optical devices are (such as the second harmonic generator that adopts nonlinear optical crystal, or the like), dielectric devices (comprising ferroelectric devices), superconducting device or the like.In this connection, the material that is used for first to the 3rd layer is the above-mentioned various types of semiconductors that are used for semiconductor device, and such as having the piezo-electric device of being used for, thermoelectric device, Optical devices, dielectric devices, various types of materials that the oxide of the hexagonal crystallographic texture of superconducting device etc. is such.
When employing comprises that light-emitting diode or semiconductor laser are made those devices of electronic installation, can make such as the such electronic installation of LED backlight, light emitting diode illuminating apparatus, light emitting diode indicator or the like, and utilize light-emitting diode or semiconductor laser to make the projecting apparatus or the rear projection television of light source, grating light valve (GLV).
For the of the present invention the 12 and the 13 execution mode, can similar application be arranged to the first to the 11 execution mode.
In the embodiments of the present invention of above being mentioned, the first nitride based III-V compound semiconductor layer begins the lower surface growth from each spill of substrate, in this process, the first nitride based III-V compound semiconductor layer is grown under the state that forms the triangular-section, utilize this lower surface to do its end, thus the spill of burying and do not have the space.The cross growth from the first nitride based III-V compound semiconductor layer of such growth of the second nitride based III-V compound semiconductor layer.In this stage, the first nitride based III-V compound semiconductor layer comprises dislocation, and it is along producing from the interface with the lower surface of the spill of substrate perpendicular to the direction of a first type surface of substrate.This dislocation arrives near the inclined-plane of the first nitride based III-V compound semiconductor layer or its.When the second nitride based III-V compound semiconductor layer growth, the part bending that dislocation arrives along the direction of a first type surface that is parallel to substrate.When the second nitride based III-V compound semiconductor layer growth when the satisfactory thickness, the part that is parallel to the dislocation top that this first type surface of substrate forms becomes the very little zone of dislocation density.According to this method, first to the tetrazotization thing base III-V compound semiconductor layer can be grown by the epitaxial growth of one-period.In addition, the jut of being made by the material that is different from substrate type forming on substrate is simpler than the situation of the direct knurled surfaces that forms patterning through dry etch process of substrate, and processing accuracy is very high usually.
More generally, this as by ground floor, and the situation that the second nitride based III-V compound semiconductor layer is used as the second layer also is like this for the first nitride based III-V compound semiconductor layer.
According to the embodiment of the present invention, owing to do not have the space to form between each first nitride based III-V compound semiconductor layer and the second nitride based III-V compound semiconductor layer and the substrate, so light extraction efficiency can significantly improve.In addition, the degree of crystallinity of the second nitride based III-V compound semiconductor layer is so good, the degree of crystallinity that makes each form thereon the 3rd nitride based III-V compound semiconductor layer, active layer and tetrazotization thing base III-V compound semiconductor layer also can significantly improve, thereby obtains having the very light-emitting diode of high-luminous-efficiency.In addition, carry out epitaxial growth by single and can make light-emitting diode, thereby cause low manufacturing cost.The surperficial indentation of substrate is easy to have high processing accuracy.Utilization has this light-emitting diode of high-luminous-efficiency, can access various types of electronic installations, such as high performance light source battery unit, LED backlight, light emitting diode illuminating apparatus, light emitting diode indicator, light emitting diode light communication device, optical space transmitting device etc.
More generally, as mentioned above, when the first nitride based III-V compound semiconductor layer is used as ground floor, and the second nitride based III-V compound semiconductor layer can access similar result when being used as the second layer.
Description of drawings
Figure 1A shows the profile of the method for making light-emitting diode according to the embodiment of the present invention respectively to 1C;
Fig. 2 A shows the profile of the method for making light-emitting diode according to the embodiment of the present invention respectively to 2C;
Fig. 3 shows the profile of the method for making light-emitting diode according to the embodiment of the present invention;
Fig. 4 shows in the method for making light-emitting diode according to the embodiment of the present invention, is formed on the plane graph of example of the flat shape of the jut on the substrate;
Fig. 5 shows in the method for making light-emitting diode according to the embodiment of the present invention, is formed on the plane graph of example of the flat shape of the jut on the substrate;
Fig. 6 shows the plane graph of the light-emitting diode of making by the method for making light-emitting diode according to the embodiment of the present invention;
Fig. 7 is the profile of other structure example of the light-emitting diode made according to the embodiment of the present invention;
Fig. 8 is the profile of other structure example of the light-emitting diode made according to the embodiment of the present invention;
Fig. 9 is the profile of other structure example of the light-emitting diode made according to the embodiment of the present invention;
Figure 10 is the profile of other structure example of the light-emitting diode made according to the embodiment of the present invention;
Figure 11 is the profile of other structure example of the light-emitting diode made according to the embodiment of the present invention;
Figure 12 has schematically shown used substrate in the method for the light-emitting diode of making according to the embodiment of the present invention;
Figure 13 is schematically illustrated in the method for making light-emitting diode according to the embodiment of the present invention, and how nitride based III-V compound semiconductor layer grows on substrate;
Figure 14 shows in the method for making light-emitting diode according to the embodiment of the present invention, by the schematic diagram that the nitride based III-V compound semiconductor layer that is grown on the substrate is carried out the performance of the viewed dislocation of tem observation;
Figure 15 shows in the method for making light-emitting diode according to the embodiment of the present invention, is grown in the schematic diagram of the distribution example of the helical dislocation in the nitride based III-V compound semiconductor layer on the substrate;
Figure 16 shows in first embodiment of the invention and makes in the method for light-emitting diode, is grown in the schematic diagram of the distribution example of the helical dislocation in the nitride based III-V compound semiconductor layer on the substrate;
Figure 17 A shows respectively in the method for making light-emitting diode according to the embodiment of the present invention to 17F, and nitride based III-V compound semiconductor layer is the schematic diagram of how to grow on substrate;
Figure 18 A and 18B show respectively in the method for making light-emitting diode according to the embodiment of the present invention, are grown in the schematic diagram of the dislocation performance of the nitride based III-V compound semiconductor layer on the substrate;
Figure 19 A shows respectively in the method for making light-emitting diode according to the embodiment of the present invention to 19C, is grown in the photo of the growth initial condition of the nitride based III-V compound semiconductor layer on the substrate;
Figure 20 A shows respectively in the method for making light-emitting diode according to the embodiment of the present invention to 20C, does not have the schematic diagram of the growth conditions under the situation that micronucleus forms at the early growth period of the nitride based III-V compound semiconductor layer on the substrate;
Figure 21 A and 21B show respectively in the method for making light-emitting diode according to the embodiment of the present invention, do not have the schematic diagram of the growth conditions under the situation that micronucleus forms at the early growth period of the nitride based III-V compound semiconductor layer on the substrate;
Figure 22 shows the schematic diagram of the ray trace analog result of the light-emitting diode of making according to the embodiment of the present invention;
Figure 23 shows the schematic diagram of the surface smoothness of the active layer of the light-emitting diode of manufacturing according to the embodiment of the present invention;
Figure 24 shows the schematic diagram of the surface smoothness of the active layer of the light-emitting diode of manufacturing according to the embodiment of the present invention;
Figure 25 A and 25B show the profile of making the method for light-emitting diode according to another embodiment of the present invention respectively;
Figure 26 shows the plane graph of the light-emitting diode of making according to the method for other execution mode manufacturing light-emitting diode according to the present invention;
Figure 27 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 28 shows the plane graph of the light-emitting diode of making according to the method for other execution mode manufacturing light-emitting diode according to the present invention;
Figure 29 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 30 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 31 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 32 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 33 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 34 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 35 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 36 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 37 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 38 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 39 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 40 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 41 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 42 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 43 A shows respectively according to other execution mode of the present invention to 43C, is positioned at the plane graph of example of flat shape of jut of the active layer below of light-emitting diode;
Figure 44 A shows respectively according to other execution mode of the present invention to 44C, is positioned at the example of flat shape of jut of the active layer top of light-emitting diode;
Figure 45 is the profile that illustrates according to the light-emitting diode distortion of other execution mode of the present invention;
Figure 46 is the profile that illustrates according to another distortion of the light-emitting diode of other execution mode of the present invention;
Figure 47 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 48 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 49 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 50 A shows the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively to 50C;
Figure 51 shows the profile that other execution mode according to the present invention is made the method for light-emitting diode;
Figure 52 shows by the method that other execution mode according to the present invention is made light-emitting diode and is grown in the schematic diagram that nitride based III-V compound semiconductor layer in the substrate carries out the dislocation performance that tem observation obtains;
Figure 53 shows the schematic diagram according to the ray trace analog result of the light-emitting diode of other execution mode manufacturing according to the present invention;
Figure 54 shows the schematic diagram according to the ray trace analog result of the light-emitting diode of other execution mode manufacturing according to the present invention;
Figure 55 shows the schematic diagram according to the ray trace analog result of the light-emitting diode of other execution mode manufacturing according to the present invention;
Figure 56 A and 56B show the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively;
Figure 57 A and 57B show the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively;
Figure 58 A and 58B show the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively;
Figure 59 A shows the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively to 59C;
Figure 60 A and 60B show the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively;
Figure 61 A and 61B show the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively;
Figure 62 A shows the profile that other execution mode according to the present invention is made the method for light-emitting diode respectively to 62J;
Figure 63 A shows the profile that other execution mode according to the present invention is made the method for LED backlight respectively to 63C;
Figure 64 shows the perspective view that other execution mode according to the present invention is made the method for LED backlight;
Figure 65 shows the perspective view that other execution mode according to the present invention is made the method for LED backlight;
Figure 66 shows the perspective view that other execution mode according to the present invention is made the method for LED backlight;
Figure 67 shows the perspective view according to the integrated light-emitting diode of other execution mode manufacturing according to the present invention;
The integrated light-emitting diode that Figure 68 shows according to the 31 execution mode manufacturing of the present invention is the profile that how to be installed on the base;
Figure 69 A and 69B show respectively according to the plane graph of the light source battery unit of other execution mode of the present invention and the battery enlarged drawing of light source battery unit;
Figure 70 shows the plane graph according to the instantiation of the light source battery unit of other execution mode of the present invention;
Figure 71 shows the plane graph according to another example of the light source battery unit of other execution mode of the present invention;
Figure 72 shows the plane graph according to the another example of the light source battery unit of other execution mode of the present invention;
Figure 73 shows the profile of the other example of light-emitting diode;
Figure 74 shows the profile of the other example of light-emitting diode;
Figure 75 shows the profile of the another example of light-emitting diode;
Figure 76 shows the profile of an example again of light-emitting diode;
Figure 77 A shows the profile of the method for growing GaN semiconductor layer on conventional indentation substrate respectively to 77C;
Figure 78 shows the profile of the problem that growth Figure 77 A exists in the method for the conventional GaN semiconductor layer shown in the 77C;
Figure 79 A shows the profile of the method for growing GaN Semiconductor substrate on conventional indentation substrate respectively to 79D;
Figure 80 A shows the profile of the method for growing GaN Semiconductor substrate on another kind of indentation substrate respectively to 80F; And
Figure 81 A and 81B show the schematic diagram of sapphire oikocryst dignity and crystal orientation respectively.
Embodiment
With reference to the accompanying drawings embodiments of the present invention are described.What note is that in the whole accompanying drawing of describing embodiments of the present invention, similar Reference numeral is represented similar or corresponding parts, member or part.
In Figure 1A to 3, show manufacturing method for LED successively according to first embodiment of the invention.This light-emitting diode is made by the so nitride based III-V compound semiconductor of GaN.
In the first embodiment, shown in Figure 1A, provide the substrate 11 that has flat primary flat and make by the material that is different from nitride based III-V compound semiconductor.Jut 12 with isosceles triangle is formed on the substrate 11 with given plane pattern compartment of terrain.Therefore, the spill 13 with trapezoid cross section is formed between the adjacent jut 12.Substrate 11 can be, for example mentioned in front one, and comprise, and Sapphire Substrate for example, its first type surface is for example c surface.The form of planar shaped or jut 12 and recess 13 can be one that selects from a plurality of planar shaped listed earlier.For example, planar shaped can be such planar shaped, wherein jut 12 and recess 13 all extend so that bar paten as shown in Figure 4 to be provided along direction, or such planar shaped, and wherein each jut 12 all has the hexagon planar shaped and with the form two-dimensional arrangements of honeycomb.Typically, it is arranged like this, make dotted line among Fig. 4 direction (promptly, the direction that intersects with striped) become parallel with a axle of the described nitride based III-V compound semiconductor layer 15 in back, perhaps the direction of dotted line among Fig. 5 (that is the direction that, connects most neighboring projection portion 12) becomes parallel with the m axle of the described nitride based III-V compound semiconductor layer 15 in back.For example, be the situation of Sapphire Substrate at substrate 11, the bar shaped jut 12 among Fig. 4 and the bearing of trend of recess 13 Sapphire Substrate＜1-100 direction, and among Fig. 5 recess bearing of trend equally Sapphire Substrate＜1-100 direction.Bearing of trend can Sapphire Substrate＜11-20 direction.The material of jut can be above-mentioned those.With regard to the easiness of handling, so preferably comprise SiO for example 2, SiN, CrN, SiON, CrON or the like.
In order on substrate 11, to form jut 12, can adopt the technology of any known with isoceles triangle tee section.For example, by the CVD method, vacuum deposition method, sputtering method or the like will be as the film of the material of jut 12 (SiO for example 2Film) the whole surface of formation substrate 11.Then, will be formed on the film to the corrosion-resisting pattern of definite form by photoetching technique.Under (taper) the etched condition of splaying, the mask that film passes corrosion-resisting pattern is carried out etching subsequently, thereby form the jut 12 of isoceles triangle tee section by reactive iron etching (RIE) method or the like.
Next, by they being carried out heat clean to cleaning on the surface of substrate 11 and jut 12, by known method for example, under about 550 ℃ growth temperature, for example on substrate 11, generate, GaN resilient coating, AIN resilient coating, CrN resilient coating, mix the GaN resilient coating of Cr or mix the AIN resilient coating (not shown) of Cr.Then, by for example, the nitride based III-V compound semiconductor of mocvd method epitaxial growth layer.This nitride based III-V compound semiconductor layer is by for example, and GaN makes.In this stage, shown in Figure 1B, thereby beginning to grow from the basal surface of spill 13 forms a plurality of micronucleus of being made by nitride based III-V compound semiconductor 14.Shown in Fig. 1 C, nitride based III-V compound semiconductor layer 15 is by the growth and the combining step growth of micronucleus 14, thereby form the isoceles triangle tee section, this triangle is done the end and is made hypotenuse with the first type surface plane inclined with respect to substrate 11 with the basal surface of spill 13.In this case, has the height of nitride based III-V compound semiconductor layer 15 of isoceles triangle tee section greater than the height of jut.For example, the bearing of trend of nitride based III-V compound semiconductor layer 15 its＜1-100 direction, the plane on inclined plane is (1-101) face.Nitride based III-V compound semiconductor layer 15 can undope or be mixed with n type impurity or p type impurity.Will be described below the growth conditions of nitride based III-V compound semiconductor layer 15.The bearing of trend of nitride based III-V compound semiconductor layer 15 can its＜11-20 direction.
Then, when nitride based III-V compound semiconductor layer 15 is grown and is kept the in-plane on inclined plane, the opposite end of nitride based III-V compound semiconductor layer 15 grows in the bottom scope of side of jut 12, thereby provide state, specifically shown in Fig. 2 A with pentagonal section.
Next, continued growth and set growth conditions like this that cross growth is become is main, shown in Fig. 2 B, nitride based III-V compound semiconductor layer 15 cross growth as shown by arrows, and above jut 12, launching under the state of hexagonal cross-section.Among Fig. 2 B, dotted line is illustrated in the growth interface in this growth course, and occurs hereinafter at any time.
Further continuation along with cross growth, the increase of its thickness shown in Fig. 2 C when nitride based III-V compound semiconductor layer 15 is grown, the nitride based III-V compound semiconductor layer 1 of growing from adjacent spill 13 contacts with each other and combines at last.
Then, shown in Fig. 2 C, the flat surfaces of nitride based III-V compound semiconductor layer 15 further cross growth the becoming first type surface that is parallel to substrate 11 up to its surface.Sheng Chang nitride based III-V compound semiconductor layer 15 is very low in the dislocation density of recess 13 upper sections like this.
Attention can directly be transformed into the state shown in Fig. 2 B and not have the step shown in Fig. 2 A in some cases from the state shown in Fig. 1 C.
Next, as shown in Figure 3, for example, on nitride based III-V compound semiconductor layer 15, form the active layer 17 and the nitride based III-V compound semiconductor of the p type layer 18 of the nitride based III-V compound semiconductor of n type layer 16, the nitride based III-V compound semiconductor layer of employing successively by mocvd method.In this case, nitride based III-V compound semiconductor layer 15 is the n type.
Next, there is the substrate 11 of nitride based III-V compound semiconductor layer to remove growth on it from the MOCVD device.
Afterwards, on the nitride based III-V compound semiconductor of p type layer 18, form p lateral electrode 19.The material of P lateral electrode 19 should be preferably, and for example, has the ohmic metal of high reflectance.
Afterwards, in order to activate the p type impurity in the nitride based III-V compound semiconductor of the p type layer 18, under the temperature of 550 to 750 ℃ (for example 650 ℃) or 580 to 620 ℃ (for example 600 ℃), at for example N 2And O 2Mist (for example have 99% N 2With 1% O 2Composition) atmosphere under heat-treat.Work as O 2With N 2During mixing, activate easily.Replacedly, can F or Cl are raw-material to have a similar halide (NF of high electronegative nitrogen with O and N with being used for 3, NCl 3Or the like) and N 2Perhaps N 2And O 2The atmosphere of mist mix.Heat treatment time is for example five minutes to two hours, preferred 40 minutes to two hours, and more preferably about 10 to 60 minutes.The reason that heat treatment temperature is lower is in order to prevent that active layer 16 from degenerating in heat treated process.What note is still to heat-treat before p lateral electrode 19 forms after the epitaxial growth of the nitride based III-V compound semiconductor of p type layer 18.
Next, the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 form pattern with the form of expectation, for example, by RIE method, powder injection process (powder blasting method), sand-blast (sand blasting method) or the like, thereby form boss portion 20.
Next, in the part adjacent, on nitride based III-V compound semiconductor layer 15, form n lateral electrode 21 with boss portion 20.
If desired, can polish the substrate that has been formed with such light emitting diode construction on it or polish,, subsequently substrate 11 be rule to form bar (bar) to reduce its thickness from its rear side.Afterwards, bar is rule to form chip.
Like this, just made the light-emitting diode of appointment.
The example of the planar shaped of p lateral electrode 19 and n lateral electrode 21 is shown in Figure 6, and wherein jut has the bar shaped of extending along a direction.
The raw material that are used for nitride based III-V compound semiconductor layer growth comprise raw-material the triethyl-gallium ((C that is used for Ga 2H 5) 3Ga, TEG) or trimethyl gallium ((CH 3) 3Ga TMG), is used for raw-material the trimethyl aluminium ((CH of Al 3) 3Al TMA), is used for raw-material the triethylindium ((C of In 2H 5) 3In, TMI) or trimethyl gallium ((CH 3) 3In, TMI), and the raw-material ammoniacal liquor that is used for N.Used alloy comprises for example n type alloy, such as silane (SiH 4) or disilane (Si 2H 6), and p type alloy for example, such as two (methyl cyclopentadiene) magnesium ((CH 3C 5H 4) 2Mg), two (ethyl cyclopentadiene) magnesium ((C 2H 6C 5H 4) 2Mg) or two (cyclopentadiene) magnesium ((C 5H 4) 2Mg).As the used carrier gas of nitride based III-V compound semiconductor layer growth, for example use H 2Gas.
Ad hoc structure example to light-emitting diode is described now.Specifically, for example, nitride based III-V compound semiconductor layer 15 is a n type GaN layer, nitride based III-V compound semiconductor layer 16 is from descending successively by n type GaInN layer, n type GaN layer and n type GaInN layer constitute, successively by p type GaInN layer, p type AlInN layer and p type GaN layer and p type GaInN layer constitute the nitride based III-V compound semiconductor of p type layer 18 from down.Active layer 17 has, for example a plurality of quantum well (MQW) structure (for example, GaInN quantum well layer and GaN barrier layer are alternately laminated) of GaInN base.In component in the active layer 17 is selected according to the emission wavelength of light-emitting diode.For example, the content of In reaches 11% during for the emission wavelength of 405nm, reaches 18% during for 450nm, reaches 24% during for 520nm.The material of p lateral electrode 19 comprises that for example, Ag or Pd/Ag perhaps if desired, also have the barrier metal of being made by Ti, W, Cr, WN, CrN or the like except the material of mentioning for the first time.Used n lateral electrode 21 can be for example, to have a kind of of Ti/Pt/Au structure.
In the light-emitting diode that obtains so shown in Figure 3, between p lateral electrode 19 and n lateral electrode 21, apply forward voltage, make electric current pass through to realize the light emission, resulting light is extracted the outside by substrate 11.Suitably select the In component in the active layer 17 to make it to send the red purple light that arrives, especially, send blue light, send green light or send red light.In this case, recess 13 places at the interface of light between substrate 11 and nitride based III-V compound semiconductor layer 15 of directive substrate 11 are refracted and pass substrate 11 directive outsides in the light of active layer 17 generations.The light of directive p lateral electrode 19 is reflected and directive substrate 11 at p lateral electrode 19 places in the light that produces in the active layer 17, passes substrate 11 directive outsides.
Light-emitting diode structure is not limited to structure shown in Figure 3, can be, for example the structure of those shown in Fig. 7 to 11.For structure shown in Figure 7, the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 are made and reserve its central part by composition like this, thereby form boss portion 20.P lateral electrode 19 is formed on the nitride based III-V compound semiconductor of the p side layer 18 of boss portion 20, and n lateral electrode 21 is formed on the nitride based III-V compound semiconductor of the n type layer 15 of opposite side of boss portion 20.Under situation shown in Figure 8, the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 are formed with recess G respectively therein, for example, form at central part with the form of splitting groove (slit groove) or cylinder hole (for example, the basal surface of the post of circle, horn shape (anglewise), point-like (point-like) etc.) with little width.Bar shaped or point-like n lateral electrode 21 are formed on the nitride based III-V compound semiconductor of the n type layer 15 of bottom of recess G.Because n lateral electrode 21 is very low with the contact impedance of the nitride based III-V compound semiconductor of n type layer, so the little contact area of this of n lateral electrode 21 has been guaranteed the good Ohmic contact characteristic, relatively easily account for leading thereby allow electric current to run through the nitride based III-V compound semiconductor of n type layer 15 from contact point (or contact-making surface).P lateral electrode 19 forms around n type electrode 21.Replacedly, n lateral electrode 21 can form around p lateral electrode 19.Under situation shown in Figure 9, the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 are formed with therein respectively by little width and (for example split groove or cylinder hole, the basal surface of the post of circle, horn shape, point-like etc.) the recess G of Xing Chenging is (when recess G is the form of cylinder hole, the form that a plurality of such recess G two-dimensional arrangements become the point on honeycomb, grid or the blockage (promptly, the hole of representing as the point on the blockage is with at interval the form in hole toward each other).In this case, n lateral electrode 21 is formed on the nitride based III-V compound semiconductor of the n type layer 15 of each recess G bottom.For example, become the point on honeycomb, grid or the blockage if each recess G is the form of such cylinder hole as mentioned above and two-dimensional arrangements, p lateral electrode 19 just forms around n lateral electrode 21 so.Replacedly, the n lateral electrode forms around the p lateral electrode.Under situation shown in Figure 10, the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 are formed with little width respectively therein and (for example split groove or cylinder hole, the basal surface of the post of circle, horn shape, point-like etc.) the recess G of form is (when recess is the form of cylinder hole, a plurality of such recess G two-dimensional arrangements become honeycomb, the point on grid or the blockage).N lateral electrode 21 is formed on the nitride based III-V compound semiconductor of the n type layer 15 of each recess G bottom.For example, when each recess G is the form of cylinder hole and two-dimensional arrangements when becoming point on honeycomb, grid or the blockage, p lateral electrode 19 forms around n lateral electrode 21, and perhaps n lateral electrode 21 forms around p lateral electrode 19.Under situation shown in Figure 11, the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 are formed with little width respectively therein and (for example split groove or cylinder hole, the basal surface of the post of circle, horn shape, point-like etc.) the recess G of form is (when recess G is the form of cylinder hole, a plurality of recess G are arranged in honeycomb, the point on grid or the blockage).Each recess G is formed with by SiO on its sidewall 2The dielectric film I that makes.Under the condition of the dielectric film I of the scope of burying recess H by it and the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 electric insulation, n lateral electrode 21 is formed on the nitride based III-V compound semiconductor of the n type layer 15 of each recess bottom.For example, all be the form of above-mentioned cylinder hole and two-dimensional arrangements when becoming point on honeycomb, grid or the blockage at each recess G, p lateral electrode 19 forms around n lateral electrode 21 or n lateral electrode 21 forms around p lateral electrode 19.Under the situation shown in Fig. 7 to 11.Especially in Figure 11, the wiring of p lateral electrode 19 and n lateral electrode 21 is easy to utilize conventional two-layer wiring technology to realize.
Light-emitting diode structure described above is particularly suited for flip-chip (FC) light-emitting diode structure very much, and wherein the optical clear substrate results from the whole rear side of optical clear substrate as the emission of substrate 11 and light.The performance index of (luminous efficiency)/(entire chip area) have been mentioned as light-emitting diode.In order to improve this index of (luminous efficiency)/(entire chip area), expectation with the least possible degree wherein the quantity of the recess G that is removed of active layer 17 reduce, perhaps reduce with the base area of as far as possible little degree with recess G.Therefore, consider the migration of charge carrier (electronics) in the nitride based III-V compound semiconductor of the n type layer 15, the whole area of n lateral electrode 21 that is formed on recess G bottom with respect to the entire chip area preferably in tens percent of cylindricality n lateral electrode 21, more preferably in a few percent or following, most preferably be 1% or below, thereby guarantee to run through electric current leading of active layer 17.
In first execution mode, helical dislocation density minimizes the width W of the basal surface of recess 13 in the nitride based III-V compound semiconductor layer 15 in order to make g, the depth d of recess 13, i.e. the height of jut 12, and the angle α that sets up between the first type surface of the inclined plane of nitride based III-V compound semiconductor layer 15 under the state shown in Fig. 1 C and substrate 11 is definite like this, to satisfy following equation (referring to accompanying drawing 12)
2d≥W gtanα
For example, for W g=2.1 μ m and α=59 °, d 〉=1.75 μ m; For W g=2 μ m and α=59 °, d 〉=1.66 μ m; For W g=1.5 μ m and α=59 °, d 〉=1.245 μ m; For W g=1.2 μ m and α=59 °, d 〉=0.966 μ m.Under other situation, best d＜5 μ m.
For the growth of nitride based III-V compound semiconductor layer 15 in the step shown in Figure 1B, 1C and the 2A, the raw-material V/III ratio of preferably growing is set at high value, and growth temperature is set in reduced levels.More particularly, the situation of under the air pressure that is grown in 1atm of nitride based III-V compound semiconductor layer 15, carrying out, the V/III of preferred raw material is than in 13000 ± 2000 the scope for example, and growth temperature for example is set in 1100 ± 50 ℃ the scope.Compare for raw-material V/III, under the pressure condition that is grown in x atm of nitride based III-V compound semiconductor layer 15, carry out end situation, in view of the Bernoulli principle that concerns between definition flow rate and the air pressure, preferably with V/III than being set in square resulting value of taking advantage of pressure variation by ratio, specifically, be (13000 ± 2000) * x substantially 2For example, in the following situation of growth of 0.92atm (700Torr), raw-material V/III is than in the scope that preferably sets 11000 ± 1700 (for example 10530).X is preferably 0.01 to 2atm.For growth temperature, the situation of under the air pressure conditions that is not higher than 1atm, growing, preferred settings is at lower temperature, thereby suppresses the cross growth of nitride based III-V compound semiconductor layer 15 and allow to select easily the growth of nitride based III-V compound semiconductor layer 15 in the recess 13.For example, when under 0.92atm (700Torr), growing, preferably growth temperature is set in 1050 ± 50 ℃ scope interior (for example 1050 ℃).Like this, the growth of nitride based III-V compound semiconductor layer 15 is just concrete as Figure 1B, shown in 1C and the 2A.When growth, nitride based III-V compound semiconductor layer 15 does not just begin growth on jut 12.Growth rate is roughly 0.5 to 5 μ m/ hour, preferably approximately 3.0 μ m/ hours.When nitride based III-V compound semiconductor layer 15 when for example the GaN layer is made, the flow rate of raw gas for example is the 20SCCM of TMG, NH 320SLM.On the other hand, in the step shown in Fig. 2 B and the 2C growth (cross growth) of nitride based III-V compound semiconductor layer 15 lower raw material V/III than and higher growth temperature under carry out.Specifically, the situation of under the air pressure conditions of nitride based III-V compound semiconductor layer 15, carrying out at 1atm, raw-material V/III ratio for example is set in 5000 ± 2000 the scope, and growth temperature for example is set in 1200 ± 50 ℃ the scope.Compare for raw-material V/III, the situation of under the air pressure conditions of x atm, growing at nitride based III-V compound semiconductor layer 15, in view of the Bernoulli principle that concerns between definition flow rate and the air pressure, preferably with V/III than being set in square resulting value of taking advantage of pressure variation by ratio, specifically, essence is (5000 ± 2000) * x 2For example, in the situation that 0.92atm (700Torr) grows down, raw-material V/III is than preferably setting in 4200 ± 1700 scope (for example 4232).For growth temperature, when under the air pressure conditions that is not higher than 1atm, growing, preferably set temperature lower, thereby suppress the surface roughness of nitride based III-V compound semiconductor layer 15 and allow good cross growth.For example, in the situation that 0.92atm (700Torr) grows down, growth temperature preferably sets in 1150 ± 50 ℃ scope (for example 1110 ℃).When for example the GaN layer was made, the flow rate of raw gas for example was the 40SCCM of TMG, NH at nitride based III-V compound semiconductor layer 15 320SLM.Like this, nitride based III-V compound semiconductor layer 15 forms by the cross growth shown in Fig. 2 B and 2C.
It is how to flow on substrate and diffusion that Figure 13 has schematically shown raw gas on the growth phase of GaN layer, and this GaN layer is as the example of nitride based III-V compound semiconductor layer 15.Most important point is initial stage of growth in this growth course, and GaN does not grow at jut 12 places of substrate 11 and GaN begins growth at recess 13 places.What note is, though the form shown in the jut 12 is the triangular-section in Figure 13, even the cross section is also not have GaN to grow in the trapezoidal protrusion portion 12.In general, when considering raw material and the NH of TMG as Ga 3During as the raw-material situation of N, pass through NH 3And the direct reaction growing GaN between the Ga, this reaction is represented by following reaction equation:
Ga (CH 3) 3(gas)+3/2H 2(gas) → Ga (gas)+3CH 4(gas)
NH 3(gas) → (1-α) NH 3(gas)+α/2N 2(gas)+3 α/2H 2(gas)
Ga (gas)+NH 3(gas)=GaN (solid)+3/2H 2(gas)
Though produced H 2Gas, but this H 2Gas is reaction in crystal growth, perhaps has etching action.In the step shown in Figure 1B/1C and the 2A, utilization is not used in the condition of the GaN growth on the conventional flat substrate, promptly utilizes the condition of strengthening etching action and the condition that is not easy to grow (by improving the V/III ratio), suppresses the growth on the jut 12.On the other hand, in the inside of recess 13, utilize the condition that suppresses etching action to produce crystallization.Traditionally, in order to improve the flatness of growth crystal surface, under the condition of cross growth degree increase (utilizing higher temperature), grow.In first execution mode, for make helical dislocation towards the direction bending of the first type surface that is parallel to substrate to reduce the purpose of its quantity, implement growth down in the temperature (for example 1050 ± 50 ℃) that is lower than under the conventional situation, and the stage is in early days buried recess 13 with nitride based III-V compound semiconductor layer 15.
Figure 14 has schematically shown the result of study that distributes for by the crystal defect in the definite nitride based III-V compound semiconductor layer 15 of transmission electron microscope (TEM).Among Figure 14, Reference numeral 22 expression helical dislocations.As seeing from Figure 14, though near jut 12 centers, promptly from the joint portion between the nitride based III-V compound semiconductor layer 15 of adjacent recess 13 growths, dislocation density uprises, but at the dislocation density step-down of the other parts that comprise recess 13 upper sections.For example, when the degree of depth of recess be that the width of d=1 μ m and basal surface is W gDuring=2 μ m, the dislocation density at this low-dislocation-density place is 6 * 10 7/ cm 2, this is by reduce by one to two order of magnitude under the situation of the substrate 11 that does not utilize protrusion of surface.In addition, it will be appreciated that, on direction, dislocation do not occur perpendicular to the sidewall of recess 13.
Among Figure 14, the average thickness in the zone of the nitride based III-V compound semiconductor layer 15 that contacts with substrate 11 at recess 13 places of dislocation density height and degree of crystallinity difference is 1.5 times at the average thickness in the zone of the nitride based III-V compound semiconductor layer 15 that contacts with substrate at jut 12 places of dislocation density height and degree of crystallinity difference.This is that cross growth owing to the nitride based III-V compound semiconductor layer 15 on the jut 12 causes.
Figure 15 shows the distribution situation that has helical dislocation 22 under the situation of this flat shape as shown in Figure 4 at jut 12.Figure 16 shows the distribution situation that has helical dislocation 22 under the situation of this flat shape as shown in Figure 5 at jut 12.
Next, with reference to figure 17A to Figure 17 F to nitride based III-V compound semiconductor layer 15 be how from the early growth period growth and how dislocation is propagated is described.
When beginning to grow, at a plurality of micronucleus of making by nitride based III-V compound semiconductor layer 14 of basal surface generation of spill 13, shown in Figure 17 A.In these micronucleus 14, dislocation (being illustrated by the broken lines) is propagated with the contact-making surface of substrate 11 on the vertical direction and is passed from the side of micronucleus 14.When continued growth, nitride based III-V compound semiconductor layer 15 is growth always in the growth of micronucleus 14 and integrating step, shown in Figure 17 B and 17C.In the growth and cohesive process of micronucleus 14, dislocation occurs crooked on the direction of the first type surface that is parallel to substrate 11, and feasible quantity of passing the dislocation on top reduces.Along with further continued growth, shown in Figure 17 D, nitride based III-V compound semiconductor layer 15 forms the isoceles triangle tee section, and wherein the basal surface of recess 13 is done the leg-of-mutton end.In this stage, the quantity that passes the dislocation on top from nitride based III-V compound semiconductor layer 15 obviously reduces.Next, shown in Figure 17 E, 15 cross growth of nitride based III-V compound semiconductor layer.In this step, pass and have the dislocation of side of nitride based III-V compound semiconductor layer 15 that the lower surface of recess 13 wherein is provided as the isoceles triangle tee section at the end and so show, thereby some dislocation that is lower than the horizontal plane of jut 12 continues to extend to the side and the disappearance of the jut 12 of the first type surface that is parallel to substrate 11, and some dislocation that is higher than the horizontal plane of jut 12 is parallel to the side that the first type surface of substrate 11 extends and pass the nitride based III-V compound semiconductor layer 15 of cross growth.When the further cross growth of nitride based III-V compound semiconductor layer 15, from the nitride based III-V compound semiconductor layer 15 of the offside of jut 12 growth in the combination of the top of jut 12, at last, nitride based III-V compound semiconductor layer 15 becomes the plane surface of the first type surface that is parallel to substrate 11, shown in Figure 17 F.When jut 12 upper layers combine, the dislocation in the nitride based III-V compound semiconductor layer 15 is (perpendicular to the direction of the first type surface of substrate 11) bending upwards.
With reference to figure 18A and 18B, be described be formed into the characteristic that dislocation showed this process after 15 cross growth of nitride based III-V compound semiconductor layer from micronucleus 14 once more.Shown in Figure 18 A and 18B, in the process of micronucleus 14 formation, growth and combination with the interface of substrate 11 on the dislocation that occurs repeated flex and form bundle (dislocation (1)) in the horizontal direction.Wan Qu dislocation extends to the side and the disappearance (dislocation (2)) of jut 12 in the horizontal direction.With the interface of substrate 11 on the dislocation bending that occurs once and pass through to the surface (dislocation (3)) of nitride based III-V compound semiconductor layer 15.Disappear afterwards by the side that makes dislocation form bundle and to make crooked in the horizontal direction dislocation extend to jut 12, can access the nitride based III-V compound semiconductor layer 15 that helical dislocation quantity reduces under the situation that does not form micronucleus 14.
Figure 19 A shows the TEM photo of situation lower section that is formed on the basal surface of the jut 12 shown in Figure 17 A at micronucleus 14 to 19C.Figure 19 B and 19C are respectively the amplification cross section TEM photos of the part that centered on by ellipse among Figure 19 A.Can know the formation of seeing at early growth period micronucleus 14 from Figure 19 A to 19C.
Next, under the situation that is formed on early growth period at micronucleus 14 with the situation that does not have micronucleus 14 to form under the dislocation that in nitride based III-V compound semiconductor layer 15, takes place show how different being described.
Figure 20 A shows respectively at nitride based III-V compound semiconductor layer 15 early growth period to 20C and does not occur under the situation of micronucleus 14, with Figure 17 D to the corresponding state of 17F.Shown in Figure 20 A, do not occur at early growth period under the situation of micronucleus 14, when nitride based III-V compound semiconductor layer 15 like this growth make to have when making the isoceles triangle tee section at the leg-of-mutton end with the basal surface of recess 13, only exist from the upwardly extending dislocation in interface of the basal surface of recess 13, and this dislocation density is generally greater than the density under the situation of Figure 17 D.Shown in Figure 20 B, when continued growth, pass through to and have the following performance of dislocation of side of nitride based III-V compound semiconductor layer 15 that the basal surface that utilizes recess 13 is made the isoceles triangle tee section at the end.The dislocation that is lower than the horizontal plane of jut 12 continues to extend to the side and the disappearance of the jut 12 of the first type surface that is parallel to substrate 11, and the first type surface that the dislocation that is higher than the horizontal plane of jut 12 is parallel to substrate 11 extends and pass through to the side of the nitride based III-V compound semiconductor layer 15 of cross growth.Shown in Figure 20 C, when the cross growth of nitride based III-V compound semiconductor layer 15 further continues, the nitride based III-V compound semiconductor layer 15 of growing from the opposite side of jut 12 is together with each other above jut 12, and last nitride based III-V compound semiconductor layer 15 forms the plane surface of the first type surface that is parallel to substrate 11.When mutually combining above jut 12, the dislocation in the nitride based III-V compound semiconductor layer 15 is bent upwards, and forms helical dislocation 22.Though the density of helical dislocation 22 is low satisfactorily, be higher than density in this case on micronucleus 14 is formed on recess at early growth period the basal surface.This is because shown in Figure 21 A and 21B, under the situation that does not have micronucleus 14 to form, when the dislocation that produces from the interface with substrate 11 utilized the basal surface of recess to do the inclined plane of isosceles triangle at the end when arrival, bending in the horizontal direction once.More particularly, in this case, there is not to obtain the effect of dislocation formation bundle in formation, growth and the cohesive process of micronucleus 14.
Figure 22 shows a simulation (ray trace simulation) result, this result be about when the situation of the spill degree of depth that relatively changes substrate 11 during with the situation that do not form concavo-convex (irregularity) light extraction efficiency from the light-emitting diode to the outside how to improve.Carry out the extraction of light from the dorsal part of substrate 11.Among Figure 22, abscissa is represented the degree of depth (that is, the height of jut 12) of recess 13, and ordinate is illustrated in the raising degree of light extraction efficiency η under the situation that does not form jut 12 (light extraction magnification ratio).In this connection, jut 12 has the strip that extends along a direction, and the angle theta that forms between the first type surface of the side of jut 12 and substrate 11 is 135 °, the length W of recess 13 base portions gBe 2 μ m, and the length of jut 12 base portions is 3 μ m.Be set at, the refractive index of substrate 11 is 1.77, and the refractive index of nitride based III-V compound semiconductor layer 15 is 2.35.As can be seen from Figure 22, the light extraction magnification ratio for the degree of depth of recess 13 be 0.3 μ m or when above be 1.35 times or more than, for the degree of depth be 0.5 μ m during to 2.5 μ m be 1.5 times or more than, is 1.75 times for 0.7 μ m during to 2.15 μ m, for 1 μ m during to 1.75 μ m be 1.85 times or more than, be maximum (about 1.95 times) during for about 1.3mm.
Next, near the growing surface state the consideration active layer 17.Usually,, the pit etc. of growing will occur so, thereby make the flatness variation of growing surface, as shown in figure 23 if helical dislocation is arranged in the grown layer.The density of helical dislocation is high more, and the degree of variation is just severe more.If in the active layer 17 helical dislocation is arranged, fluctuation will appear in its thickness and composition in the plane so, cause occurring in the emission wavelength face inhomogeneous and such as the such flat crystal defective of antiphase boundary defective, thereby make luminous efficiency descend (that is, internal quantum descends).On the contrary, according to first execution mode, the helical dislocation density in the nitride based III-V compound semiconductor layer 15 is such as foregoing such obvious reduction.Therefore, be formed on the also step-down of helical dislocation density in the active layer 17 of layer on 15, it is very little to make that the luminous efficiency that causes because of helical dislocation descends, and therefore can access the luminous efficiency that is better than known homologue.
Helical dislocation in the nitride based III-V compound semiconductor layer 15 concentrates near the central part of jut of substrate 11 and according to the setting of jut 12 and arranges regularly, and therefore the helical dislocation in the active layer 17 arranges in its lower section regularly.Therefore, when comparing with the situation of helical dislocation random distribution, the area of the part that the plane surface of active layer 17 forms obviously increases, thereby makes luminous efficiency further to improve.
In addition, when the growing surface roughening, for example, under the high situation of the In of active layer content, the just new easily crystal defect that occurs with the form of flat crystal defective like this such as antiphase boundary defective and dislocation of occurring from the active layer 17, thus cause luminous efficiency to descend.On the contrary, first embodiment of the invention, the surface flatness of active layer 17 improves as previously mentioned greatly, thereby suppresses the appearance of this crystal defect, and luminous efficiency can not descend.
For the flatness of the growing surface that improves active layer 17 and reduce the quantity of flat crystal defective, utilize mix the GaN of Al, the barrier layer of formation active layers 17 such as the GaInN that mixes Al, AlGaN is effectively (referring to U.S. Patent No. 3543628).
As mentioned above,, do not form the space between substrate 11 and the nitride based III-V compound semiconductor layer 15, thereby can prevent the decline of the light extraction efficiency that causes because of the space according to first execution mode.Helical dislocation in the nitride based III-V compound semiconductor layer 15 concentrates near the central part of jut 12 of substrate 11, and the dislocation density of other parts is for example, low to about 6 * 10 7/ cm 2, and therefore under the situation of the substrate that utilizes conventional indentation, reduce greatly.Therefore, the degree of crystallinity of the nitride based III-V compound semiconductor layer that nitride based III-V compound semiconductor layer 15 and growth active layer 17 thereon is such improves greatly, and the quantity of non-launching centre significantly reduces.Like this, can access the very high nitride based III-V compound semiconductor light-emitting diode of its luminous efficiency.
In addition, make nitride based III-V compound semiconductor light-emitting diode and only need an epitaxial growth.Not only do not need the mask of growing, and by on substrate 11, forming the film as the material of jut 12, for example SiO 2Film, SiON film, SiN film, CrN film, CrON film or the like, and by etching method, powder injection process, sand-blast or the like film is handled, thereby on substrate 11, form jut 12.Therefore, not need carry out indentation handle in the processing such as the such substrate 1 of sapphire lining of difficulty.At last, can adopt the light-emitting diode of nitride based III-V compound semiconductor with low cost by simple operation manufacturing.
Next, second execution mode of the present invention is described.
In second execution mode, grow into that the basal surface that utilizes spill 13 is done the end and the degree of the isoceles triangle tee section that forms when enclosing at nitride based III-V compound semiconductor layer 15, the height of jut 12 is selected like this, makes the height of nitride based III-V compound semiconductor layer 15 be lower than the height of jut 12.For example, Figure 25 A and the 25B height that shows nitride based III-V compound semiconductor layer 15 equals the situation of the height of jut 12.This makes and to occur and to pass through to having all dislocations of side of nitride based III-V compound semiconductor layer 15 of making the isoceles triangle tee section at the end with the basal surface of spill 13 from the interface with substrate 11, continue to extend to the side with the jut 12 of the major surfaces in parallel of substrate 11, and last the disappearance.Therefore, the quantity of helical dislocation 22 that passes through to the surface of nitride based III-V compound semiconductor layer 15 significantly reduces, thereby makes that helical dislocation density is zero substantially.
Except foregoing description, second execution mode is similar to first execution mode.
According to second execution mode, because its helical dislocation density of can growing is zero nitride based III-V compound semiconductor layer 15 substantially, so can access dislocation-free substantially nitride based III-V compound semiconductor substrate.For example, when the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 are grown on this dislocation-free nitride based III-V compound semiconductor substrate, dislocation density in these layers can obviously reduce, the advantage of its existence is, can realize having the nitride based III-V compound semiconductor light-emitting diode of very good characteristic.Much less, also can access the advantage similar to first execution mode.
Next, the 3rd execution mode of the present invention is described.
In the 3rd execution mode, as shown in figure 26, be formed on that jut 12 on the substrate 11 forms the isoceles triangle tee section and be the form of comb from the plane.
Except foregoing description, the 3rd execution mode is similar to first execution mode.
According to the 3rd execution mode, can access the advantage similar to first execution mode.
The 4th execution mode of the present invention is described.
In the 4th execution mode, as shown in figure 27, the thickness of nitride based III-V compound semiconductor layer 15 is less than the height of jut 12.And the top of jut 12 is outstanding from the upper surface of nitride based III-V compound semiconductor layer 15.
Except foregoing description, the 4th execution mode is similar to first execution mode.
According to the 4th execution mode, can access the advantage similar to first execution mode.
Now the 5th execution mode of the present invention is described.In the 5th execution mode, as shown in figure 28, boss portion 20, thus p lateral electrode 19 and n lateral electrode 21 so arrange with the plane of a major surfaces in parallel of substrate 11 in half-twist.
Except foregoing description, the 5th execution mode is similar to first execution mode.
According to the 5th execution mode, can access the advantage similar to first execution mode.
Next, the 6th execution mode is described.
In the 6th execution mode, as shown in figure 29, jut 12 is made of the film like second portion 12b of 12a of first with triangular-section and the covering 12a of first.12a of these firsts and second portion 12b are formed by dissimilar materials.The material that is used to form 12a of first and second portion 12b comprises, for example, and those that the front is listed and selecting as required.Specifically, the material of the 12a of first is such as SiO 2Such dielectric material, the material of second portion 12b are metal or alloy.
Except foregoing description, the 6th execution mode is similar to first execution mode.
According to the 6th execution mode, not only can obtain the advantage similar, and can access following advantage to first execution mode.More particularly, because the second portion 12b of jut 12 is made by metal or alloy, so the light that sends from active layer 17 can reflex on the opposite flank of substrate 11 by second portion 12b, this is advantageous extracting light from the opposite flank of substrate 11 under the situation of outside.
Should be noted that in the situation that is being intended to extract light 12a of first and second portion 12b one of at least can be by forming such as such transparent conductive bodies such as ITO, IZO, ZO from the side of substrate 11.In addition, second portion 12b can have opening (window), being come out in the first 12a part of jut 12.
Next, the 7th execution mode of the present invention is described.
In the 7th execution mode, as described in Figure 30, jut 12 is made of the 12a of first of film like and the second portion 12b that covers the 12a of first and have an isoceles triangle tee section.12a of first and second portion 12b are formed by dissimilar materials respectively.The material that forms 12a of first and second portion 12b was mentioned respectively and suitably selection as required in front.Object lesson comprise be used for the 12a of first such as SiO 2Such dielectric material and the metal or the alloy that are used for second portion 12b.
Except foregoing description, the 7th execution mode is similar to first execution mode.
According to the 7th execution mode, can access the advantage similar with the 6th execution mode to first.
Next, the 8th execution mode of the present invention is described.
In the 8th execution mode, as shown in figure 31, used nitride based III-V compound semiconductor layer 15 is the p type, and order growth has the nitride based III-V compound semiconductor of p type layer 18, active layer 17 and the nitride based III-V compound semiconductor of n type layer 16 on it.Afterwards, form n lateral electrode 21 on the nitride based III-V compound semiconductor of n type layer 16, the nitride based III-V compound semiconductor of p type layer 18, active layer 17 and the nitride based III-V compound semiconductor of n type layer 16 experience are etched with and form boss portion 20.P lateral electrode 19 is formed on it on the nitride based III-V compound semiconductor of the p type layer 15 of the part of boss portion 20.
According to the 8th execution mode, can access the advantage similar to first execution mode.
Now the 9th execution mode of the present invention is described.In the 9th execution mode, as described in Figure 32, reflectance coating 23 is formed on the dorsal part of substrate 11.
Except foregoing description, the 9th execution mode is similar to first execution mode.
According to the 9th execution mode, not only can obtain the advantage similar, and can access following advantage to first execution mode.More particularly, because reflectance coating 23 is formed on the dorsal part of substrate 11,, under the situation of outside, be very favourable with light extraction therefore from opposite side with respect to substrate 11 so the light that sends from active layer 17 can reflect to the opposite flank of substrate 11.
The tenth execution mode of the present invention is described.
In the tenth execution mode, as shown in figure 33, the light-emitting diode shown in Figure 31 is formed with reflectance coating 23 at the dorsal part of substrate 11.
Except foregoing description, the tenth execution mode is similar to first execution mode.
According to the tenth execution mode, can access and the identical advantage of the first and the 9th execution mode.
Now the 11 execution mode of the present invention is described.
In the 11 execution mode, as shown in figure 34, do not form boss portion 20 for the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18.In addition, used substrate 11 is the substrate of conduction, and n lateral electrode 21 is formed on the dorsal part of substrate 11.
Except foregoing description, the 11 execution mode is similar to first execution mode.
According to the 11 execution mode, can access the advantage similar to first execution mode.The light that sends from active layer 17 distributes to p lateral electrode 19 and n lateral electrode 21.When suitable selection is used for the material type, jut 12 of substrate 11 and jut 12 and during as the arrangement of the high reflecting electrode of p lateral electrode 19 and n lateral electrode 21 or transparency electrode, can controls the extraction direction of light.
Next, the 12 execution mode of the present invention is described.
In the 12 execution mode, as shown in figure 35, used nitride based III-V compound semiconductor layer 15 is the p type, and order growth has the nitride based III-V compound semiconductor of p type layer 18, active layer 17 and the nitride based III-V compound semiconductor of n type layer 16 on it.Afterwards, on the nitride based III-V compound semiconductor of n type layer 16, form n lateral electrode 21.Do not form boss portion 20 with respect to the nitride based III-V compound semiconductor of p type layer 18, active layer 17 and the nitride based III-V compound semiconductor of n type layer 16.Used substrate 11 is the substrate of conduction, and p lateral electrode 19 is formed on the dorsal part of substrate 11.
Except foregoing description, the 12 execution mode is similar to first execution mode.
According to the 12 execution mode, can access the result similar to first execution mode.
Next, the 13 execution mode is described.
In the 13 execution mode, as shown in figure 36, do not form boss portion 20 with respect to the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18.Jut 12 is formed and is used as n lateral electrode 21 by electric conducting material (comprising such transparent conductive material such as ITO, IZO, ZO or the like).
Except foregoing description, the 13 execution mode is similar to first execution mode.
According to the 13 execution mode, can access the advantage similar to first execution mode.In addition, because jut 12 also is used as n lateral electrode 21, so do not need to form the technology of n lateral electrode 21, the advantage of existence is that manufacturing process becomes simply, the manufacturing cost reduction.Jut 12 serves as the n lateral electrode 21 of absolute version, thereby can prevent to occur in the course of work of light-emitting diode current crowding (currentcrowding) phenomenon, and therefore for high-power, high brightness and large-area light-emitting diode are effective.
Next, the 14 execution mode of the present invention is described.
In the 14 execution mode of the present invention, as shown in figure 37, used nitride based III-V compound semiconductor layer 15 is the p type, and order growth has the nitride based III-V compound semiconductor of p type layer 18, active layer 17 and the nitride based III-V compound semiconductor of n type layer 16 on it.Afterwards, on the nitride based III-V compound semiconductor of n type layer 16, form n lateral electrode 21.The nitride based III-V compound semiconductor of p type layer 18, active layer 17 and the nitride based III-V compound semiconductor of n type layer 16 do not form boss portion 20.Jut 12 is formed and is used as p lateral electrode 19 by electric conducting material (comprising such transparent conductive material such as ITO or the like).
Except foregoing description, the 14 execution mode is similar to first execution mode.
According to the 14 execution mode, can access the advantage similar to first execution mode.In addition, because jut 12 so do not need to form the technology of p lateral electrode 19, exists advantage to be also as p lateral electrode 19, manufacturing process becomes simply, and manufacturing cost reduces.Jut 12 serves as the p lateral electrode 19 of absolute version, thereby can prevent to occur in the course of work of light-emitting diode the current crowding phenomenon, and therefore for high-power, high brightness and large-area light-emitting diode are effective.
Next, the 15 execution mode of the present invention is described.
In this 15 execution mode, as shown in figure 38, as first execution mode, next the step that forms jut 12 and growing nitride base III-V compound semiconductor layer 15 repeatedly repeats this step from forming jut 12 at substrate 11.Jut 12 in each layer is formed on the same position in the plane of the first type surface that is parallel to substrate 11.As first execution mode, for example, order growing nitride base III-V compound semiconductor layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 on the nitride based III-V compound semiconductor layer 15 of topmost.
Except foregoing description, the 15 execution mode is similar to first execution mode.
According to the 15 execution mode, except with first execution mode obtains identical advantage, because the formation of jut 12 and the growth of nitride based III-V compound semiconductor layer 15 are repeated, so the more nitride based III-V compound semiconductor in top layer 15 shows the more crystalline degree.Its advantage is to significantly improve the degree of crystallinity that is grown in the nitride based III-V compound semiconductor of n type layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 on the upper strata 15 more.In this connection, concentrating on the helical dislocation that occurs in the nitride based III-V compound semiconductor layer 15 that is formed on the jut 12 can cover with top jut 12.This is particularly advantageous in and improves the more degree of crystallinity of the nitride based III-V compound semiconductor in top layer 15.A plurality of juts 12 are made of electric conducting material respectively, and the jut 2 in these a plurality of layers passes through the lead short circuit, thereby can more effectively prevent electric current present crowding phenomenon in the light-emitting diode course of work.For the nitride based III-V compound semiconductor layer 15 of any kind, i.e. p type or n type, this technology all is effective.Especially, the carrier concentration (hole concentration) and the mobility of nitride based III-V compound semiconductor layer 15 are little, make that the effect that suppresses the current crowding phenomenon is very high, thereby make luminous efficiency significantly improve.If the jut in the multilayer 12 is not electrically connected each other, the jut 12 in the so independent layer serves as separate conductors, makes to connect easily and various types of electronic installations are installed easily.
Next, the 16 execution mode of the present invention is described.
In the 16 execution mode, as shown in figure 39, as first execution mode, next the step that forms jut 12 and growing nitride base III-V compound semiconductor layer 15 repeatedly repeats this step from forming jut 12 at substrate 11.In this case, the jut in each layer is formed on the position that has been offset half period in the plane of the first type surface that is parallel to substrate 11 mutually.As first execution mode, for example, order growth on the nitride based III-V compound semiconductor layer 15 of topmost, nitride based III-V compound semiconductor layer 16, active layer 17 and the nitride based III-V compound semiconductor of p type layer 18.
Except foregoing description, the 16 execution mode is similar to first execution mode.
According to the 16 execution mode, can access the advantage similar with the 15 execution mode to first.
Now the 17 execution mode of the present invention is described.
In the 17 execution mode, as shown in figure 40, jut 12 is formed on the substrate 11, and as first execution mode, growing nitride base III-V compound semiconductor layer 15 further forms jut 12 subsequently.As first execution mode, for example, the nitride based III-V compound semiconductor of further growth n type layer 16, next, on the nitride based III-V compound semiconductor of n type layer 16, grow successively active layer 17 and the nitride based III-V compound semiconductor of p type layer 18.Afterwards, form jut 12 on the nitride based III-V compound semiconductor of p type layer 18, the nitride based III-V compound semiconductor of further growth p type layer 24 subsequently is as first execution mode.
Except foregoing description, the 17 execution mode is similar to first execution mode.
According to the 17 execution mode, can access the advantage similar with the 15 execution mode to first.
Next, the 18 execution mode of the present invention is described.
In the 18 execution mode, as shown in figure 41, jut 12 is formed on the substrate 11, and as first execution mode, growing nitride base III-V compound semiconductor layer 15 further forms jut 12 subsequently thereon.As first execution mode, for example, the nitride based III-V compound semiconductor of further growth n type layer 16, next, on the nitride based III-V compound semiconductor of n type layer 16, grow successively active layer 17 and the nitride based III-V compound semiconductor of p type layer 18.Afterwards, form jut 12 on the nitride based III-V compound semiconductor of p type layer 18, the nitride based III-V compound semiconductor of further growth p type layer 24 subsequently is as first execution mode.In this case, the jut in each layer 12 be respectively formed at the first type surface that is parallel to substrate 11 the plane bias internal position of half period.
Except foregoing description, the 18 execution mode is similar to first execution mode.
According to the 18 execution mode, can access the advantage similar with the 15 execution mode to first.
The 19 execution mode of the present invention is described.
In the 19 execution mode, as shown in figure 42, jut 12 is formed on the substrate 11, for example, as first execution mode, the nitride based III-V compound semiconductor of growing n-type layer 16 continues to grow active layer 17 and the nitride based III-V compound semiconductor of p type layer 18 subsequently thereon.Next, form jut 12 on the nitride based III-V compound semiconductor of p type layer 18, the nitride based III-V compound semiconductor of growing p-type layer 24 subsequently is as first execution mode.Jut 12 in each layer is respectively formed at the same position place in the plane of the first type surface that is parallel to substrate 11.
The example of the flat shape of the jut 12 of Figure 43 A below 43C shows active layer 17, the example of the flat shape of the jut of Figure 44 A above 44C shows active layer 17.The flat shape of jut 12 below the active layer 17 and the jut 12 above the active layer 17 can combination in any.
Except foregoing description, the 19 execution mode is similar to first execution mode.
According to the 19 execution mode, can access the advantage similar with the 15 execution mode to first.
What note is, among Figure 42, the lower projection portion 12 that active layer 17 is clipped in the middle and last side projecture part 12 are arbitrary can be by making such as the such electric conductor of metal, alloy, transparent conductive body or the like.Especially, adopt do such as metal, alloy, the such electric conductor of transparent conductive body active layer 17 on the situation of material of side projecture part 12, can form the reflecting electrode 25 that contacts with jut 12 and further form p lateral electrode 19 thereon, specifically as shown in figure 45.Replacedly, if such as metal, alloy, the such electric conductor of transparent conductive body be used as with respect to the material of the last side projecture part 12 of active layer 17 and be printing opacity or the reflection, can suitably control the thickness of nitride based III-V compound semiconductor layer 24 so, for example, be λ/4 (λ is an emission wavelength), then form the reflecting electrode 25 that contacts with jut 12 thereon, further for example form p lateral electrode 19 as shown in figure 46.Like this, can form the light that can produce at active layer to substrate 11 offside reflections from any direction, guarantee when light-emitting diode is worked from the structure of the good electrical circulation flow path of p lateral electrode 19 simultaneously.
Next, the 20 execution mode of the present invention is described.
In the 20 execution mode, after the step before the mode identical with the 11 execution mode shown in Figure 34 forms the p lateral electrode, remove substrate 11 to expose the dorsal part of nitride based III-V compound semiconductor layer 15.Afterwards, as shown in figure 47, n lateral electrode 21 is formed on the dorsal part of nitride based III-V compound semiconductor layer 15.
If each is all made p lateral electrode 19 and n lateral electrode 21 by high reflecting electrode or transparency electrode, the direction of so can selective light extracting.
Removing substrate 11 allows the thickness of light-emitting diode very little generally.In order to improve mechanical strength, can support substrates S can be attached and join to p lateral electrode 19 by metal electrode M as shown in figure 48.Support substrates S can be conduction or nonconducting, as long as support substrates S has such structure and can make electric current flow to light-emitting diode by metal electrode M.
Except foregoing description, the 20 execution mode is similar to first execution mode.
According to the 20 execution mode, can access the advantage similar to first execution mode.
Next, the 21 execution mode of the present invention is described.
In the 21 execution mode, after the step before the mode identical with the 12 execution mode shown in Figure 35 forms n lateral electrode 21, remove substrate 11 to expose the dorsal part of nitride based III-V compound semiconductor layer 15.As shown in figure 49, p lateral electrode 19 is formed on the dorsal part of nitride based III-V compound semiconductor layer 15.
Except foregoing description, the 21 execution mode is similar to first execution mode.
According to the 21 execution mode, can access the advantage similar to first execution mode.
The 22 execution mode of the present invention is described.
In the 22 execution mode, shown in Figure 50 A, the jut with trapezoid cross section is formed on the substrate 11 with the given interval shown in the plane graph.Therefore, the recess 13 with trapezoid cross section is formed between the jut 12.
Next, nitride based III-V compound semiconductor layer 15 is grown in the mode identical with first execution mode.More particularly, nitride based III-V compound semiconductor layer 15 is grown by the step of the formation on the basal surface of each recess, growth and micronucleus combination, shown in Figure 50 B, this nitride based III-V compound semiconductor layer 15 has the isoceles triangle tee section of doing the end with the basal surface of recess 13.In addition, shown in Figure 50 C, have nitride based III-V compound semiconductor layer 15 further growth of plane surface and low helical dislocation density by cross growth.
Next, carry out further step, to obtain the nitride based III-V compound semiconductor light-emitting diode of indentation, shown in Figure 51 in the mode identical with first execution mode.
Except foregoing description, the 22 execution mode is similar to first execution mode.
Figure 52 has schematically shown by TEM and has checked the result that the crystal defect in the nitride based III-V compound semiconductor layer 15 distributes.
According to the 22 execution mode, can access the advantage similar to first execution mode.
Figure 53 to 55 shows respectively and is being formed with jut and recess on the substrate 11 and is not forming under the situation of jut and recess, extracts the example of light to the analog result of the efficiency change of outside from light-emitting diode.Under all situations, all the dorsal part from substrate 11 carries out light extraction.
Among Figure 53, abscissa is represented the refractive index of jut 12, and ordinate is illustrated in the raising degree of light extraction efficiency η under the situation that does not form jut (light extraction magnification ratio).Among Figure 53, the data of usefulness ▲ expression are for jut 12 situation for as shown in Figure 4 one dimension striped (1D) form, use ● the data of expression are to intersect the situation of two-dimensional arrangements of (2D) mutually for one dimension strip jut 12.The angle theta that forms between the first type surface of the side of jut and substrate 11 is 135 °, the length W of the basal surface of recess gBe W g=2 μ m, the base portion length of jut 12 is 3 μ m.Be set at, the refractive index of substrate 11 is 1.77, and the refractive index of nitride based III-V compound semiconductor layer 15 is 2.35.As can be seen from Figure 53, light extraction efficiency becomes maximum and is big to satisfactory in 1.2 to 1.7 ranges of indices of refraction when the refractive index of the jut 12 of 1D and 2D is 1.4.2D is greater than 1D for the light extraction magnification ratio.
Notice that these results are applicable to that the cross section of jut 12 is as the leg-of-mutton situation in first execution mode.
Among Figure 54, abscissa is represented the angle theta that forms between the first type surface of the side of jut 12 and substrate 11, and ordinate is represented the light extraction magnification ratio.Among Figure 54, the data of usefulness ▲ expression are to be situations of one dimension striped (1D) form as shown in Figure 4 for jut 12, use ● the data of expression are to intersect the situation of two-dimensional arrangements of (2D) mutually for one dimension strip jut 12.The length W of the basal surface of recess 13 gBe W g=3 μ m, the base portion length of jut 12 is 2 μ m.Be set at, the refractive index of substrate 11 is 1.77, and the refractive index of jut is 1.4, and the refractive index of nitride based III-V compound semiconductor layer 15 is 2.35.As can be seen from Figure 54, when in the scope of the angle theta that forms between the first type surface of the side of jut 12 concerning 1D and 2D and substrate in 100 °＜θ＜160 °, the light extraction magnification ratio is 1.55 times high or higher, in the time of in ° scope of 132 °＜θ＜139 be 1.75 times high or higher, especially when θ=135 °, reach maximum.In addition, this factor is 1.75 times high or higher in the time of in ° scope of 147 °＜θ＜154, especially reaches maximum when θ=152 °.2D works energetically 1D for the light extraction magnification ratio.
These results are applicable to that the cross section of jut 12 is as the leg-of-mutton situation in first execution mode.
Among Figure 55, abscissa is represented the depth d of recess 13, and ordinate is illustrated in the raising degree of light extraction efficiency η under the situation that does not form jut 12 (light extraction magnification ratio).Jut 12 has one dimension shape of stripes as shown in Figure 4.The base portion length W of recess 13 gWith the base portion length ratio of jut 12 be 3: 2.If the refractive index of substrate 11 is 1.77, the refractive index of jut 12 is 1.4, and the refractive index of nitride based III-V compound semiconductor layer 15 is 2.35.As can be seen from Figure 55, the light extraction magnification ratio is along with the degree of depth of recess 13 increases and increases.
Now the 23 execution mode of the present invention is described.
In the 23 execution mode, shown in Figure 56 A, nitride based III-V compound semiconductor layer 15 growth become flat up to the surface in the identical mode of first execution mode, the part concentrated above jut 12 of helical dislocation 22 is optionally removed by etching etc. afterwards, makes the jut 12 of this part be exposed.
Next, shown in Figure 56 B, nitride based III-V compound semiconductor layer 26 is 15 cross growth of nitride based III-V compound semiconductor layer from a left side.
Afterwards, carry out step after the nitride based III-V compound semiconductor of n type layer 16 growth in the identical mode of first execution mode, so that light-emitting diode to be provided.
According to the 23 execution mode, can access the advantage similar to first execution mode.
Next, the 24 execution mode of the present invention is described.
In the 24 execution mode, shown in Figure 57 A, jut 12 is formed on the substrate 11, and nitride based III-V compound semiconductor layer 15 is grown in the same mode of first execution mode.
Next, shown in Figure 57 B, mask (not shown) corresponding to jut 12 is formed on the nitride based III-V compound semiconductor layer 15 of jut 12 upper sections, for example pass through subsequently, the RIE method, powder injection process, sand-blast etc. carry out etching to nitride based III-V compound semiconductor layer 15 or grind up to exposing substrate 11 exposing.
Next, remove after the mask, shown in Figure 58 A, nitride based III-V compound semiconductor layer 26 from the opposite flank cross growth of the nitride based III-V compound semiconductor layer 15 that therefore forms pattern to bury the space between itself and the nitride based III-V compound semiconductor layer 15, shown in Figure 58 B.In this stage, between nitride based III-V compound semiconductor layer 26 and substrate 11, form the space.
Afterwards, shown in Figure 59 A, substrate is removed or peels off.Shown in Figure 58 B, can chemically or mechanical carry out removing or peeling off of substrate 11 by utilizing the space between nitride based III-V compound semiconductor layer 26 and the substrate 11 (physics).More particularly, for example, the etchant of given type or etching gas (active gases) be distributed in the space corrode substrate, be used to remove or peel off with side from nitride based III-V compound semiconductor layer 15,26.Replacedly, can heat, perhaps use ultrasonic irradiation so that substrate 11 pinch spallings to space, jut 12 or its peripheral material layer.In addition, such as being used for this purpose from such laser beams such as YAG laser, excimer laser.
Next, if remaining jut so just removes its complete etching.Like this, just obtain the nitride based III-V compound semiconductor substrate 27 that constitutes by nitride based III-V compound semiconductor layer 15,26 shown in Figure 59 B.
In order to remove or peel off substrate 11, can adopt such method, it for example comprises, the method of optionally dissolving or melting jut 12 by chemistry or thermal technology, and for example, optionally dissolve or melt the method for low temperature buffer layer (for example, the resilient coating of making by GaN, AlN, AlGaN, CrN etc.) by chemistry or thermal technology.These methods can suitably be selected according to the repellence or the durability of nitride based III-V compound semiconductor layer 15,26.Especially, adopting CrN to do under the situation of material of jut 12, the CrN resilient coating can be used as low temperature buffer layer, and like this, nitride based III-V compound semiconductor layer 15,26 can be easy to chemical mode from peeling off such as the such substrate 11 of Sapphire Substrate.
In this stage, nitride based III-V compound semiconductor layer 27 becomes out-of-flatness at its dorsal part, and is smooth by make the dorsal part of substrate 27 such as polishing.
Like this, shown in Figure 59 C, can access two first type surface all is smooth nitride based III-V compound semiconductor layer 27.
When the nitride based III-V compound semiconductor layer of given type is grown on this nitride based III-V compound semiconductor substrate 27, can make such as the so various types of semiconductor device of light-emitting diode.
Next, the 25 execution mode of the present invention is described.
In the 25 execution mode, shown in Figure 57 B, mask (not shown) corresponding to jut 12 is formed on the nitride based III-V compound semiconductor layer 15 of jut 12 upper sections, for example pass through subsequently, RIE method, powder injection process, sand-blast etc. carry out etching or are ground to the degree of depth that the dotted line shown in Figure 57 B is represented nitride based III-V compound semiconductor layer 15.In this case, before exposing substrate 11, stop etching or grind.
To carry out following step with the same mode of the 24 execution mode.
According to the 24 execution mode, can access the advantage similar to first execution mode.
Next, the 26 execution mode of the present invention is described.
In the 26 execution mode, shown in Figure 60 A, formation is than the little mask (not shown) of nitride based III-V compound semiconductor layer 15 width of jut 12 upper sections, utilizes mask that nitride based III-V compound semiconductor layer 15 is carried out etching by for example RIE method subsequently or grinds up to exposed surface 15.
Next, remove after the mask, shown in Figure 60 B, nitride based III-V compound semiconductor layer 26 from the opposite flank cross growth of the therefore nitride based III-V compound semiconductor layer 15 of composition to bury the space between the adjacent nitride base III-V compound semiconductor layer 15.At this moment, between nitride based III-V compound semiconductor layer 26 and substrate 11, form the space, as shown in the figure.
Afterwards, to carry out following step with the same mode of the 24 execution mode.
According to the 26 execution mode, can access the advantage similar to first execution mode.
Next, the 27 execution mode of the present invention is described.
In the 27 execution mode, shown in Figure 61 A, plane mask (not shown) is formed on the nitride based III-V compound semiconductor layer 15 of recess 12 upper sections, is used for bridge joint above jut partly 12 and whole recess 13.Subsequently by such as the RIE method nitride based III-V compound semiconductor layer 15 being carried out etching or grinding up to exposing jut 12.
Next, remove after the mask, shown in Figure 61 B, nitride based III-V compound semiconductor layer 26 from the opposite flank cross growth of the therefore nitride based III-V compound semiconductor layer 15 of composition to bury the space between the adjacent nitride base III-V compound semiconductor layer 15.
Afterwards, carry out following step in the same mode of the 24 execution mode.
According to the 27 execution mode, can access the advantage similar to first execution mode.
Next, the 28 execution mode of the present invention is described.
In the 28 execution mode, carry out the p lateral electrode in the same mode of first execution mode and form step before, following step is different with it.In order to form p lateral electrode 19, preferably insert and contain the Pd layer (for example to stop electrode material, Ag etc.) diffusion, perhaps by (for example forming thereon such as the nitride of such high melting point metal layer of Ti, W, Cr or its alloy or refractory metal, TiN, WN, TiWN, CrN etc.) layer and be used to not have the technology of the barrier metal layer of crystal boundary, amorphous, to prevent that by pressurizeing, heat or diffuse to form to p lateral electrode 19 be the inefficacy that Au in Au or the Sn layer or Sn occur that contains on upper strata (solder layer or projection).The technology that insertion contains the Pd layer for example is, the known Pd insert layer in the metal plating technology, and the material that is used for barrier metal layer is that the Al wiring technique and the Ag wiring technique of Si base electronic installation is known.
In order to protect the p lateral electrode 19 that directly contacts and can not resist thermal stress, show the example that carries out lamination such as the nitride of such refractory metal of Ti, W, Cr or its alloy or refractory metal as protective layer with the nitride based III-V compound semiconductor of p type layer 18.This protective layer can be as direct and the nitride based III-V compound semiconductor of p type layer 18 electrodes in contact.Because good stress durability and the bonding epistasis that adds; protective layer not only can be applied to the side of the nitride based III-V compound semiconductor of p side layer 18; and especially can be as the n lateral electrode 21 that contacts with the nitride based III-V compound semiconductor of n type layer 15, to substitute traditional Ti/Pt/Au electrode that adopts or to be used as ground floor n lateral electrode.For utilizing the bonding method that adds epistasis, can adopt the substrate lamination and no matter p side or n side, with the joint of reinforcement metal-metal or the joint of metal-insulator.Stress application durability and the bonding particular instance that adds epistasis comprise, uppermost surface by single-layer metal film or the film formed p lateral electrode 19 of multiple layer metal is made by Au, high melting point metal film of being made by Ti, W, Cr or its alloy or the nitride film of just having mentioned metal are formed on the conductive support substrate, are formed with the Au film on it and this Au film engages with p lateral electrode 19.
Specifically, in the 28 execution mode, shown in Figure 62 A, after forming p lateral electrode 19, wait by lift method (lift method) to form Ni film 41 with its covering p lateral electrode 19.Next, though not shown, for example, form the Pd film to cover Ni film 41, form metal nitride films, as films such as TiN, WN, TiWN, CrN to cover the Pd film, if subsequently if desired, further form Ti, W, Mo, Cr or its alloy film to cover the Pd film.Replacedly, can form the Pd film with covering p lateral electrode 19, and not form Ni film 41, if necessary subsequently, form TiN, WN, films such as TiWN, CrN, further form Ti, W, Mo, Cr or its alloy film to cover nitride film to cover the Pd film.
Next, shown in Figure 62 B, form to the corrosion-resisting pattern 42 of definite form to cover Ni film 41 and Pd film by photoetching.
Shown in Figure 62 C, for example, utilize corrosion-resisting pattern 42 to carry out etching by the RIE method, to form the boss portion 20 of trapezoid cross section as mask.The angle that forms between the first type surface of the inclined-plane of boss portion 20 and substrate 11 is that for example 35 spend.If desired, on the inclined-plane of boss portion 20, form λ/c dielectric film (λ is an emission wavelength).
Shown in Figure 62 D, n lateral electrode 21 is formed on the nitride based III-V compound semiconductor of the n type layer 15.
Next, shown in Figure 62 E, SiO 2Film 43 is formed on the whole surface of substrate as passivating film.Under the situation for adhesiveness, durability and the corrosion stability of bottom in considering process application, can adopt SiN film or SiON to substitute SiO 2Film.
Shown in Figure 62 F, SiO 2Film 43 forms Al film 44 as SiO on the inclined-plane of boss portion 20 subsequently by the back side etch attenuate 2Reflectance coating on the film 43.Provide this Al film 44 with the light that will produce from active layer 17 offside reflection, to improve light extraction efficiency to substrate 11.44 formation of Al film and n lateral electrode 21 are in the one end in contact.This is in order to increase the light reflection by not allowing to produce the space between Al film 44 and n lateral electrode 21.Afterwards, form SiO once more 2Film 43 thinks that passivating film provides enough thickness.
Next, shown in Figure 62 G, remove the SiO of Ni film 41 and n lateral electrode 21 upper sections by etching 2 Film 43 is with formation opening 45,46, thereby exposure is positioned at the Ni film 41 and the n lateral electrode 21 of these parts.
Next, shown in Figure 62 H, pad electrode 47 is formed on the Ni film 41 at opening 45 places, and pad electrode 48 also is formed on the n lateral electrode 21 at opening 46 places.
Shown in Figure 62 I, projection mask material 49 is formed on the top on entire substrate surface, and the projection mask material 49 that removes pad electrode 48 upper sections by etching exposes the pad electrode 48 of this part to form opening 50 subsequently.
Shown in Figure 62 J, projection mask material 49 is used to form Au projection 51 on pad electrode 48.Next, remove projection mask material 49.After the entire substrate surface formed projection mask material (not shown), the projection mask material that removes pad electrode 47 upper sections by etching was with the formation opening once more, thereby permission pad electrode 47 is exposed in this part.Afterwards, on pad electrode 47, form Au projection 52.
If desired, substrate 11 is polished or grinds to reduce its thickness, be formed with light emitting diode construction in above-mentioned mode on the substrate 11 from its dorsal part.Then substrate 11 is rule to form bar.Further bar is rule to form chip.
Note, Figure 62 A to the electrode layer laminated structure shown in the 62J just for example, when especially each electrode layer forms multilayer, need to improve p lateral electrode 19 and the adhesiveness between other metal level, stress durability and the cracking resistance line performance of making by the Ag electrode, thereby when consider suppressing the stress that causes because of the difference of thermal expansion coefficients that raises with unit temp by each metal level and suppressing diffusion between the adjacent metal, obtain low contact resistance and permission highly reflective by the character of keeping such as the Ag electrode.Therefore, if desired, should adopt this Al wiring technique of the above-mentioned Si of being used for base electronic installation.
Next, the 29 execution mode of the present invention is described.
In the 29 execution mode, (for example utilize the blue LED that obtains except that method and the red light emitting diodes that provides separately the green LED according to first execution mode, the AlGaInP light-emitting diode), the manufacturing to LED backlight is described.
In the mode same with first execution mode, the blue LED structure is formed on the substrate 11, the projection (not shown) is respectively formed on p lateral electrode 19 and the n lateral electrode 21, obtains the blue LED of flip-chip form subsequently by section (chipping).Similarly, obtain the green LED of flip-chip form.On the other hand, form red light emitting diodes, make the AlGaInP semiconductor stack be stacked on the n type GaAs substrate, be formed with the p lateral electrode on it so that the AlGaInP light-emitting diode of chip form to be provided so that diode structure to be provided.
These red light emitting diodes chips, green LED chip and blue led chips are installed in respectively such as on the such base of AlN.For example, these bases are installed in such as on the such substrate of Al substrate in the mode of base upset.Specifically shown in Figure 63 A.Among Figure 63 A, 61 expressions be substrate, 62 expressions be base, 63 expressions be the red diode chip for backlight unit of sending out, 64 expressions be the green LED chip, 65 expressions be blue led chips.Each for example all has the chip size of 350 μ m * 350 μ m these red light emitting diodes chips 63, green LED chip 64 and blue led chips 65.Red light emitting diodes chip 63 is installed is made the n lateral electrode be positioned on the base 62, green LED chip 64 and blue led chips 65 are installed make p lateral electrode and n lateral electrode be positioned on the base 62 by projection respectively.The base 62 that red light emitting diodes chip 63 is installed on it has the extraction electrode (not shown) of the n lateral electrode that forms given pattern.The n lateral electrode side of red light emitting diodes chip 63 is installed in the position of extracting electrode.Lead-in wire 67 is engaged, be used in the p of red light emitting diodes chip 63 lateral electrode and formation connection between the given pad electrode 66 that forms on the substrate 61, and the lead-in wire (not shown) is engaged, and is used in an end that extracts electrode and formation connection between another pad electrode that forms on the substrate 61.The extraction electrode of the p lateral electrode that is formed with given pattern on the base 62 of green LED chip 64 respectively and the extraction electrode (two all not shown) of n lateral electrode are installed on it.The p lateral electrode of green LED chip 64 and n lateral electrode are installed on the given position of extraction electrode of the extraction electrode of p lateral electrode and n lateral electrode by projection respectively.The lead-in wire (not shown) is engaged, be used at extraction electrode one end of the p of green LED chip 64 lateral electrode and be arranged on to form between the pad electrode on the substrate 61 connecting, and the lead-in wire (not shown) is engaged, and is used at extraction electrode one end of n lateral electrode and is arranged on to form between the pad electrode on the substrate 61 connecting.This is applicable to blue led chips 65.
Note, base 62 can save, wherein red light emitting diodes chip 63, green LED chip 64 and blue led chips 65 are directly installed on the printed circuit board (PCB) with heat dissipation characteristics of optional type, perhaps have on the inwall or outer wall of the plate of printed circuit board (PCB) function or housing.This make LED backlight or panel on the whole cost reduce.
Above-mentioned this red light emitting diodes chip 63, green LED chip 64 and blue led chips 65 is provided with as unit (unit), the unit of requirement with given arranged in patterns on substrate 61.The example of arranging is shown in Figure 64.Next, shown in Figure 63 B, seal to use its capping unit with transparent resin 68.Afterwards, the curing transparent resin 68.Transparent resin 68 solidifies by curing and shrinks (Figure 63 C) a little along with solidifying.Like this, shown in Figure 65, can access LED backlight, wherein each unit of being made by red light emitting diodes chip 63, green LED chip 64 and blue led chips 65 all is arranged in array on substrate 61.In this case, transparent resin 68 contacts with the dorsal part of the substrate 11 of green LED chip 64 and blue led chips 65, makes the situation that the difference of refractive index directly contacts less than the dorsal part of substrate 11 and air.This makes at the dorsal part of substrate 11, passes through to outside reflection of light rate from substrate 11 and reduces, thereby improve light extraction efficiency and therefore improve luminous efficiency.
This LED backlight is applicable to the backlight of liquid crystal board for example.
Next, the 30 execution mode of the present invention is described.
In the 30 execution mode, the red light emitting diodes chip 63 of requirement, green LED chip 64 and blue led chips 65 are arranged in given pattern, as the 29 execution mode.Afterwards, shown in Figure 66, with being applicable to that the transparent resin 69 of red light emitting diodes chip 63 seals to cover this light-emitting diode chip for backlight unit 63 with it.Equally, with being applicable to that the transparent resin 70 of green LED chip 64 seals to cover this light-emitting diode chip for backlight unit 64 with it.Seal to cover this blue led chips 65 with it with the transparent resin 71 that is applicable to blue led chips 65.Afterwards, transparent resin 69 to 71 is solidified.Resin 69 to 71 solidifies through curing and shrinks along with solidifying a little.Like this, each unit of being made by red light emitting diodes chip 63, green LED chip 64 and blue led chips 65 all is arranged in array on substrate 61, thereby obtains LED backlight.In this case, transparent resin 70,71 contacts with the dorsal part of the substrate 11 of green LED chip 64 and blue led chips 65, makes the situation that the difference of refractive index directly contacts less than the dorsal part of substrate 11 and air.This makes at the dorsal part of substrate 11, passes through to substrate 11 and reduces to outside reflection of light rate, thereby improve light extraction efficiency and therefore improve luminous efficiency.
This LED backlight is applicable to the backlight of liquid crystal board for example.
Next, the 31 execution mode of the present invention is described.
In the 31 execution mode, light emitting diode construction is formed on the substrate 11 according to the method for first execution mode, and p lateral electrode 19 and n lateral electrode 21 form bar shaped respectively.The projection (not shown) is respectively formed on p lateral electrode 19 and the n lateral electrode 21, subsequently substrate is rule so that the sheet of the quadrangle with intended size to be provided.Like this, just obtain having the integrated light-emitting diode of bar shaped luminescence unit.In this case, n lateral electrode 21 forms and surrounds bar shaped boss portion 20.Shown in Figure 68, this integrated light-emitting diode is installed on the base of being made by AlN etc. 72.In this case, be formed with the extraction electrode of p lateral electrode and the extraction electrode (the two is not shown) of n lateral electrode with given pattern respectively on the base 72, be formed with scolder 73,74 on it.The p lateral electrode 19 of integrated light-emitting diode and n lateral electrode 21 are arranged in respectively on scolder 73 and 74, make scolder 73,74 fusings for joint afterwards.
Each light-emitting diode can provide protective circuit, is used for the purpose of the overcurrent protection of the overcurrent (for example, (reverse parallel connection) be connected in parallel Zener diode) in the position that does not hinder light extraction.
Next, the 32 execution mode of the present invention is described.
In the 32 execution mode, the manufacturing of light source battery unit is described, it has also utilized the red light emitting diodes of independent setting except blue LED and green LED that the method according to first execution mode obtains.
Shown in Figure 69 A, in the 32 execution mode, the unit 75 of requirement with given arranged in patterns on printed circuit board (PCB) 76, as the 29 execution mode, each unit 75 comprises red light emitting diodes chip 63, green LED chip 64 and blue led chips 65 in every kind and at least with given arranged in patterns.In this case, individual unit 75 comprises a red light emitting diodes chip 63, a green LED chip 64 and a blue led chips 65, and they are arranged in the summit of regular triangle.Figure 69 B shows the unit 75 of amplification.Interval a in each unit 75 between red light emitting diodes chip 63, green LED chip 64 and the blue led chips 65 is for example 4mm, though be not limited to this value.Interval b between the unit 75 is for example 30mm, though be not limited to this value.For printed circuit board (PCB) 76, for example can use, FR4 (abbreviation of flame retardant type 4) substrate, metal core substrate, flexible printed circuit board etc. are though be not limited to these.This is because other printed circuit board (PCB) also can adopt, as long as they are the printed circuit board (PCB)s with heat dispersion.As the 29 execution mode, seal to cover each unit 76 with it with transparent resin.Replacedly, as the 30 execution mode, can realize that sealing is to cover red light emitting diodes chip 63 with transparent resin 69, can seal to cover green LED chip 64 with transparent resin 70, can seal to cover blue led chips 65 with transparent resin 71.Like this, each unit 75 that is made of red light emitting diodes chip 63, green LED chip 64 and blue led chips 65 all is arranged on the printed circuit board (PCB) 76, thereby obtains the light source battery unit.
The object lesson that unit 75 is arranged in the printed circuit board (PCB) 76 is respectively shown in Figure 70 and 71, though be not limited to these.Example shown in Figure 70 is, unit 75 is arranged in 4 * 3 two-dimensional array, and the example shown in Figure 71 is that unit 75 is arranged in 6 * 2 two-dimensional array.
Figure 72 shows other arrangement of unit 75.In this case, each unit 75 comprises a red light emitting diodes chip 63, two green LED chips 64 and blue led chips 65, and they for example are arranged in, foursquare summit.Two green LED chips 64 are positioned at the summit of a cornerwise opposite end of square, and red light emitting diodes chip 63 and blue led chips 65 are positioned at the summit of another cornerwise opposite end.
If the independent or a plurality of arrangements of this light source battery unit can access so, for example, be suitable for and make liquid crystal board LED backlight backlight.
For as Fig. 7 to 11, the red light emitting diodes chip 63 of unit 75 especially shown in Figure 11, green LED chip 64 and blue led chips 65, because wiring two-layer wiring technology for p lateral electrode 19 and n lateral electrode 21, it can be installed on the printed circuit board (PCB) 76, perhaps is installed on the printed circuit board (PCB) 76 by base.
Note, though in general, pad electrode part and wiring portion routine on the printed circuit board (PCB) 76 are formed by Au, but its all or part of can be by have good durability and the bonding refractory metal that adds epistasis like this such as Ti, W, Cr or its alloy, the metal nitride that perhaps be formed with Au on it forms.These materials can pass through, for example, and formation such as plating, electroless plating, vacuum moulding machine (fast deposition flashdesposition), sputtering method.Replacedly, pad electrode part or wiring portion are formed by the Au that is formed with above-mentioned this material on it.Also replacedly, pad electrode part or wiring portion can be by forming such as Ti, W, Cr or the such refractory metal of its alloy, then by nitrogenize and form once more, make surface recovery arrive the state before the nitrogenize thereon such as Ti, W, Cr or the such high melting point metal layer of its alloy.Afterwards, light-emitting diode chip for backlight unit 63 to 65 from TiW electrode or Au electrode side by die bonding, if desired, bonding by the monofilm of making by Ti, W, Cr, Au etc.
When being connected to, installation is installed in printed circuit board (PCB) 76; the transistor device (circuit) of open base (based open); diac device (circuit); during the protection chip (circuit) of the light-emitting diode chip for backlight unit 63 to 65 on the negative-resistance device (circuit) etc.; can adopt such as above-mentioned employing such as Ti, W, Cr or its alloy or the such electrode structure of metal nitride; thereby improve the light source battery unit in adhesion strength, the reliability of aspects such as thermal stress durability.
The part of printed circuit board (PCB) 76 except that the transparent resin 68 to 79 that is formed by sealing can apply with the resist heavy back at last, and this resist is white as far as possible, and feasible light from light-emitting diode chip for backlight unit 63 to 65 is inhibited because of being printed circuit board 76 absorptions.
Though specifically described embodiments of the present invention, the present invention should not be interpreted as being limited to these execution modes, can carry out various deformation and replacement within the scope of the invention.
For example, the technology of the quantitative value of pointing out in the first to the 32 execution mode, material type, structure, shape, substrate type, raw material, jut 12 and recess 13 and location all are for example.If desired, can adopt and be different from top quantitative value, material, structure, shape, substrate, raw material and technology.
Specifically, for example, in the first to the 32 execution mode, p type layer and n type layer can be put upside down with respect to types of conductors.
If desired, can be with the two or more combinations in the first to the 32 execution mode.
Notice that the light-emitting diode that has the knurled surfaces structure of patterning on light extraction face or light reflection surface comprises these shown in Figure 73 to 76.
In the light-emitting diode shown in Figure 73, the nitride based III-V compound semiconductor of n type layer 82, the nitride based III-V compound semiconductor of n type layer 83, active layer 84, the nitride based III-V compound semiconductor of p type layer 85 and the nitride based III-V compound semiconductor of p type layer 86 order are grown on the substrate 81.Afterwards, nitride based III-V compound semiconductor layer 83, active layer 84, the nitride based III-V compound semiconductor of p type layer 85 and the nitride based III-V compound semiconductor of p type layer 86 are etched with formation boss portion 87.The nitride based III-V compound semiconductor of p type layer 86 is carried out surperficial indentation and p lateral electrode 88 is buried in the recess.N lateral electrode 89 is formed on the nitride based III-V compound semiconductor of the n type layer 82 with boss portion 87 adjacent parts.Adopt this light-emitting diode, light can extract or extract from the nitride based III-V compound semiconductor of p type layer 86 side from substrate 81 sides.For substrate 81, can adopt such as the such substrate of substrate 11.
In the light-emitting diode shown in Figure 74, except reflectance coating 90 is formed on the dorsal part of substrate 81, adopt this structure shown in Figure 73.The light that this reflectance coating 90 allows to send from active layer 84 makes light to be extracted the outside from the nitride based III-V compound semiconductor of p type layer 86 side to the nitride based III-V compound semiconductor of p type layer 86 lateral reflection.
In the light-emitting diode shown in Figure 75, except reflectance coating 90 is formed on the dorsal part of the nitride based III-V compound semiconductor of p side layer 86, adopt this structure shown in Figure 73.The light that this reflectance coating 90 allows to send from active layer 84 is to substrate 11 lateral reflections, so light may be extracted the outside from substrate 11 sides.
In the light-emitting diode shown in Figure 76, the nitride based III-V compound semiconductor of n type layer 83, active layer 84 and the nitride based III-V compound semiconductor of p type layer 85 are on substrate 81 after the epitaxial growth, form jut 91 thereon, subsequently with the same nitride based III-V compound semiconductor of the mode growing p-type layer 86 of first execution mode.Jut 91 is identical with jut 12.
Notice that among Figure 76, reflecting electrode can be formed on the nitride based III-V compound semiconductor of the p type layer 86 that contacts with jut 91.Replacedly, do not consider the material of the jut 91 of optical clear or reflection, the thickness of the nitride based III-V compound semiconductor of p type layer 24 can suitably be adjusted, for example, to λ/4, form the reflecting electrode that contacts with jut 91 on it, further form the p lateral electrode subsequently.This allows a kind of structure, wherein reflects from substrate 81 with high reflectance at the light that active layer 84 produces from any direction, and the good electric current from the p lateral electrode when guaranteeing light-emitting diode work simultaneously passes through.
The present invention is contained in Japanese patent application JP2005-275504 that proposed in Japan Patent office on September 22nd, 2005 and the relevant theme of Japanese patent application JP2006-215342 that proposed in Japan Patent office on October 8th, 2006, this in conjunction with its full content with for referencial use.

Claims (24)

1, a kind of method of making light-emitting diode, it comprises the following steps:
Be provided at the substrate that has a plurality of juts on the one first type surface and growth regulation mononitride base III-V compound semiconductor layer on each recess at described substrate under the state that forms the triangular-section, wherein, jut is by making with the dissimilar material of described substrate, and the basal surface of recess is the leg-of-mutton end;
On described substrate from the described first nitride based III-V compound semiconductor layer cross growth second nitride based III-V compound semiconductor layer; And
Grow the 3rd nitride based III-V compound semiconductor layer of first conductivity type of order on the described second nitride based III-V compound semiconductor layer, the tetrazotization thing base III-V compound semiconductor layer of the active layer and second conductivity type.
2, basis the process of claim 1 wherein in the growth course of the described first nitride based III-V compound semiconductor layer,
Under the state that is forming the triangular-section, when arriving near the inclined-plane of the described first nitride based III-V compound semiconductor layer or its with the dislocation that the interface produced perpendicular to the basal surface of the described spill of a first type surface direction, dislocation is to be parallel to the direction bending of this first type surface.
3, according to the process of claim 1 wherein that described jut has 0.3 μ m or above height.
4, be 100 °＜θ＜160 ° according to the process of claim 1 wherein that described jut has the angle theta that forms between the side that tilts with respect to this first type surface and this side and this first type surface.
5, according to the process of claim 1 wherein that the female portion has down the trapezoid cross section.
6, according to claim 5 method, wherein the degree of depth when recess is d, the basal surface width of recess is Wg, when the angle that forms between the inclined-plane of the described first nitride based III-V compound semiconductor layer and this first type surface is α, set up the relation of 2d 〉=Wgtan α under the state of triangular-section.
7, according to the process of claim 1 wherein that this first type surface has jut and recess alternately.
8, according to the process of claim 1 wherein that jut has the hexagon flat shape, be two-dimensional arrangements, and form recess to center on each jut with the comb form.
9, according to the process of claim 1 wherein that described jut made by dielectric material.
10, according to the process of claim 1 wherein that the reflectivity of described jut has the reflectivity that is lower than described substrate.
11, method according to claim 1, wherein after the described second nitride based III-V compound semiconductor layer cross growth, being removed to small part of the jut top of the described first nitride based III-V compound semiconductor layer and the described second nitride based III-V compound semiconductor layer and/or recess top, the described the 3rd nitride based III-V compound semiconductor layer cross growth on the left part of the described second nitride based III-V compound semiconductor layer, described active layer and described tetrazotization thing base III-V compound semiconductor layer are grown on the described the 3rd nitride based III-V compound semiconductor layer in proper order.
12, method according to claim 1, wherein after the described second nitride based III-V compound semiconductor layer cross growth, being removed to small part of the jut top of the described first nitride based III-V compound semiconductor layer and the described second nitride based III-V compound semiconductor layer and/or recess top, the 5th nitride based III-V compound semiconductor layer cross growth on the left part of the described second nitride based III-V compound semiconductor layer, the described the 3rd nitride based III-V compound semiconductor layer, described active layer and described tetrazotization thing base III-V compound semiconductor layer are grown on the described the 5th nitride based III-V compound semiconductor layer in proper order.
13, a kind of light-emitting diode comprises:
Substrate has a plurality of juts on an one first type surface,, wherein jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on this substrate and does not form the space in each recess of substrate, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the described the 6th nitride based III-V compound semiconductor layer,
Wherein, in the described the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
14, a kind of method that is used to make integrated light-emitting diode, wherein integrated a plurality of light-emitting diodes, the method comprising the steps of:
Be provided at the substrate that has a plurality of juts on the one first type surface and growth regulation mononitride base III-V compound semiconductor layer on each recess at described substrate under the state that forms the triangular-section, wherein, each jut is by making with the dissimilar material of described substrate, and the basal surface of recess is the leg-of-mutton end;
On described substrate from the first nitride based III-V compound semiconductor layer cross growth, the second nitride based III-V compound semiconductor layer; And
The order tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type of growing on the described second nitride based III-V compound semiconductor layer.
15, a kind of integrated light-emitting diode, wherein integrated a plurality of light-emitting diodes,
Comprising one of at least of a plurality of light-emitting diodes:
Substrate has a plurality of juts on an one first type surface, wherein jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on this substrate and does not form the space in each recess of substrate, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the 6th nitride based III-V compound semiconductor layer,
Wherein, in the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives the basal surface that utilizes recess and does near the leg-of-mutton inclined-plane at the end or its, and there to be parallel to the direction bending of this first type surface.
16, a kind of method of growing nitride base III-V compound semiconductor layer, it comprises the following steps:
Be provided at the substrate that has a plurality of juts on the one first type surface and growth regulation mononitride base III-V compound semiconductor layer on each recess at described substrate under the state that forms the triangular-section, wherein each jut is by making with the dissimilar material of described substrate, and the basal surface of recess is the leg-of-mutton end; And
On described substrate from the first nitride based III-V compound semiconductor layer cross growth, the second nitride based III-V compound semiconductor layer.
17, a kind of substrate of growing nitride base III-V compound semiconductor layer, it comprises:
Substrate has a plurality of juts on an one first type surface, wherein each jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on the described substrate and does not form the space in each recess of substrate,
Wherein, in the described the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
18, a kind of light source battery unit, it comprises, is positioned at a plurality of unit on the printed substrate, each unit comprises red light emitting diodes, at least one in every kind of green LED and the blue LED,
Selected at least one light-emitting diode comprises from red light emitting diodes, green LED and blue LED:
Substrate has a plurality of juts on an one first type surface, wherein jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on the described substrate and does not form the space in each recess of substrate, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the described the 6th nitride based III-V compound semiconductor layer,
Wherein, in the described the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
19, a kind of LED backlight, wherein having arranged every kind all has a plurality of red light emitting diodes, green LED and blue LED,
Selected at least a type light-emitting diode comprises from red light emitting diodes, green LED and blue LED:
Substrate has a plurality of juts on an one first type surface, wherein jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on this substrate and not be used in each recess of substrate and forms the space, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the 6th nitride based III-V compound semiconductor layer,
Wherein, in the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
20, a kind of light emitting diode illuminating apparatus, wherein having arranged every kind all has a plurality of red light emitting diodes, green LED and blue LED,
Selected at least a type light-emitting diode comprises from red light emitting diodes, green LED and blue LED:
Substrate has a plurality of juts on an one first type surface, wherein jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on this substrate and does not form the space in each recess of substrate, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the 6th nitride based III-V compound semiconductor layer,
Wherein, in the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
21, a kind of light emitting diode indicator, wherein having arranged every kind all has a plurality of red light emitting diodes, green LED and blue LED,
Selected at least a type light-emitting diode comprises from red light emitting diodes, green LED and blue LED:
Substrate has a plurality of juts on an one first type surface, wherein, jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on this substrate and does not form the space in each recess of substrate, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the 6th nitride based III-V compound semiconductor layer,
Wherein, in the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
22, a kind of electronic installation with one or more light-emitting diodes,
At least one light-emitting diode comprises:
Substrate has a plurality of juts on an one first type surface, wherein jut is by making with the dissimilar material of substrate;
The 6th nitride based III-V compound semiconductor layer, it is grown on this substrate and does not form the space in each recess of substrate, and
The tetrazotization thing base III-V compound semiconductor layer of the 3rd nitride based III-V compound semiconductor layer, active layer and second conductivity type of first conductivity type, it is formed on the 6th nitride based III-V compound semiconductor layer,
Wherein, in the 6th nitride based III-V compound semiconductor layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
23, a kind of method of making electronic installation comprises the following steps:
Be provided at the substrate that has a plurality of juts on the one first type surface and growth regulation one deck on each recess at substrate under the state that forms the triangular-section, jut is by making with the dissimilar material of described substrate, and the basal surface of recess is the leg-of-mutton end; And
On described substrate from the described ground floor cross growth second layer.
24, a kind of electronic installation comprises:
Substrate has a plurality of juts on an one first type surface, wherein jut is by making with the dissimilar material of substrate;
Do not form the 3rd layer of space in each recess at substrate in growth on the described substrate, wherein
In the 3rd layer, the dislocation that produces from the interface along the basal surface of the recess of the vertical direction of this first type surface arrives that the basal surface that utilizes recess is made the leg-of-mutton inclined-plane at the end or near it and there to be parallel to the direction bending of this first type surface.
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