CN1874022A - Light-emitting diode, integrated light-emitting diode and method for their production, method for growing, light source cell unit, backlight device, display and electronic device - Google Patents

Abstract

A method for making a light-emitting diode, which including the steps of: providing a substrate having at least one recessed portion on one main surface and growing a first nitride-based III-V group compound semiconductor layer through a state of making a triangle in section having a bottom surface of the recessed portion as a base thereby burying the recessed portion; laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer over the substrate; and successively growing a third nitride-based III-V group compound semiconductor layer of a first conduction type, an active layer and a fourth nitride-based III-V group compound semiconductor layer of a second conduction type on the second nitride-based III-V group compound semiconductor layer.

Description

Light emitting diode, integrated light emitting diode, method of manufacturing the same, method of growing the same, light source unit device, backlight device, display, and electronic device

Technical Field

The present invention relates to a light emitting diode and a method of manufacturing a light emitting diode, and also relates to an integrated light emitting diode and a method of manufacturing an integrated light emitting diode. As described above, the present invention also relates to a methodof growing a nitride-based group III-IV compound semiconductor, and a light source unit (cell unit), a light emitting diode backlight (backlight), a light emitting diode display, and an electronic device using the light emitting diode. More particularly, the present invention relates to a light emitting diode using a nitride-based group III-V compound semiconductor and various devices or apparatuses using the same.

Background

In the case of epitaxially growing a GaN semiconductor on a different type of substrate such as a sapphire substrate, high-density crystal defects, particularly threading dislocations (threading dislocations), due to a large difference between lattice constants or thermal expansion coefficients, may occur.

To avoid this, a dislocation density reduction technique using selective lateral growth has been widely used so far. According to this technique, a GaN semiconductor is epitaxially grown on a sapphire substrate or other substrate, and then the substrate is removed from the crystal growth apparatus. From SiO₂Etc., is formed on the GaN semiconductor layer, and then the substrate is returned to the crystal growth apparatus, where the GaN semiconductor is epitaxially grown again by using the growth mask.

Although this technique ensures reduction of dislocation density in the upper GaN semiconductor layer, it requires two epitaxial growth cycles, which in turn causes an increase in cost.

To overcome this problem, a method has been proposed in which different substrates are treated in advance to provide a patterned indented surface on which a GaN semiconductor is epitaxially grown (see, for example, Report of Mitsubishi Cable Industries, ltd., No.98, October, 2001, entitled "development of High-power UV led manufacturing a leds Technique" and japanese patent laid-open nos. 2004-6931 and 2004-6937). This approach is schematically illustrated in fig. 36A to 36C. As shown in fig. 36A, c the sapphire substrate 101 is processed to provide a patterned toothed surface on one main surface thereof. Reference numeral 101a denotes a recessed portion, and reference numeral 101b denotes a protruding portion. These recessed portions 101a and protruding portions 101b extend along the<1-100>direction of the sapphire substrate. Next, for example, through the steps of fig. 36B and 36C, the GaN semiconductor 102 is grown on the sapphire substrate 101. In fig. 36C, the dotted line indicates a growth interface during growth. A feature of this method is shown in fig. 36C, for example, a gap 103 is formed between the sapphire substrate 101 and the GaN semiconductor layer 102 in each of the recessed portions 101 a. Fig. 37 schematically shows a crystal defect distribution on the GaN semiconductor layer 102 grown according to this method. As shown in fig. 37, threading dislocations 104 occur in the GaN semiconductor layer 102 above each protruding portion 101b in a direction perpendicular to the interface with the upper surface of the protruding portion 101b, forming a high defect density region 105. On the other hand, a portion located above the recessed portion 101a and between the adjacent high defect density regions 105 is a low defect density region 106.

Note that in fig. 36C, the shape of the buried form of the GaN semiconductor layer 102 located below the gap 103 formed within the recessed portion 101a of the sapphire substrate 101 is rectangular. This buried form may also be triangular in some cases. In this case, the GaN semiconductor layer 102 buried in the recessed portion 101a is in contact with the GaN semiconductor layer 102 grown laterally from the protruding portion 101b, thereby forming a gap, such as in the case of a rectangular buried form.

For reference, fig. 38A to 38D show how the GaN semiconductor layer 102 is grown in the case of the<11-20>direction in which the extending directions of the concave portion 101a and the convex portion 101b intersect at right angles with the<1-100>direction of the sapphire substrate 101.

FIGS. 39A to 39F schematically show another growth method in the related art, different from the aforementioned method (see, for example, Japanese patent laid-open No. 2003-318441). As shown in fig. 39A, with a sapphire substrate manufactured to have a patterned toothed surface, a GaN semiconductor layer 102 is grown on the substrate through the steps shown in fig. 39B to 39F. According to the method, the GaN semiconductor layer 102 is formed, but no gap is formed between the sapphire surface 101 and the GaN semiconductor layer 102.

Disclosure of Invention

As described above, with the growth method in the related art shown in fig. 36A to 36C, the gap 103 is formed between the sapphire substrate 101 and the GaN semiconductor layer 102. According to the results of experiments conducted by the inventors, a problem arises in forming a light emitting diode structure by growing a GaN semiconductor layer on the GaN semiconductor layer 102, that is, the light emitting efficiency of such a light emitting diode is low. The following considerations may be considered: once the light emitting diode operates, light emitted from the active layer is repeatedly reflected at the gap 103, and further absorbs the light, thereby deteriorating light extraction efficiency.

On the other hand, with another growth method in the related art shown in fig. 39A to 39F, there is proposed: no gap is formed between the sapphire substrate 101 and the GaN semiconductor layer 102. However, it is difficult to reduce the dislocation density of the GaN semiconductor layer 102 to a similar degree to that of the growth method in the related art shown in fig. 36A to 36C. This leads to the fact that when a light emitting diode structure is used by growing GaN semiconductor layers on GaN semiconductor layers 102 having a high dislocation density, these GaN semiconductor layers also increase the dislocation density, thereby causing a decrease in light emission efficiency.

There is a need to provide a light emitting diode which is remarkably improved in light extraction efficiency and greatly improved in crystallinity of a nitride-based III-V compound semiconductor layer of the light emitting diode to produce very high light emission efficiency by solving the above-discussed problems such as gap formation, which can be manufactured at low cost by an epitaxial growth method, and a method of manufacturing the above-mentioned type of diode.

It is also desirable to provide an integrated light emitting diode and a method of manufacturing the integrated light emitting diode having the above advantages.

Further, there is a need to provide a method of growing a nitride-based group III-V compound semiconductor that is suitable for use in the fabrication of such light emitting diodes or integrated light emitting diodes.

In addition, it is also necessary to provide various high-performance devices such as a light source unit device, a light-emitting diode backlight device, a light-emitting diode display, and other electronic devices using the above-described light-emitting diodes.

Other features of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings.

In the following, several embodiments of the invention will be outlined.

According to a first embodiment of the present invention,there is provided a method of manufacturing a light emitting diode, the method including the steps of: providing a substrate having at least one notch portion on one main surface thereof, growing a first nitride-based group III-V compound semiconductor layer by forming a state of a triangle having a bottom surface of the notch portion as a base in cross section, thereby burying the notch portion; laterally growing a second nitride-based group III-V compound semiconductor layer from the first nitride-based group III-V compound semiconductor layer on the substrate; a third nitride-based III-V group compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having the second conductivity type are sequentially grown on the second nitride-based III-V group compound semiconductor layer.

The first nitride-based group III-V compound semiconductor layer and the second nitride-based group III-V compound semiconductor layer may be any one type of p, n, and i, and may be the same conductivity type or conductivity types different from each other. In addition, two or more portions of different types may be mixed in the first nitride-based group III-V compound semiconductor layer and the second nitride-based group III-V compound semiconductor layer.

When the dislocation reaches the inclined plane of the first nitride-based III-V compound semiconductor layer or the vicinity thereof, wherein the semiconductor layer is in a state of forming a triangle in cross section, it bends away from the triangle in a direction parallel to the one main surface, as the dislocation reaches the inclined plane of the first nitride-based III-V compound semiconductor layer or the vicinity thereof, when the first nitride-based III-V compound semiconductor layer and the second nitride-based III-V compound semiconductor layer are formed separately, a first recess having a first width is formed on the bottom of the substrate recess portion, a second recess having a second width is formed on the opposite side of the substrate recess portion, the second width is greater than the first width, these first and second recesses are formed by reflection of the grown first nitride-based III-V compound semiconductor layer and second nitride-based III-V compound semiconductor layer in a manner that the first and second recesses are formed by a generally planar shape of a trapezoidal base III-V compound semiconductor layer, or a hexagonal base III-V compound semiconductor layer, and the second recess having a generally planar shape, a width equal to or less than a width, preferably a width equal to a width of a width equal to 0.2, a width, which is greater than a width, or greater than a width, and a width, which may be provided by a width of a hexagonal base III-V semiconductor layer, and a thickness of a thickness, and a thickness of a.

In order to grow the first nitride based group III-V compound semiconductor layer on the notch portion of the substrate, an amorphous layer (amorphous layer) may be formed on the substrate on the opposite side of the notch portion. The amorphous layer will be the growth mask. This is because nucleation on the amorphous layer is impossible at the time of growth. For example, a surface layer of a single crystal substrate may be subjected to ion implantation for amorphization or may be formed into an amorphous layer on the substrate by any of film growth methods. The amorphous layer is composed of an amorphous silicon (a-Si) film, for example, an amorphous silicon film including SiO₂Film, SiN film (including not only Si₃N₄Films also include those having different compositions formed by plasma Chemical Vapor Deposition (CVD) and SiON (including the case where the ratio between O and N changes and the refractive index and the side shape conform to the intended design), and theamorphous layer is generally an insulating film. Further, a first amorphous layer, a second amorphous layer, and a third amorphous layer, which are used as growth masks when the first nitride-based III-V compound semiconductor layer is grown, may be formed in this order on the substrate on the opposite side of each notch portion. In this case, the second amorphous layer should be an amorphous layer that can be selectively etched with respect to, for example, the first and third amorphous layers.

After laterally growing the second nitride-based group III-V compound semiconductor layer, there may be a process in which a portion other than a portion above each of the notch portions of the second nitride-based group III-V compound semiconductor layer is removed, then a third nitride-based group III-V compound semiconductor layer is laterally grown on the second nitride-based group III-V compound semiconductor layer on the remaining notch portions, and then an active layer and a fourth nitride-based group III-V compound semiconductor layer are sequentially grown on the third nitride-based group III-V compound semiconductor layer. Alternatively, after laterally growing the second nitride-based group III-V compound semiconductor layer, there may be another process in which a portion other than a portion located on each notched portion of the second nitride-based group III-V compound semiconductor layer may be removed, followed by laterally growing a fifth nitride-based group III-V compound semiconductor layer on the second nitride-based group III-V compound semiconductor layer on the remaining notched portion, and then sequentially growing a third nitride-based group III-V compound semiconductor layer, an active layer, and a fourth nitride-based group III-V compound semiconductor layer on the fifth nitride-based group III-V compound semiconductor layer.

The third nitride-based III-V group compound semiconductor layer isformed to have an electrode of the first conductivity type, which is electrically connected to or in contact with the third nitride-based III-V group compound semiconductor layer. Likewise, an electrode having the second conductivity type is formed on the fourth nitride-based group III-V compound semiconductor layer in a state of being electrically connected to the fourth layer.

The substrate may be composed of a variety of materials. As the substrate composed of a different type of material from the nitride-based group III-V compound semiconductor layer, for example, mention is made of sapphire (having C, a, r-planes and an off face), SiC (including 6H, 4H and 3C), Si, ZnC, ZnO, LiMgO, GaAs, MgAl₂O₄Etc. formed on the substrate. Preferably, hexagonal or cubic substrates, more preferably hexagonal substrates, composed of these materials are used. Alternatively, a substrate composed of a nitride-based group III-V compound semiconductor, such as GaN, InAlGaN, AlN, or the like, may also be used. Those obtained by growing a nitride-based group III-V compound semiconductor layer on a substrate composed of a material different from the nitride-based group III-V compound semiconductor and forming a notch portion in the nitride-based group III-V compound semiconductor layer may also be used as an alternativeAnd (6) selecting. Further, another type of substrate may be used in which a substrate is formed of a different constituent material from the nitride-based group III-V compound semiconductor, a layer is provided on the substrate, the layer is constituted of a different material in type from the nitride-based group III-V compound semiconductor, the layer is formed as a stacked polycrystalline or amorphous layer constituted of at least one material, and then the layer is partially patterned to the depth of the substrate, thus forming a surface of a toothed pattern.

Note that: the substrate can be removed if desired.

Most generally, the nitride-based group III-V compound semiconductor layers used as the first to fifth nitride-based group III-V compound semiconductor layers and the active layer are represented by the formula Al_xB_yGa_1-x-y-zIn_zAs_uN_1-u-vP_vWherein x is 0. ltoreq. x.ltoreq.1, y is 0. ltoreq. y.ltoreq.1, z is 0. ltoreq. z.ltoreq.1, u is 0. ltoreq. u.ltoreq.1, v is 0. ltoreq. v.ltoreq.1, and x + y + z is 0. ltoreq. x + z<1 and u + v 0<1. Preferably, the expression mentioned is Al_xB_yGa_1-x-y-zIn_zN, wherein x is more than or equal to 0 and less than or equal to 1, y is more than or equal to 0 and less than or equal to 1, z is more than or equal to 0 and less than or equal to 1, and x + y + z is more than or equal to 0 and less than or equal to 1. More preferably, the semiconductor layer is made of Al_xGa_1-x-zIn_zN, wherein x is more than or equal to 0 and less than or equal to 1, and z is more than or equal to 0 and less than or equal to 1. Specific examples include GaN, InN, AlN, AlGaN, InGaN, AlGaInN, and the like. The first nitride-based III-V group compound semiconductor layer to be buried In the notch portion of the substrate is preferably made of GaN, In_xGa_1-xN、Al_xGa_1-xN、Al_xIn_yGa_1-x-yN is In_xGa_1-xIn N, x is more than 0 and less than 0.5; in Al_xGa_1-xIn N, x is more than 0 and less than 0.5; in Al_xIn_yGa_1-x-yIn N, x is more than 0 and less than 0.5, and y is more than 0 and less than 0.2. The first conductivity type may be n-type or p-type, and correspondingly, the second conductivity type may be p-type or n-type.

For growing the nitride-based III-V group compound semiconductor layers constituting the first to fifth nitride-basedIII-V group compound semiconductor layers and the active layer, for example, metal-organic chemical vapor deposition (MOCVD), hydride or Halide Vapor Phase Epitaxy (HVPE), Molecular Beam Epitaxy (MBE), and many other epitaxial methods may be used.

According to a second embodiment of the present invention, there is provided a light emitting diode including: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type grown on the sixth nitride-based group III-V compound semiconductor layer. In the light emitting diode, in the sixth nitride based III-V group compound semiconductor layer, a dislocation occurs from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, the dislocation may reach or approach an inclined surface of a triangle having the bottom surface of the recess portion as a base, and be bent in a direction parallel to the one main surface.

According to a third embodiment of the present invention, there is provided a light emitting diode including: a substrate having at least one notch portion on one main surface; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type grown on the sixth nitride-based group III-V compound semiconductor layer. In the light emitting diode, the substrate may form a first pit (pit) having a first width on a bottom surface of the recess portion, and a second pit having a second width larger than the first width on an opposite side of the recess portion.

According to the second, third and later fifth, sixth, eighth to seventeenth embodiments of the present invention, the sixth nitride-based III-V compound semiconductor layer corresponds to the first nitride-based III-V compound semiconductor layer and the second nitride-based III-V compound semiconductor layer in the first embodiment, respectively.

It should be noted that: all statements made in relation to the first exemplary embodiment are likewise true for the second and third exemplary embodiments of the present invention and the fourth to eighteenth exemplary embodiments to be found later, except where stated otherwise or required otherwise in individual exemplary embodiments.

According to a fourth embodiment of the present invention, there is provided a method of manufacturing an integrated light emitting diode having a plurality of light emitting diodes integrated therein, the method comprising the steps of: growing a first nitride-based group III-V compound semiconductor layer on at least one of the recess portions on the one main surface of the substrate by forming a state of a triangle having a bottom surface of the recess portion as a base on the cross section, thereby burying the recess portion; laterally growing a second nitride-based group III-V compound semiconductor layer from the first nitride-based group III-V compound semiconductor layer on the substrate; a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer are sequentially grown on the second nitride-based group III-V compound semiconductor layer.

According to a fifth embodiment of the present invention, there is provided an integrated light emitting diode, wherein a plurality of light emitting diodes are integrated in the integrated light emitting diode, and at least one of the light emitting diodes comprises: a substrate having at least one notch portion on one main surface; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductive type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductive type formed on the sixth nitride-based group III-V compound semiconductor layer. In the light emitting diode, in the sixth nitride-based III-V group compound semiconductor layer, a dislocation occurs from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the recess portion as a base, and bends in a direction parallel to the one main surface.

According to a sixth embodiment of the present invention, there is provided an integrated light emitting diode, wherein a plurality of light emitting diodes are integrated in the integrated light emitting diode, and at least one light emitting diode comprises: a substrate having at least one notch portion on one main surface; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type grown on the sixth nitride-based group III-V compound semiconductor layer. In the light emitting diode, a first pit having a first width may be formed on a bottom surface of the substrate recess portion, and a second pit having a second width larger than the first width may be formed on an opposite side of the substrate recess portion.

In the fourth to sixth embodiments of the present invention, the integrated light emitting diode can be applied in various fields. Typical uses are light emitting diode backlights, such as liquid crystal displays, light emitting diode illuminators, light emitting diode displays, and the like. The arrangement and manner of the integrated light emitting diodes with respect to the diodes is arbitrary. For example, the light emitting diodes can be arranged in a two-dimensional array, or stripe-shaped light emitting diodes are arranged in one or more rows. The form of the integrated light emitting diode includes a form in which a wafer having a semiconductor layer stacked structure is subjected to a block process according to a so-called semiconductor manufacturing technique to provide a circuit pattern and integrated and finely (microscopically) arranged individual light emitting diodes, or a form in which individual light emitting diodes previously divided into micro-chips (microscopically) are finely arranged in a plurality on the circuit pattern. In addition, the light emitting diodes may be driven independently or simultaneously. Alternatively, a group of light emitting diode blocks in a randomly arranged region (i.e., region driving) may be independently driven.

According to a seventh embodiment of the present invention, there is provided a method of growing a nitride-based III-V compound semiconductor layer, the method including the steps of: providing a substrate having at least one notch portion on one main surface thereof, and growing a first nitride-based group III-V compound semiconductor layer by forming a state of a triangle having a bottom surface of the notch portion as a base in cross section, thereby burying the notch portion; and laterally growing a second nitride-based III-V group compound semiconductor layer from the first nitride-based III-V group compound semiconductor layer on the substrate.

This growth method of a nitride-based III-V group compound semiconductor layer can be applied not only to the manufacture of light emitting diodes and integrated light emitting diodes, but also to the manufacture of various semiconductor devices.

According to an eighth embodiment of the present invention, there is provided a substrate for growing a nitride-based III-V compound semiconductor, including: a substrate having at least one notch portion on one main surface thereof; and a sixth nitride-based III-V compound semiconductor layer grown on the substrate without forming a gap on the notch portion. On the substrate, in the sixth nitride-based III-V group compound semiconductor layer, a dislocation occurs from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the recess portion as a base, and is bent in a direction parallel to the one main surface.

According to a ninth embodiment of the present invention, there is provided a substrate for growing a nitride-based III-V compound semiconductor, including: a substrate having at least one notch portion on one main surface thereof; and a sixth nitride-based III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion. The substrate may form a first pit having a first width on a bottom surface of the recess portion, and a second pit having a second width larger than the first width on an opposite side of the recess portion.

According to a tenth embodiment of the present invention, there is provided a light source unit device including a printed circuit board and a plurality of cells (cells) formed on the printed circuitboard, each cell including at least one red light emitting diode, at least one green light emitting diode, and at least one blue light emitting diode. In the light source unit device, at least one of the red light emitting diode, the green light emitting diode, and the blue light emitting diode may include: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type grown on the sixth nitride-based group III-V compound semiconductor layer. In the sixth nitride-based III-V group compound semiconductor layer, a dislocation occurs from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the recess portion as a base, and bends in a direction parallel to the one main surface.

According to an eleventh embodiment of the present invention, there is provided a light emitting diode backlight device including a plurality of red light emitting diodes, a plurality of green light emitting diodes, and a plurality of blue light emitting diodes arranged in a pattern. Among the light emitting diodes, at least one of a red light emitting diode, a green light emitting diode, and a blue light emitting diode includes: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type formed on the sixth nitride-based group III-V compound semiconductor layer. In the sixth nitride-based III-V group compound semiconductor layer, a dislocation occurs from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the recess portion as a base, and bends in a direction parallel to the one main surface.

According to a twelfth embodiment of the present invention, there is provided a light emitting diode backlight device including red light emitting diodes, green light emitting diodes, and blue light emitting diodes arranged in a pattern, each of the diodes being plural in number, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes includes: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer, wherein the substrate forms a first pit having a first width on a bottom surface of the notch portion, and forms a second pit having a second width on an opposite side of the notch portion, the second width being greater than the first width.

According to a thirteenth embodiment of the present invention, there is provided a light emitting diode lighting device including red light emitting diodes, green light emitting diodes, and blue light emitting diodes arranged in a pattern, each of the diodes being plural in number, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes includes: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type formed on the sixth nitride-based group III-V compound semiconductor layer, wherein in the sixth nitride-based group III-V compound semiconductor layer, a dislocation occurs from an interface between the bottom surface of the notch portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the notch portion as a base, and is bent in a direction parallel to the one main surface.

According to a fourteenth embodiment of the present invention, there is provided a light emitting diode lighting device including red light emitting diodes, green light emitting diodes, and blue light emitting diodes arranged in a pattern, each of the diodes being plural in number, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes includes: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer, wherein the substrate forms a first pit having a first width on a bottom surface of the notch portion, and forms a second pit having a second width on an opposite side of the notch portion, the second width being greater than the first width.

According to a fifteenth embodiment of the present invention, there is provided a light emitting diode display including red light emitting diodes, green light emitting diodes, and blue light emitting diodes arranged in a pattern, each of the diodes being plural in number, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes includes: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type formed on the sixth nitride-based group III-V compound semiconductor layer, wherein in the sixth nitride-based group III-V compound semiconductor layer, a dislocation occurs from an interface between the bottom surface of the notch portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the notch portion as a base, and is bent in a direction parallel to the one main surface.

According to a sixteenth embodiment of the present invention, there is provided a light emitting diode display including red light emitting diodes, green light emitting diodes, and blue light emitting diodes arranged in a pattern, each of the diodes being plural in number, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes includes: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer, wherein the substrate forms a first pit having a first width on a bottom surface of the notch portion, and forms a second pit having a second width on an opposite side of the notch portion, the second width being greater than the first width.

In the tenth to sixteenth embodiments according to the present invention, for example, the red light emitting diode may be a light emitting diode using an AlGaInP semiconductor.

According to a seventeenth embodiment of the present invention, there is provided an electronic device including at least one light emitting diode, the at least one light emitting diode including: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having the second conductivity type formed on the sixth nitride-based group III-V compound semiconductor layer, wherein in the sixth nitride-based group III-V compound semiconductor layer, a dislocation occurs from an interface between the bottom surface of the notch portion in a direction perpendicular to the one main surface, reaches or approaches an inclined surface of a triangle having the bottom surface of the notch portion as a base, and is bent in a direction parallel to the one main surface.

Accordingto an eighteenth embodiment of the present invention, there is provided an electronic device including at least one light emitting diode, the at least one light emitting diode including: a substrate having at least one notch portion on one main surface thereof; a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the notch portion; and a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer, wherein the substrate forms a first pit having a first width on a bottom surface of the notch portion, and forms a second pit having a second width on an opposite side of the notch portion, the second width being greater than the first width.

In the seventeenth and eighteenth embodiments of the present invention, electronic apparatuses include projectors, rear projection televisions, Grating Light Valves (GLVs), and the like that use light emitting diodes as light sources, in addition to light emitting diode backlights (e.g., backlights for liquid crystal displays, and the like), light emitting diode illumination apparatuses, light emitting diode displays, and the like. In general, an electronic device may be of substantially any type, which may include portable and desktop devices, as long as the electronic device has at least one light emitting diode for display, illumination, optical communication, optical transmission, and the like. In addition to the above-described examples, specific examples include a mobile phone, a mobile device, a robot, a personal computer, a vehicle-mounted device, various home electronic products, a light emitting diode optical communication device, a light emitting diode optical transmission device, and the like. The electronic device further comprisesa combination of two or more types of light emitting diodes, which are capable of emitting light of different wavelengths over a wavelength range comprising a far infrared wavelength range, an infrared wavelength range, a red wavelength range, a yellow wavelength range, a green wavelength range, a blue wavelength range, a violet wavelength range, an ultraviolet wavelength range, etc. In particular, the light-emitting diode device has two or more light-emitting diodes capable of emitting visible light of different wavelength ranges, the wavelength range of the visible light being selected among a red wavelength range, a yellow wavelength range, a green wavelength range, a blue wavelength range and a violet wavelength range. Two or more kinds of light emitted from the light emitting diodes are mixed to obtain natural light or white light. Further, as the light source, a light emitting diode capable of emitting light having a wavelength in at least one of a blue wavelength range, a violet wavelength range, and an ultraviolet wavelength range is used, and the light emitted from the light emitting diode is irradiated to the phosphor, and the light obtained by excitation of the phosphor is mixed to obtain natural light or white light.

According to a nineteenth embodiment of the present invention, there is provided a method of manufacturing an electronic device, the method including the steps of: providing a substrate having at least one notch portion on one main surface; growing a first layer on the notch portion by forming a state of a triangle having a bottom surface of the notch portion as a base in cross section, and burying the notch portion; and laterally growing a second layer from the first nitride-based compound semiconductor layer on the substrate.

According to a twentieth embodiment of the present invention, there is provided an electronic device including: a substrate having at least one notch portion on one main surface; and a third layergrown on the substrate without forming a gap in the recess portion, wherein, in the third layer, a dislocation occurs from an interface with a bottom surface of the recess portion in a direction perpendicular to the one main surface, the dislocation reaches or approaches an inclined surface of a triangle having the bottom surface of the recess portion as a base, and is bent in a direction parallel to the one main surface.

In the nineteenth and twentieth embodiments of the present invention, the first to third layers may be other types of semiconductors having wurtzite (wurtzit) structure or more generally hexagonal crystal (hexagonal crystal) structure such as ZnO, α -ZnS, α -CdS, α -CdSe and the like and a plurality of semiconductors having other crystal structures, in addition to nitride-based III-V compound semiconductors, semiconductor devices using these semiconductors include light emitting devices such as ordinary light emitting diodes, intermediate sub-band transition (quantum cascade) light emitting diodes, ordinary semiconductor lasers, intermediate sub-band transition (quantum cascade) semiconductor diodes and the like, light receiving devices such as photodiodes, sensors, solar cells, electronic transition devices, typical electronic devices are transistors including Field Effect Transistors (FETs) such as high electron mobility transistors and bipolar transistors such as Heterojunction Bipolar Transistors (HBTs) which may be mounted on a single or a plurality of these devices, may be formed using the same or multiple integrated optical line communication devices, if necessary, may be formed using the same optical communication substrate or a plurality of light emitting devices.

In addition to these semiconductor devices (e.g., a light emitting device, a light receiving device, an electronic transition device, and the like), electronic devices include piezoelectric devices, thermoelectric devices, optical devices (e.g., a second harmonic generator using a nonlinear optical crystal, a dielectric device including a ferroelectric device), superconducting devices, and the like. In this connection, the materials of the first to third layers may include various semiconductors described above, particularly piezoelectric and thermoelectric devices, optical devices, dielectric devices, and superconducting devices, and various materials such as an oxide having a hexagonal crystal structure may be used.

When these electronic devices including a light emitting diode or a semiconductor laser are utilized, a light emitting diode backlight device, a light emitting diode lighting device, a light emitting diode display, a projector or a rear projection television using a light emitting diode or a semiconductor laser as a light source, and an electronic apparatus such as a grating light valve can be provided.

As for the nineteenth and twentieth embodiments of the present invention, these applications as in the first to eighteenth embodiments are also applicable to the nineteenth and twentieth embodiments.

As described above, according to the embodiments of the present invention, the first nitride-based III-V compound semiconductor layer starts to grow from the bottom of the notch portion of the substrate. During the growth, by forming a state of a triangle having the bottom face of the recess portion as a base on the cross section, the first nitride-based III-V group compound semiconductor layer is formed, thereby burying the recess portion, which layer does not form a gap at the recess portion. Thereafter, a second nitride-based group III-V compound semiconductor layer is laterally grown from above the first nitride-based group III-V compound semiconductor layer. At this stage, in the first nitride-based III-V group compound semiconductor layer, dislocations occur from the interface with the bottom surface ofthe recess portion of the substrate in the direction perpendicular to the one main surface of the substrate. The dislocations reach the inclined surface of the first nitride-based group III-V compound semiconductor layer or approach the inclined surface of the first nitride-based group III-V compound semiconductor layer, in which case the dislocations are bent in a direction parallel to the one main surface of the substrate when the second nitride-based group III-V compound semiconductor layer is grown. When the second nitride-based III-V group compound semiconductor layer is grown to a satisfactory thickness, a portion above the dislocation parallel to the one main surface of the substrate becomes a region where the dislocation density is very small. According to the method, the first to fourth nitride-based group III-V compound semiconductor layers may be grown using an epitaxial growth technique.

More generally, similar results can also be achieved when the first nitride-based group III-V compound semiconductor layer is used only as the first layer and the second nitride-based group III-V compound semiconductor layer is used only as the second layer.

According to the embodiments of the present invention, the light extraction efficiency can be significantly improved without forming a space or a gap between the first nitride-based III-V group compound semiconductor layer and the second nitride-based III-V group compound semiconductor layer and the substrate. Since the crystallinity of the second nitride-based group III-V compound semiconductor layer becomes good, the crystallinity of the third nitride-based group III-V compound semiconductor layer, the active layer, and the fourth nitride-based group III-V compound semiconductor layer grown on the second layer can be significantly improved. Finally, a light emitting diode having very high light emission efficiency is obtained. In addition, since the light emitting diode can be formed by one epitaxy, the manufacturing cost is low. Therefore, it is possible to realize the manufacture of a high-performance light source unit device, a light emitting diode backlight device, a light emitting diode lighting apparatus, and a light emitting diode display, and various types of electronic apparatuses using light emitting diodes having high light emission efficiency.

More generally, similar results can be achieved when a first nitride-based group III-V compound semiconductor layer is used as the first layer and a second nitride-based group III-V compound semiconductor layer is used as the second layer.

The above and other features and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, which illustrate, by way of example, preferred embodiments of the invention.

Drawings

Fig. 1A to 1F are sectional views illustrating a method of manufacturing a GaN light emitting diode according to a first embodiment of the present invention, respectively.

Fig. 2 is a plan view showing an example of forming planar shapes of a notch portion and a projection portion on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 3 is a schematic diagram showing how light is extracted from a GaN light emitting diode obtained according to the first embodiment of the present invention.

Fig. 4 is a schematic view showing a sapphire substrate used in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 5 is a schematic view showing how a GaN layer is grown on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 6 is a schematic view showing the distribution of crystal defects in GaN grown on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 7 is a photograph showing a planar cathodoluminescence image of a GaN layer grown on a sapphire substrate in the method of fabricating a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 8A and 8B are schematic views respectively illustrating dislocation behaviors obtained by TEM observation of a GaN layer grown on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 9 is a diagram illustrating the result of estimating the dislocation density in a GaN layer grown on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 10A and 10B are micrographs respectively showing sectional TEM observation results of an interface of a GaN layer grown on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 11 is a schematic view illustrating the formation of pits when a GaN layer is grown on a sapphire substrate in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 12A to 12C are micrographs respectively showing sectional TEM observation results of interfaces of GaN layers grown on a sapphire substrate in the method ofmanufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 13A and 13B are schematic views illustrating thickness distributions of the GaN layer in fig. 12B and 12C, respectively.

Fig. 14 is a diagram showing a result of a tracking simulation for manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 15 is a schematic diagram illustrating an optimized condition for improving light extraction efficiency of a GaN light emitting diode manufactured according to the first embodiment of the present invention.

Fig. 16 is a graph showing the result of simulation of the area ratio of the inclined surface of the sapphire substrate used in the GaN light emitting diode manufactured according to the first embodiment of the present invention.

Fig. 17 is a graph showing a simulation result of an area ratio of an inclined surface of a sapphire substrate used in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 18 is a graph showing a simulation result of an area ratio of an inclined surface of a sapphire substrate used in the method of manufacturing a GaN light emitting diode according to the first embodiment of the present invention.

Fig. 19 is a schematic view illustrating the surface flatness of the active layer of the GaN light emitting diode manufactured according to the first embodiment of the present invention.

Fig. 20 is a schematic view illustrating the surface flatness of the active layer of the GaN light emitting diode manufactured according to the first embodiment of the present invention.

Fig. 21A to 21E are sectionalviews respectively illustrating a method of manufacturing a GaN light emitting diode according to a second embodiment of the present invention.

Fig. 22A to 22G are sectional views respectively illustrating a method of manufacturing a GaN light emitting diode according to a third embodiment of the present invention.

Fig. 23A to 23F are sectional views each illustrating a method of manufacturing a GaN light emitting diode according to a fourth embodiment of the present invention.

Fig. 24A to 24G are sectional views each illustrating a method of manufacturing a GaN light emitting diode according to a fifth embodiment of the present invention.

Fig. 25A to 25G are sectional views each illustrating a method of manufacturing a GaN light emitting diode according to a sixth embodiment of the present invention.

Fig. 26A to 26B are sectional views respectively illustrating a method of manufacturing a GaN light emitting diode according to a seventh embodiment of the present invention.

Fig. 27A to 27J are sectional views respectively illustrating a method of manufacturing a GaN light emitting diode according to an eighth embodiment of the present invention.

Fig. 28A to 28C are sectional views respectively illustrating a method of manufacturing a GaN light emitting diode backlight according to a ninth embodiment of the present invention.

Fig. 29A and 29B are perspective views respectively illustrating a method according to a ninth embodiment of the present invention.

Fig. 30 is a perspective view illustrating a method of manufacturing a light emitting diode backlight device according to a tenth embodiment of the present invention.

Fig. 31 is a perspective view illustrating a method of manufacturing an integrated light emitting diode according to an eleventh embodiment of the present invention.

Fig. 32 is a cross-sectional view showing an integrated light emitting diode manufactured according to an eleventh embodiment of the present invention and mounted on a submount (submount).

Fig. 33A and 33B are a plan view showing a light source unit device according to a twelfth embodiment of the present invention and an enlarged view of a unit of the light source unit device, respectively.

Fig. 34A and 34B are respectively plan views showing specific examples of a light source unit device according to a twelfth embodiment of the present invention.

Fig. 35 is a plan view showing an example of arrangement of another unit of the light source unit device according to the twelfth embodiment of the present invention.

Fig. 36A to 36C are sectional views respectively illustrating a related method of growing a GaN semiconductor layer on a dentate substrate.

Fig. 37 is a sectional view illustrating a problem of the related method shown in fig. 36.

Fig. 38A to 38D are sectional views each illustrating another related method of growing a GaN semiconductor layer on a dentate substrate.

Fig. 39A to 39F are sectional views each illustrating another related method of growing a GaN semiconductor substrate on a dentate substrate.

Detailed Description

Embodiments of the present invention are described below with reference to the drawings. Note that like reference numerals in the drawings denote like parts.

Fig. 1A to 1F show a method of manufacturing a GaN light emitting diode according to a first embodiment of the present invention in order of steps.

In the first embodiment, as shown in fig. 1A, a sapphire substrate 11 having a tooth-like pattern on one main surface thereof is provided. Reference numeral 11a denotes a notch portion or a groove, and reference numeral 11b denotes a protrusion portion or a protrusion. In this case, the notch portion 11a has an inverted trapezoidal cross section. For example, the main surface of the sapphire substrate 11 is a c-plane, and the notch portion 11a is a stripe shape extending along the<1-100>direction of the sapphire substrate 11. Although the planar shapes of the notch portion 11a and the projection portion 11b may be the shapes respectively listed above, a preferred example is shown in fig. 2. In this case, as shown in fig. 2, each of the projecting portions 11b is hexagonal in plane, and these projecting portions are shaped into a two-dimensional shape, forming a honeycomb shape. The notch portions 11a are formed around the respective protrusions 11 b. The hexagonal protrusion 11b has a distance between opposite sides of the hexagon, for example, 3.8 to 4.2 μm, preferably 4 μm. The distance between the adjacent hexagonal protrusions 11b is set, for example, to 1.3 to 1.7 μm, preferably 1.5 μm, but is not limited thereto. Typically, the direction of the dotted line (i.e., the direction of the center connection line of the most adjacent protruding portion 11 b) is parallel to the m-axis of the GaN layer to be described later. The surface serration of the sapphire substrate 11 can be achieved according to a number of methods including a Reactive Ion Etching (RIE) method, a powder spraying technique, a sand blasting technique, and the like. The dimensions of these notch portions 11a and protrusion portions 11b will be described in detail below.

Then, the surface of the sapphire substrate 11 is cleaned by a method such as thermal cleaning, and then a GaN buffer layer (not shown) is grown, for example, on the sapphire substrate 11 at a growth temperature, for example, about 550 ℃, according to a known procedure. Next, GaN is epitaxially grown using a method such as MOCVD. At this stage, as shown in fig. 1B, this growth is started from the bottom surface of the notch portion 11a, and the GaN layer 12 is grown in such a manner as to form an isosceles triangle in cross section, with the bottom as the base and the surface inclined with respect to the main surface of the sapphire substrate 11 as the inclined side surface. For example, the GaN layer 12 extends in the<1-100>direction, and the inclined side faces or surfaces thereof are (1-101) faces. This GaN layer 12 may be undoped or doped with n-type or p-type impurities. The growth conditions of the GaN layer 12 will be described below.

Next, the growth of the GaN layer 12 is continued while always maintaining the surface direction of the inclined face, and the notch portion 11a is filled therein entirely, as shown in fig. 1C. In fig. 1C, the dotted line indicates a growth interface during growth (the same applies hereinafter).

Then, when the growth is continued while setting the condition in which the lateral growth is dominant, the GaN layer 12 is distributed over the protruding portions 11b while its thickness is increased, as shown in fig. 1D. Finally, the GaN layers 12 grown from the adjacent notch portions 11a contact each other above the protrusion portions 11 b.

Thereafter, as shown in fig. 1E, GaN layer 12 is laterally grown so that the surface of GaN layer 12 forms a flat surface parallel to the main surface of sapphire substrate 11. The GaN layer 12 thus grown has a very low dislocation density above the notch part 11 a.

Next, as shown in fig. 1F, for example, an n-type GaInN layer 13, an n-type GaN layer 14, an n-type GaInN layer 15, an active layer 16, a p-type GaInN layer 17, a p-type AlInN layer 18, a p-type GaN layer 19, and a p-type GaInN layer 20 are epitaxially grown in this order on the GaN layer 12. The active layer 16 has, for example, a GaInN-based Multilayer Quantum Well (MQW) structure (for example, GaInN quantum well layers and GaN barrier layers are alternately stacked). The In composition of the active layer 16 is selected based on the emission wavelength of the light emitting diode, e.g., approximately 11% at 405nm emission wavelength (up to), approximately 18% at 450nm wavelength, and approximately 24% at 520nm wavelength.

Thereafter, in order to activate the p-type impurities in the p-type GaInN layer 17, the p-type AlInN layer 18, the p-type GaN layer 19, and the p-type GaInN layer 20, heat treatment is performed in a mixed gas atmosphere, which is, for example, N at a temperature of 550 to 750 ℃ (e.g., 650 ℃) or 580 to 620 ℃ (e.g., 600 ℃), for example₂And O₂(component e.g. 99% N₂And 1% of O₂). At O₂And N₂Upon mixing, this activation occurs more readily. The time period of the heat treatment ranges, for example, from five minutes to two hours, or 40 minutes to two hours. Typically, this time is in the range of 10 to 60 minutes. The reason why the temperature of the heat treatment is suppressed to a relatively low value is to prevent the active layer 16 from deteriorating during the heat treatment.

Starting materials for growing the GaN semiconductor layer include, for example, triethylgallium ((C) as a Ga material₂H₅)₃Ga, TEG) or trimethylgallium ((CH)₃)₃Ga, TMG) as Al materialTrimethylaluminum ((CH)₃)₃Al, TMA), trimethylindium ((CH) as an In material₃)₃In, TMI) and ammonium (NH) as N material₃). Dopants include, for example, Silane (SiH) as an n-type dopant₄) And bis (methylcyclopentadienyl) magnesium (CH) magnesium (magnesium) magnesium as a p-type dopant₃C₅H₄)₂Mg), bis (ethylcyclopentadienyl) magnesium (bis (ethylcyclopentadienyls) magnesium (C)₂H₅C₅H₄)₂Mg) or bis (cyclopentadienyl) magnesium (bis (cyclopentadienyl) magnesium, (C)₅H₅)₂Mg)。

As a carrier gas for growing the GaN semiconductor layer, for example, H can be used₂。

Next, the sapphire substrate 11, on which a GaN semiconductor substrate has been formed in the manner described previously, is removed from the MOCVD apparatus.

After that, a p-side electrode 21 is formed on the p-type GaInN layer 20. The material for the p-side electrode 21 is composed of an ohmic metal having high reflectance, and is preferably Ag or Pd/Ag. Note that the p-side electrode 21 may be formed after the epitaxial growth of the n-type GaInN layer 13, the n-type GaN layer 14, the n-type GaInN layer 15, the active layer 16, the p-type GaInN layer 17, the p-type AlInN layer 18, the p-type GaN layer 19, and the p-type GaInN layer 20, but earlier than the heat treatment for activating the p-type impurities in the p-type GaInN layer 17, the p-type AlInN layer 18, the p-type GaN layer 19, and the p-type GaInN layer 20.

Next, the n-type GaN layer 14, the n-type GaInN layer 15, the active layer 16, the p-type GaInN layer 17, the p-type AlInN layer 18, the p-type GaN layer 19, and the p-type GaInN layer 20 are patterned in a desired form, for example, according to an RIE method, a powder spraying method, a sand blasting method, or the like, thereby forming the mesa portion 22.

Then, an n-side electrode 23 is formed on the n-type GaInN layer 13 at a portion adjacent to the mesa portion 22. The n-side electrode 23 is an electrode having a structure of, for example, Ti/Pt/Au.

Next, if necessary, the sapphire substrate 11 on which the light emitting diode structure as described above has been formed may be cut or ground from the back side thereof to reduce the thickness thereof, followed by scribing the sapphire substrate 11 and forming a bar. The strip is then scribed into chips.

In the resultant GaN light emitting diode, as shown in fig. 3, light emission is performed by applying a forward voltage between the p-side electrode 21 and the n-side electrode 23 to pass a current therebetween, and the light is extracted to the outside through the sapphire substrate 11. In fig. 3, light is emitted toward the upper side as shown, and thus the sapphire substrate 11 is disposed uppermost. The proper selection of the In composition of the active layer 16 ensures that red to ultraviolet light, particularly blue, green or red light, is emitted. In this connection, the light component generated by the active layer 16 toward the sapphire substrate 11 is refracted at the interface between the sapphire substrate 11 and the GaN layer 12 in the notch portion 11a, and then emitted to the outside through the sapphire substrate 11. On the other hand, the light component generated by the active layer 16 toward the p-side electrode 21 is reflected at the p-side electrode 21, and goes toward the sapphire substrate 11, passing through the sapphire substrate 11, and goes to the outside. Note that the light shown in fig. 3 is light in the case where the refractive index of the GaN semiconductor layer constituting the light emitting diode is 2.438, the refractive index of the sapphire substrate 11 is 1.785, and the refractive index of air is 1.

In the first embodiment, in order to minimize the threading dislocation density of the GaN layer 12, the width W of the notch portion 11a_gThe depth d, the angle αbetween the inclined surface of the GaN layer 12 in the state shown in FIG. 1B and the main surface of the sapphire substrate 11 satisfy the following inequality (see FIG. 4)

2d≥W_gtanα

For example, when W_gWhen the angle is 2.1 μm and α is 59 degrees, d is 1.75 μm or more, and W is the same as above_gWhen the angle is 2 μm and α is 59 degrees, d is not less than 1.66 μm, and W is_g1.5 μm, when α is 59 degrees, d is more than or equal to 1.245 μm, in W_gWhen the angle is 59 degrees at α ≧ 1.2 μm, d is 0.966 μm, and in any case, d<5 μm is preferred.

A stage of growing the GaN layer 12 in the steps shown in FIGS. 1B and 1C, forThe ratio between the starting materials V/III of the growth is set to a higher value, for example in the range 13000+2000, and the growth temperature is set to a lower value, for example 1050 ± 50 ℃. This ensures growth of the GaN layer 12 for completely masking the notch portion 11a while allowing a face inclined with respect to the main surface of the substrate 11 to appear on the inclined surface, as shown in fig. 1B and 1C. Under such conditions, the GaN layer 12 is hardly grown on the protruding portion 11 b. The growth of the GaN layer 12 is performed, for example, at 1.0 to 2.0 atmospheres, preferably at about 1.6 atmospheres. This allows lateral growth to be suppressed and growth of the GaN layer to occur in the notch portion 11a to be easily selected. The growth rate generally ranges from 1.0 to 5.0. mu.m/hr, preferably about 3.0. mu.m/hr. Flow rate of the primary gas, e.g. TMG 20SCCM, NH ₃20 SLM. On the other hand, the growth (lateral growth) of the GaN layer 12 in the steps shown in fig. 1D and 1E is performed in the following manner: the ratio between the starting materials V/III is set to a low value, for example in the range 5000. + -. 2000, and the growth temperature is set to a high value, for example in the range 1150. + -. 50 ℃. If the growth temperature is higher than the above range, the obtained GaN layer 12 easily becomes rough on its surface. On the other hand, if the temperature is low, pits are likely to occur at the positions where the GaN layers 12 are connected to each other. The flow rate of the primary gas is, for example, 40SCCM, NH ₃20 SLM. In this way, the GaN layer 12 grows laterally as shown in fig. 1D and 1E to obtain a flat surface. No gap or void occurs between the GaN layer 12 and the sapphire substrate 11.

Fig. 5 schematically shows how the initial gas flows during the growth of the GaN layer 12 and diffuses over the sapphire substrate 11. The most important of this growth process is: the GaN layer 12 is not grown at the protruding portions 11b (step portions) of the sapphire substrate 11 at the initial stage of growth, but the GaN layer 12 starts to grow on the notch portions 11 a. The reason for this is considered as follows. In general,when TMG is used as the starting material for Ga and NH₃When used as starting material for N, by NH₃And Ga, the reaction represented by the following equation:

during the reaction, H is produced₂A gas. This H₂The gas has an adverse effect on crystal growth, i.e. etching. In the steps shown in fig. 1B and 1C, in the related art, the growth at the protruding portion 11B is suppressed using a condition that the GaN growth is not performed on the flat substrate used, that is, a condition that enhances the etching action, growth is not easily generated (a condition that increases the V/III value). In this connection, such etching action is relieved in the notch portion 11a, and thus crystal growth is generated. In order to improve the surface flatness of the growing crystal, in the related art, the crystal is generally grown under conditions of increasing the degree of lateral growth (or at higher temperatures). According to the first embodiment, in order to reduce the number of threading dislocations by bending the threading dislocations in a direction parallel to the main surface of the sapphire substrate 11 and burying the notch portions 11a with the GaN layer 12 at an early stage, growth is performed at a temperature lower than that mentioned in the above related art (e.g., 1050 ± 50 ℃).

Fig. 6 schematically shows the crystal defect distribution result of the GaN layer 12 determined by a Transmission Electron Microscope (TEM). Fig. 7 shows a planar Cathodoluminescence (CL) image of the surface of the GaN layer 12. As can be seen from fig. 6, although the dislocation density becomes high at the mutually associated portions of the GaN layer 12 grown from the adjacent notch portions 11a, the dislocation density becomes low at other portions including the portion above the notch portions 11 a. For example, the depth d of the recess portion is 1 μm, and the width W of the bottom surface _g2 μm, upper surface width W of the protruding portion 11b_tIn the case of 2 μm, the dislocation density is 1 × 10 at this low dislocation density portion⁷/cm². Therefore, the dislocation density is reduced by one or two orders of magnitude as compared with the case of using the sapphire substrate 11 without surface-serration. Can also seeOut, in the direction perpendicular to the side wall of the notch portion 11a, no dislocation occurs. The planar cathodoluminescence diagram shown in fig. 7 corresponds very well to the results in fig. 6.

In fig. 6, the average thickness of the region wherethe dislocation density of GaN layer 12 in contact with sapphire substrate 11 at notch portion 11a is high and the crystallinity is poor is 1.5 times the average thickness of the region where the dislocation density of GaN layer 12 in contact with sapphire substrate 11 at protrusion portion 11b is high and the crystallinity is poor. This result reflects the lateral growth of the GaN layer 12 on the protruding portion 11 b.

Fig. 8A and 8B schematically show dislocation behavior during growth of the GaN layer 12, as found in the TEM analysis results. Fig. 8A is a sectional view, and fig. 8B is a plan view corresponding to the sectional view shown in fig. 8A. In general, dislocations can be divided into two categories.

The first type of dislocation ((a + c) dislocation type) is shown below. In fig. 8A and 8B, dislocations (1) are generated from the interface with the bottom of the notch portion 11a, and the dislocations (1) are bent in the horizontal direction (i.e., in the direction parallel to the main surface of the sapphire substrate 11) on the plane (a) of the hypotenuse of the isosceles triangle using the bottom as the base. The dislocations (1) continue to extend to the side walls of the notch portion 11a and disappear there. Dislocations (2) occur from the interface with the bottom of the notch portion 11a, bend in the horizontal direction at the surface (a), and extend to the vicinity of the center of the protrusion portion 11 b. Then, the dislocations (2) are bent upward (in a direction perpendicular to the main surface of the sapphire substrate 11) at the surface (c) associated with the center of the protruding portion 11b, and then rise in the perpendicular direction at the associated portion, thereby forming threading dislocations at the center of the protruding portion 11 b. This (a + c) -type threading dislocation has a Burger vector of 1/3<11-23>and is concentrated at the center of the projecting portion 11 a.

The second type of dislocation (a-type dislocation) is explained below. As shown in fig. 8A and 8B, dislocations (3) occur from the interface with the bottom of the notch portion 11a, are bent in the horizontal direction in the vicinity of the plane (d), then continue to the side wall of the notch portion 11a, and finally disappear. Note that: the bending in the horizontal direction does not necessarily occur at the plane (d). Similar to the mechanism of the dislocations (3), the dislocations (4) are bent in the horizontal direction, extend to the vicinity of the center of the protruding portion 11b, and rise in the vertical direction at the central associated portion of the protruding portion 11b, thereby forming threading dislocations at the center of the protruding portion 11 b. The difference with the dislocations (2) is the extension in the horizontal direction. Similar to the mechanism of the dislocations (3), the dislocations (5) are bent in the horizontal direction and extend to the vicinity of the center of the protruding portion 11b, where they extend along the normal (indirecty) direction. The dislocations (5) cause threading dislocations at the center of the protruding portions 11 b. This type a threading dislocation has a Bergess vector of 1/3<11-20>.

In addition to the (a + c) type dislocation and the a type dislocation, newly generated threading dislocations (both of the (a + c) type dislocation and the a type dislocation) on the surface of the GaN layer 12 were observed at the associated portion at the center of the projected portion 11 b.

As shown in fig. 9, the angle between the side wall of the notched portion 11a and the main surface of the sapphire substrate 11 is represented by γ, the angle between the connecting surface grown on the protruding portion 11b and the main surface of the sapphire substrate 11 is represented by β, and the ratio of high-density defect regionson the GaN layer 12 is represented as follows:

R＝cotβ((W_g/2)tanα-d)/(1/2)(W_t+W_g+dcotγ)

in this case, the dislocation density was estimated to be W_initialX (R + U (1-R)), where U represents the frequency of a-type dislocations (c-dislocations) promoted onto the surface of GaN layer 12 and is empirically about1/10 to 1/100. for example, when α and β approach 59 degrees, γ approaches 67 degrees, W_gWhen it is close to 2.1. mu.m, Wt is close to 2 μm, and d is close to 1 μm, R is close to 0.195, so that W_initialApproximately 3 x 10⁸/cm². When the U is connected to 1/50, the dislocation density is close to 6.3X 10⁷/cm²。

In fig. 10A and 10B, cross-sectional TEM photographs near the interface between the sapphire substrate 11 and the GaN layer 12 are shown. Fig. 11 shows a cross-sectional view of the vicinity. FIG. 10A corresponds to the area surrounded by the dotted line on the protruding portion 11B shown in FIG. 11, and FIG. 10B corresponds to the area surrounded by the dotted line on the recessed portion 11a shown in FIG. 11The area around which the wire is wound. As shown in fig. 10A and 10B, on the interface between the sapphire substrate 11 and the GaN layer 12, the pit shape viewed on the sapphire substrate 11 side is different between the notched portion 11a and the protruding portion 11B. As shown particularly in FIG. 11, when the width P of the concave point 13 formed in the notch portion 11a is used_gThe width P of the concave point 14 formed on the protruding part 11b is shown_tWhen it is expressed, P_t＞P_gTypical of P_t＞1.2P_g. The width P of the pits 14 formed on the protruding portion 11b_tIs larger than the width P of the concave point 13 formed in the concave portion 11a_gThereason for this is that: the GaN layer 12 is not grown on the protruding portions 11b at the initial stage of growth, so that the protruding portions 11b are exposed to NH having an etching action₃For a long time. In the related art method, this situation does not occur.

Fig. 12A shows a cross-sectional TEM photograph (dark field image) of the region near the notch portion 11a and the protrusion portion 11B of the sapphire substrate 11, fig. 12B is an enlarged cross-sectional TEM photograph of the region near the upper surface of the protrusion portion 11B shown in fig. 12A, and fig. 12C is an enlarged view of the region near the bottom surface of the notch portion 11a shown in fig. 12B, in which the black portion in each drawing represents the sapphire substrate 11. Fig. 13A schematically shows a cross section of the region near the upper surface of the protruding portion 11B shown in fig. 12B, and the thickness of the portion of the GaN layer 12 above the protruding portion 11B where the crystallinity is poor is close to 37 nm. Fig. 13B schematically shows a cross section of the region near the bottom surface of the notch portion 11a shown in fig. 12C, and the thickness of the portion of the GaN layer 12 above the notch portion 11a where crystallinity is poor is in the range of approximately 18nm to 56 nm. As seen from the above, the thicknesses of the regions of the GaN layer 12 on the notch parts 11a and the protrusion parts 11b, which are poor in crystallinity, are different from each other. This is because the GaN layer 12 grows laterally over the protruding portion 11 b. In the related-art method, no significant difference was shown.

In fig. 14, an example is shown, which is a result of simulation (data is represented by ■) of extracted light from a GaN light emitting diode (green light emitting diode) to the outside (tracking simulation), in fig. 14,assuming that a size range of 20 μm × 20 μm is taken on the sapphire substrate 11, the abscissa represents the area S of the inclined surface at the side wall of the notch portion 11a and also represents the area S with respect to 400 μm²The ordinate represents the light extraction efficiency η. as seen from fig. 14, the face S of the inclined face is increased to as large an extent as possible in order to improve the efficiency η of light extraction, in fig. 14, the notched portion 11a is shown in three directions (for example, three crystallographically equivalent to each other)<1-100>Direction) are formed at 60 degree intervals on the sapphire substrate 11, the planar shape of the projecting portion 11a is formed in a triangular shape in this case, the result shows that the light extraction efficiency η is larger in the case where the notch portions 11a are formed at 60 degree intervals in three directions than in the case where the notch portions 11a are formed extending in a stripe form in one direction.

Referring to fig. 15, consideration is again given to maximizing the area S of the inclined surface to improve the light extraction efficiency η assuming that the area occupied by the notch portion 11a and the protrusion portion 11b of the sapphire substrate 11 is used (W) over one period for the unit length portion in the extending direction of the notch portion 11a in fig. 15_t+W_g) + d/tan γ represents, and the area of the side wall inclined surface represents d/sin γ, therefore, in order to improve the light extraction efficiency η, the ratio of the area of the inclined surface (d/sin γ)/((W)_t+W_g) + d/tan γ) is effective.

Fig. 16 shows the assumption that d is 1 μm and W_t+W_gWhen the angle γ between the side wall of the notch portion 11a and the main surface of the sapphire substrate 11 is changed 4 μm, the change in the inclined surface area ratio (data indicated by a thick solid line). In fig. 16, data indicated by a thin solid line indicates a differential value of the inclined surface area ratio. In fig. 16, when γ is 69 degrees, the inclined surface area ratio is 0.24.

Fig. 17 shows that γ is 67 degrees, W_t+W_gWhen the depth d of the notch portion 11a is changed 4 μm, the inclined surface area ratio (data shown by a thick solid line) is changed. In fig. 17, data indicated by a thin solid line indicates a differential value of the area ratio of the inclined surface.As shown in fig. 17, the dislocation density in GaN layer 12 is low (e.g., d 1.66 μm, α 59 degrees, W)_g2 μm) was 0.24. Conversely, for example, when d is 1 μm, the inclined surface area ratio is 0.18.

Fig. 18 shows that γ is 67 degrees, W_t+W_gWhen the depth d of the notch portion 11a of 7 μm was changed, the inclined surface area ratio (data shown by a thick solid line) was changed, in fig. 18, data shown by a thin solid line indicates a differential value of the inclined surface area ratio, and in fig. 18, the dislocation density in the GaN layer 12 was decreased (for example, d was 1.66 μm, α was 59 degrees, and W was W ═ was_g2 μm) was 0.18. Conversely, for example, when d is 1 μm, the inclined surface area ratio is 0.12.

Next, a case of a growth surface in the vicinity of the active layer 16 is considered. In general, when the growth layer has a penetration defect, growth pits are generated, thereby causing deterioration in the flatness of the growth surface, as shown in fig. 19. Higher threading dislocation density leads to an increase in the degree of deterioration. If threading dislocations are present in the active layer 16, the composition and thickness inside the plane fluctuate, causing in-plane emission wavelength non-uniformity and occurrence of planar crystal defects such as anti-phase boundary defects (anti-phase boundary defects), thus causing a decrease in emission efficiency (i.e., decreased internal quantum efficiency). On the other hand, according to the first embodiment of the present invention, the threading dislocation density on the GaN layer 12 can be significantly reduced as mentioned above, and thus, the threading dislocation density of the active layer 16 grown thereon can be also low. Therefore, the reduction in emission efficiency due to threading dislocation is very small, and higher emission efficiency than in the related art is obtained.

Threading dislocations of the GaN layer 12 are concentrated near the center of the protruding portions 11b of the sapphire substrate 11 and are regularly arranged according to the array of the protruding portions 11 b. Accordingly, the threading dislocations of the active layer 16 are regularly aligned accordingly. Thus, the area of the active layer 16 portion is significantly increased in the region where the flat face is formed, as compared with the case where threading dislocations are randomly arranged, and thus the emission efficiency is improved.

Further, for example, where the In composition is high and the growth surface is rough In the active layer 16, new crystal defects at which planar crystal defects such as reverse interface defects and dislocation bonding occur easily, resulting In a decrease In emission efficiency. In contrast, according to the first embodiment, as described above, the flatness of the surface of the active layer is significantly improved, so that the occurrence of crystal defects is suppressed, and the reduction in emission efficiency does not occur.

In order to improve the flatness of the growth surface of the active layer 16 and reduce the number of crystal defects, it is effective to form the barrier layer of the active layer 16 from AlGaN.

As described above, according to the first embodiment, no gap isformed between the sapphire substrate 11 and the GaN layer 12, and a decrease in light extraction efficiency due to the gap can be prevented. Threading dislocations in the GaN layer 12 are concentrated near the center of the protruding portion 11b of the sapphire substrate 11, while the dislocation density of the other portions is as small as about 10⁷/cm²Thus, the dislocation density is significantly reduced compared to the related art using a substrate subjected to patterned notching. Thus, the crystallinity of the GaN semiconductor layers such as the GaN layer 12 and the active layer 16 grown thereon is significantly improved, thereby greatly reducing the number of non-emission centers. Thus, a GaN light emitting diode having high emission efficiency can be obtained. Further, one cycle of epitaxial growth is sufficient for manufacturing a GaN light emitting diode and a growth mask is not required, so that the manufacturing process becomes simple and the GaN light emitting diode can be manufactured at low cost.

Next, we will describe a second embodiment of the present invention.

In the second embodiment, as shown in fig. 21A, ion implantation is performed from the entire surface of a flat sapphire substrate 11, thereby amorphizing the surface layer of the sapphire substrate 11, thereby forming an amorphous layer 31. The atoms, energy, and dose used for ion implantation are selected to be sufficient to amorphize the sapphire substrate 11. For example, the atoms used for ion implantation include inert atoms such as He, Ne, Ar, Kr, Xe, etc., and Si, H, N, Ga, etc. For example, if Si is used as the ionThe number of atoms to be implanted is,the energy range for ion implantation is 10-30 kilo electron volts (KeV), and its dose is 1 × 10¹⁸/cm²Or a combination of the above.

Next, as shown in fig. 21B, the sapphire substrate 11 formed with the amorphous layer 31 is subjected to pattern notching to form a notch portion 11a and a protrusion portion 11B, similarly to the first embodiment.

Then, as shown in fig. 21C to 21E, a GaN layer 12 is grown on the sapphire substrate 11, similarly to the first embodiment, in which an amorphous layer 31 has been formed on the projecting portions 11 b.

Next, a step of growing the n-type GaInN layer 13 and subsequent steps are performed to provide a GaN light emitting diode similar to the first embodiment.

According to the second embodiment, advantages similar to those of the first embodiment can be obtained.

A third embodiment of the present invention will now be described.

In the third embodiment, as shown in fig. 22A and 22B, a GaN layer 32 is epitaxially grown on a sapphire substrate on which patterning notching has occurred, similarly to the first embodiment.

Next, as shown in fig. 22C, the GaN layer 32 is etched back by RIE, leaving a thin GaN layer 32 only at the bottom of the notch portion 11a of the sapphire substrate 11.

Thereafter, as shown in fig. 22D, ion implantation is performed on the entire surface of the sapphire substrate 11, thereby amorphizing the surface layer of the protruding portions 11b of the sapphire substrate 11 to form an amorphous layer 31. At the same time, the GaN layer 32 is also amorphized. The atoms, energy, and dose used for ion implantation are selected to be sufficient to amorphize GaN layer 32. For example, the atoms used for ion implantation include inert atoms such as He, Ne, Ar, Kr, Xe, etc., and Si, H, N, Ga, etc. For example, if Si is used as the ion-implanted atoms, the energy for ion implantation is in the range of 10 to 30 kilo electron volts (KeV) and the dose is 1X 10¹⁸/cm²Or a combination of the above.

Next, as shown in fig. 22E to 22G, similarly to the first embodiment, a GaN layer 12 is grown on the sapphire substrate 11; here, as described above, the amorphous layer 31 has been formed on the protruding portion 11b and the amorphous GaN layer 32 has been formed on the bottom of the recess portion 11 a. Note that: during heating to the growth temperature of the GaN layer 12, the amorphous GaN layer 32 crystallizes.

Next, a step of growing an n-type GaInN layer and subsequent steps are performed to provide a GaN light emitting diode, similarly to the first embodiment.

According to the third embodiment, advantages similar to those of the first embodiment can be obtained.

A fourth embodiment of the present invention is described.

In the fourth embodiment, the SiN film 33 is formed as an amorphous layer on the entire surface of the flat sapphire substrate 11, for example, using a vacuum deposition method, a sputtering method, a Chemical Vapor Deposition (CVD), or the like, as shown in fig. 23A. This SiN film 33 is, for example, 1nm or more in thickness.

Next, as shown in fig. 23B, the sapphire substrate 11 having the SiN film 33 formed thereon is patterned to be scored, for example, using an RIE method, a powder blast method, a sand blast method, or the like, to form the notch portions 11a and the protrusion portions 11B, as in the first embodiment.

Next, as shown in fig. 23C, the GaN layer 34 is grown at a low temperature of, for example, about 550 ℃. For example, the thickness of the GaN layer 34 is 200nm or less than 200 nm. The GaN layer 34 is grown on the bottom of each notch portion 11a of the sapphire substrate 11, and on the SiN film 33, respectively, wherein the SiN film 33 is formed on each protrusion portion 11 b.

Next, as shown in fig. 23D to 23F, similarly to the first embodiment, a GaN layer 12 is grown on the sapphire substrate 11; wherein the SiN film 33 has been formed on the protrusion portion 11b of the sapphire substrate and the GaN layer 34 has been formed on the bottom of the notch portion 11 a. During heating to the growth temperature of the GaN layer 12, the GaN layer 34 crystallizes. Thus growing the GaN layer 12 on the crystallized GaN layer 34; on the other hand, during heating to the growth temperature, the GaN layer 34 on the SiN film 33 evaporates.

Next, a step of growing the n-type GaInN layer 13 and subsequent steps are performed to provide a GaN light emitting diode, similarly to the first embodiment.

According to the fourth embodiment, advantages similar to those of the first embodiment can be obtained.

A fifth embodiment of the present invention is described.

In the fifth embodiment, as shown in fig. 24A, a SiN film 35, SiO film, etc. are sequentially formed on the entire surface of a flat sapphire substrate 11 by, for example, a vacuum deposition method, a sputtering method, Chemical Vapor Deposition (CVD), etc₂ Film 36, and SiN film 37. For example, the thickness of the SiN films 35, 37 is 1nm or more, SiO₂The thickness of the film 36 is 10nm or more.

Next, as shown in FIG. 24B, for example, by RIE, powder spraying, sandblasting, or the like, SiN film 35 and SiO are already formed₂The sapphire substrate 11 of the film 36 and the SiN film 37 is patterned to be scored to form the notch portion 11a and the protrusion portion 11b, similarly to the first embodiment.

As shown in FIG. 24C, the wet etching is performed only on SiO, for example, using a hydrofluoric acid based etchant₂The film 36 is etched, and after etching, the side surface thereof is slightly receded in the horizontal direction.

Next, as shown in fig. 24D, similarly to the first embodiment, the GaN layer 12 is grown. As described above, because of SiO₂The sidewalls of the film 36 recede in the horizontal direction, so preventing contact at SiO₂A GaN layer 12 is deposited on the sidewalls of the film 36.

Next, as shown in FIG. 24E, SiO is etched using a wet etch, for example, an acidic etchant with hydrogen fluoride₂The film 36 is entirely removed, and as a result, the SiN film 37 and the GaN layer 34 to be grown thereon are also removedAnd (4) removing (stripping).

Next, as shown in fig. 24F and 24G, the GaN layer 12 is laterally grown similarly to the first embodiment.

As in the first embodiment, the step of growing the n-type GaInN layer 13 and subsequent steps are performed to provide a GaN light emitting diode.

According to the fifth embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a sixth embodiment of the present invention is described.

In the sixth embodiment, as shown in fig. 25A to 25D, a GaN layer 12 is grown on a sapphire substrate 11 patterned with scores, similarly to the first embodiment.

As shown in fig. 25E, GaN layer 12 is patterned by RIE or the like to selectively remove the portion where threading dislocations are concentrated on projecting portion 11b, thereby allowing the surface of projecting portion 11b to be exposed there.

As shown in fig. 25F and 25G, the GaN layer 37 is laterally grown from the GaN layer 12 remaining on the notch portion 11 a.

Thereafter, a step of growing the n-type GaInN layer 13 and subsequent steps are performedto provide a GaN light emitting diode, similarly to the first embodiment.

According to the sixth embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a seventh embodiment of the present invention is described.

In the seventh embodiment, as shown in fig. 26A, a GaN layer 38 is grown on a flat sapphire substrate 11.

As shown in fig. 26B, the GaN layer 38 is patterned to be scored to form notch portions 38a and protrusion portions 38B, similarly to the notch portions 11a and protrusion portions 11B of the sapphire substrate 11 in the first embodiment.

Next, as in the first embodiment, GaN layer 12 is grown on patterned scored GaN layer 38.

Next, a step of growing the n-type GaInN layer 13 and subsequent steps are performed in the same manner as in the first embodiment to provide a GaN light emitting diode.

According to the seventh embodiment, advantages similar to those of the first embodiment can be obtained.

Next, an eighth embodiment of the present invention is described.

In the eighth embodiment, the first embodiment is repeated until the p-side electrode 21 is formed, which is different in the subsequent steps. In order to form the p-side electrode 21, it is preferable to use a technique for preventing diffusion of an electrode material (e.g., Ag) and to insert a layer containing palladium (Pd). Alternatively, in order to prevent the occurrence of a failure, for example, in the p-side electrode 21, Au or Sn diffuses from an Au or Sn-containing layer (solder layer, bump, or the like) formed on the above-described layer due to, for example, stress or a failure occurs due to heating, a barrier metal layer substantially free of grain boundaries and amorphous may be used by forming a high-melting-point metal layer, such as Ti, W, or an alloy thereof, or a nitride of each of these metals (such as TiN, WN, TiWN, or the like), on the electrode. The technique of inserting Pd-containing layers is well known, for example in the field of metal plating, and in the technique of Al wiring for silicon-based electronic devices, barrier metal materials are well known.

More specifically, as shown in fig. 27A, after the p-side electrode 21 is formed, for example, the Ni film 41 covering the p-side electrode 21 is formed by a lift (lift) method. Next, although not shown in the figure, for example, a Pd film is formed to cover the Ni film 41. Then, a metal nitride film such as TiN, WN, TiWN, etc. is formed to cover the Pd film, and if necessary, a Ti film, a W film, a Mo film, or an alloy film thereof is formed to cover the nitride film. Instead of forming the Ni film 41, a Pd film may be formed to cover the p-side electrode 21, and then a TiN, WN, TiWN film or the like may be formed to cover the Pd film, and if necessary, a Ti film, a W film, a Mo film, or an alloy film composed thereof may be formed to cover the Pd film.

Next, as shown in fig. 27B, a resist pattern 42 of a given pattern is formed to cover the Ni film 41 and the upper layer including the Pd film by photolithography.

Then, as shown in fig. 27C, etching is performed by RIE method using the resist pattern 42 as a mask, for example, to form the mesa portion 22 in which the cross-sectional shape of the mesa portion is trapezoidal. For example, the angle formed between the mesa portion 22 and the main surface of the sapphire substrate 11 is set to about 35 degrees. If necessary, on the inclined surface of the mesa portion 22, a λ/4 dielectric film is formed, where λ is an emission wavelength.

Next, as shown in fig. 27D, an n-side electrode 23 is formed on the n-type GaInN layer 13.

Next, as shown in FIG. 27E, SiO is formed on the entire surface of the substrate₂And a film 43 as a passivation film. In manufacturing, SiN film or SiON film may be used in consideration of adhesion to the underlying layer, durability, and corrosion resistanceInstead of SiO₂A membrane 43.

As shown in FIG. 27F, for SiO in order to reduce its thickness₂The film 43 is etched back, followed by SiO at the inclined portion of the mesa portion 22₂On the film 43, an Al film 44 as a reflective film is formed. This Al film 44 serves to reflect light generated from the active layer 16 to the sapphire substrate 11 side, thereby improving light extraction efficiency. The Al film 44 is formed so as to be in contact with the n-side electrode 23 at one end. This is because no gap is formed between the Al film 44 and the n-side electrode 23 in order to enhance light reflection. Then, SiO is formed again₂ Film 43, which is thick enough to form a passivation film.

As shown in FIG. 27G, the SiO film 41 and the upper surface of the n-side electrode 23 are etched₂Film 43Portions are removed to form openings 45, 46, thereby exposing the Ni film 41 and the n-side electrode 23 at these portions.

Next, as shown in fig. 27H, a pad electrode 47 is formed on the Ni film 41 at the opening 45, and a pad electrode 48 is formed on the n-side electrode 23 at the opening 46.

As shown in fig. 27I, a bump mask material 49 is formed on the entire surface of the substrate, and then the bump mask material 49 is removed by etching a portion above the pad electrode 48 to form an opening 50, exposing the pad electrode 48 at the opening 50.

Next, as shown in fig. 27J, an Au bump 51 is formed on the pad electrode 48 using the bump mask material 49, and thenthe bump mask material 49 is removed. Thereafter, a bump mask material (not shown) is formed again on the entire surface of the substrate, and the bump mask material 49 located above the pad electrode 47 is removed by etching to form an opening where the pad electrode 47 is exposed. Au bumps 52 are formed on the pad electrodes 47.

The sapphire substrate 11, on which the light emitting diode structure has been formed in the manner set forth above, is cut or ground from the back surface thereof to reduce the thickness of the substrate, if necessary, and then the sapphire substrate 11 is scribed to form a bar. The strip is then scribed into chips.

Note that: the electrode stack structure illustrated in fig. 27A to 27J is only an example. In particular, when the respective electrode layers are stacked in plurality, it is necessary to obtain high reflectivity by improving adhesion between the p-side electrode 21 formed of an Ag electrode or the like and other metal layers, stress durability, and crack resistance, and to make contact resistance low, to maintain the quality of the Ag electrode or the like, and the like, while considering suppression of occurrence of stress, which occurs as the device temperature increases due to a difference in thermal expansion coefficient between the respective metal layers, and diffusion between adjacent metal layers. Thus, the Al wiring techniques of the silicon electronic devices described above can be utilized, if desired.

A ninth embodiment of the present invention is described.

In a ninth embodiment, a method of manufacturing a light emitting diode backlight device is described, in which, in addition to the GaN blue light emitting diode and the GaN green light emitting diode obtained by the method according to the first embodiment, an AlGaInP red light emitting diode provided separately is used for this purpose.

According to the method of the first embodiment of the present invention, a GaN blue light emitting diode structure is formed on a sapphire substrate 11, bumps (not shown) are formed on the p-side electrode 21 and the n-side electrode 23, respectively, and then, chip dicing is performed to obtain a flip chip type GaN blue light emitting diode. Similarly, a flip-chip GaN green light-emitting diode was obtained. On the other hand, as for the AlGaInP red light emitting diode, the AlGaInP red light emitting diode is generally used in a chip form, which is obtained by forming an AlGaInP semiconductor layer on an n-type GaAs substrate and further providing a diode structure on which a p-side electrode is formed and an n-side electrode is formed on the back surface of the n-type GaAs substrate.

These AlGaInP red light emitting diode chip, GaN green light emitting diode, and GaN blue light emitting diode are each mounted on a submount made of AlN or the like, and then mounted on a substrate such as an Al substrate with the submount turned down, as shown in fig. 28A. In fig. 28A, reference numeral 61 denotes a substrate. Similarly, 62 denotes a submount, 63 denotes an AlGaInP red light emitting diode chip, 64 denotes a GaN green light emitting diode chip, and 65 denotes a GaN blue light emitting diode chip. These AlGaInP red light-emitting diode chip 63, GaN green light-emitting diode chip 64, and GaN blue light-emitting diode chip 65 each have a chip size of, for example, 350 μm square. These AlGaInP red light emitting diode chips 63 are mounted such that an n-side electrode is on the submount 62, and a GaN green light emitting diode chip 64 and a GaN blue light emitting diode chip 65 are mounted in such a manner that a p-side electrode and an n-side electrode are provided on the submount 62 via bumps, respectively. The submount 62 on which the AlGaInP red light emitting diode chip 63 is mounted has an extraction electrode (not shown) of a given patternfor an n-side electrode above it. The n-side electrode of the AlGaInP red light emitting diode chip 63 is mounted on a prescribed portion of the extraction electrode. For connection, the p-side electrode of the AlGaInP red light-emitting diode chip 63 and a given pad electrode 66 provided on the substrate 21 are connected to wires 67, respectively. Likewise, wires (not shown) are connected to the extraction electrode at one end and another pad electrode provided on the substrate 61, respectively, to ensure connection therebetween. The submount 62 mounting the GaN green light emitting diode chip 64 has an extraction electrode corresponding to the p-side electrode and an extraction electrode corresponding to the n-side electrode (both not shown), respectively, which are formed in a desired pattern. The p-side electrode and the n-side electrode of the GaN green light emitting diode chip 64 are mounted on given portions of the extraction electrode of the p-side electrode and the extraction electrode of the n-side electrode, respectively, by bumps. One ends of the extraction electrode corresponding to the p-side electrode of the GaN green light emitting diode chip 64 and the pad electrode on the substrate 61 are connected to one line (not shown), respectively, and one ends of the extraction electrode corresponding to the n-side electrode and the pad electrode on the substrate 61 are connected to one line (not shown), respectively. The GaN blue led chip 65 is the same.

Note that: the submount 62 may not be used, and in this case, the AlGaInP red light emitting diode chip 63, the GaN green light emitting diode chip 64, and the GaN blue light emitting diode chip 65 are directly mounted on any printed circuit board having good emission performance, respectively, thereby reducing the cost of the light emitting diode backlight device as a whole.

In practice, these AlGaInP red light emitting diode chips 63, GaN green light emittingdiode chips 64, and GaN blue light emitting diode chips 65 are provided in unit cells (unit cells), and a required number of the units are arranged in a given pattern on the substrate 61. An example of this is shown in fig. 29A. Next, as shown in fig. 28B, the device unit is encapsulated with a transparent resin 68, and the unit is further covered. The transparent resin 68 is then hardened. By the hardening, the transparent resin 68 is solidified, whereby the resin is slightly shrunk (fig. 28C). With this method, a light emitting diode backlight device is obtained in which an AlGaInP red light emitting diode chip 63, a GaN green light emitting diode chip 64, and a GaN blue light emitting diode chip 65 are provided in the form of device units, specifically, as shown in fig. 29B, which are arranged in an array on a substrate 61. In this case, the transparent resin 68 is in contact with the back surfaces of the sapphire substrates of the GaN green light-emitting diode chip 64 and the GaN blue light-emitting diode chip 65, so that the difference in refractive index is smaller than in the case where the back surface of the sapphire substrate 11 is in direct contact with air. Eventually, light transmitted through the sapphire substrate 11 to leak to the outside is caused to be less likely to be reflected at the back surface of the sapphire substrate 11, thereby improving light extraction efficiency.

This type of light emitting diode backlight is suitable for application as a backlight for a liquid crystal panel, for example.

Next, a tenth embodiment of the present invention is described.

In the tenth embodiment, a required number of device units including AlGaInP red light emitting diode chips 63, GaN green light emitting diode chips 64, GaN blue light emitting diode chips 65 are arranged in the same given pattern as in the ninth embodiment on a substrate 61. Then, as shown in fig. 30, a transparent resin 69 suitable for the AlGaInP red light emitting diode chip 63 (i.e., having higher transparency to light of the diode chip emission wavelength) encapsulates the AlGaInP light emitting diode chip 63 to cover the AlGaInP red light emitting diode chip 63. Similarly, the GaN light emitting diode chip 64 is encapsulated by a transparent resin 70 suitable for the GaN green light emitting diode chip 64 so as to cover the GaN green light emitting diode chip 64. The transparent resin 71 suitable for the GaN blue light emitting diode chip 65 encapsulates the GaN blue light emitting diode chip 65 to cover the GaN blue light emitting diode chip 65. Then, the transparent resin 69 to 71 is cured. Upon curing, the transparent resins 69 to 71 solidify, and as a result of the solidification, a minute shrinkage occurs. With this method, a light emitting diode backlight device having a plurality of cells each composed of an AlGaInP red light emitting diode chip 63, a GaN green light emitting diode chip 64, a GaN blue light emitting diode chip 65, and arranged in an array on a substrate 61 can be obtained. In this case, the transparent resins 70, 71 are in contact with the back surfaces of the sapphire substrates 11 of the GaN green light-emitting diode chips 64 and the GaN blue light-emitting diode chips 65, so that the difference in refractive index is smaller than in the case where the back surfaces of the sapphire substrates 11 are in direct contact with air. Eventually, the fact that light transmitted through the sapphire substrate 11 to leak to the outside is less likely to be reflected at the back surface of the sapphire substrate 11 is caused, thus improving light extraction efficiency.

This type of light emitting diode backlight is suitable for application as a backlight for a liquid crystal panel, for example.

Next, an eleventh embodiment of the present invention is described.

In the eleventh embodiment, according to the method of the first embodiment of the present invention, a GaN light emitting diode structure is formed on a sapphire substrate 11, and bumps (not shown) are formed on the p-side electrode 21 and the n-side electrode 23, respectively. Then, the sapphire substrate 11 is scribed into square parts having a given size. Thus, as shown in fig. 31, an integrated light emitting diode having a stripe-shaped emission portion can be obtained. In this case, the n-side electrode 23 is formed to surround the band-shaped mesa portion 22. As shown in fig. 32, the integrated GaN light emitting diode is mounted on a submount 69 composed of AlN or the like. The base 69 has an extraction electrode corresponding to the p-side electrode and an extraction electrode corresponding to the n-side electrode (both not shown) formed in a given pattern, and solder bumps 70, 71 are formed on the extraction electrodes. The integrated GaN light emitting diode is mounted such that the p-side electrode 21 is placed on the solder 70 and the n-side electrode 23 is placed on the solder 71, and then the solders 70, 71 are melted to make connection.

Next, a twelfth embodiment of the invention is described.

In the twelfth embodiment, the fabrication of a light source unit device (cell unit) is described, and AlGaInP red light emitting diodes fabricated separately are used in addition to the GaN blue light emitting diodes and GaN green light emitting diodes obtained in the steps of the first embodiment.

As shown in fig. 33A, a required number of cells 81 each including AlGaInP red light emitting diode chip 63, GaN green light emitting diode chip 64, GaN blue light emitting diode chip 65, each in a number of at least 1, are arranged in a given pattern on a printed circuit board 82, and these diodes are arranged in a given pattern. In this example, the single unit 81 includes an AlGaInP red light emitting diode chip 63, a GaN green light emitting diode chip 64, and a GaN blue light emitting diode chip 65, which are located at the vertices of a triangle. Fig. 33B shows the enlarged cell 81. In each cell 81, the distance a between the AlGaInP red light emitting diode chip 63, the GaN green light emitting diode chip 64, and the GaN blue light emitting diode chip 65 is, for example, 4mm, but is not limited to this distance. The distance b of the cell 81 is, for example, 30mm, but is not limited thereto. For the printed circuit board 82, an FR4 (flame retardant type 4) substrate, a metal core substrate, or the like may be used, but without limitation, other types of printed circuit board substrates having radiation (radiation) properties may also be used. Similarly to the ninth embodiment, the transparent resin 68 is sealed to cover each cell 81. Alternatively, similarly to the tenth embodiment, a transparent resin 69 is sealed to cover the AlGaInP red light-emitting diode chip 63, a transparent resin 70 is sealed to cover the GaN green light-emitting diode chip 64, and a transparent resin 71 is sealed to cover the GaN blue light-emitting diode chip 65. In this way, a light source unit device is obtained in which cells 81 are arranged on a printed circuit board 82, each cell 81 being constituted by an AlGaInP red light emitting diode chip 63, a GaN green light emitting diode chip 64, and a GaN blue light emitting diode chip 65.

A specific example of the arrangement of the cells 81 on the printed circuit board 82 is shown in fig. 34A and 34B. The example shown in fig. 34A is a 4 × 3 two-dimensional cell 81 array, and the example shown in fig. 34B is a 6 × 2 two-dimensional cell 81 array.

Fig. 35 shows an example of another type of array of cells 81. In this example, the cell 81 includes one AlGaInP red light emitting diode chip 63, two GaN green light emitting diode chips 64, and one GaN blue light emitting diode chip 65, which are arranged, for example, at the apex of a square. Two GaN green light emitting diode chips 64 are arranged at both ends of one diagonal line of the square, and an AlGaInP red light emitting diode chip 63 and a GaN blue light emitting diode chip 65 are arranged at both ends of the other diagonal line of the square.

When this type of light source device is provided singly or in plural, the light emitting diode backlight device may be applied as a backlight device such as a liquid crystal panel.

In the foregoing, the embodiments of the present invention have been described in detail, but the present invention should not be construed as being limited to only these embodiments. Many variations are possible in accordance with the principles of the present technology.

For example, the numerical values, materials, structures, shapes, substrates, starting materials, processes, and extending directions of the notch parts 11a described in the first to twelfth embodiments of the present invention are merely examples. Different values, materials, structures, shapes, substrates, starting materials, processes, etc. than those previously described may be used if desired.

Also, in the first to twelfth embodiments of the present invention, for example, the conductivity types of the p-type GaN semiconductor layer and the n-type GaN semiconductor layer may be reversed. Further, for example, a SiC substrate, a Si substrate, and other types of substrates may be substituted for the sapphire substrate 11.

The extending direction of the notch portion 11a may not be the<1-100>direction of the GaN layer 12 but the<11-20>direction of the GaN layer 12.

Two or more of the first to twelfth embodiments may be combined if necessary.

Those skilled in the art will understand that: various modifications, combinations, sub-combinations, and alterations may occur to others as may be within the scope of the claims or the equivalents thereof, depending upon design considerations and other factors.

The subject matter encompassed by the present invention relates to Japanese patent application JP 2005-142462 filed by the Japanese patent office at 16.5.2005 and Japanese patent application JP2006-105647 filed by the Japanese patent office at 6.4.2006, the contents of which are incorporated herein by reference.

Claims (25)

1. A method of manufacturing a light emitting diode comprising the steps of:

providing a substrate having at least one notch portion on one main surface, growing a first nitride-based group III-V compound semiconductor layer by forming a state of a triangle having a bottom face of the notch portion as a base in cross section, thereby burying the notch portion;

laterally growing a second nitride-based III-V compound semiconductor layer from the first nitride-based III-V compound semiconductor layer on the substrate; and

a third nitride-based III-V group compound semiconductor layer having a first conductive type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductive type are sequentially grown on the second nitride-based III-V group compound semiconductor layer.

2. The method according to claim 1, wherein during the growth of the first nitride-based III-V compound semiconductor layer, dislocations occur from an interface between the bottom surfaces of the recess portions in a direction perpendicular to the one main surface, the dislocations reaching a triangular inclined surface having the bottom surface of therecess portion as a base or a vicinity thereof, whereby the dislocations are bent in a direction parallel to the one main surface.

3. The method according to claim 1, wherein when the first nitride-based III-V compound semiconductor layer and the second nitride-based III-V compound semiconductor layer are grown separately, first pits having a first width are formed in the substrate at bottom surfaces of the notch portions, and second pits having a second width larger than the first width are formed in the substrate at opposite sides of the notch portions.

4. The method of claim 1, wherein the notched portion is an inverted trapezoid in cross section.

5. The method according to claim 4, wherein assuming that the depth of the notch portion is d, the width of the bottom surface of the notch portion is W_gWherein when an angle formed between an inclined surface of the first nitride-based group III-V compound semiconductor layer in a state of being triangular in cross section and the one main surface of the substrate is α, d, Wg, and α are determined so as to satisfy the relationship 2d ≧ W_gtanα。

6. The method of claim 1, wherein the major surface has an alternating arrangement of the recessed portions and protruding portions.

7. The method of claim 1, wherein the notched portion extends in one direction.

8. The method of claim 1, wherein the at least one notch portion is plural in number and the plurality of notch portions extend in first and second directions that intersect one another.

9. The method according to claim 1, wherein the projection portion is hexagonal in plan, and a plurality of the projection portions are arranged in a two-dimensional honeycomb form, and the recess portion is formed to surround each projection portion.

10. The method of claim 1, wherein the substrate is such that: the nitride-based group III-V compound semiconductor layer is grown on a substrate of a material different from that of the nitride-based group III-V compound semiconductor layer, and the notch portion is formed on the nitride-based group III-V compound semiconductor layer.

11. The method of claim 1, wherein the substrate has an amorphous layer on opposite sides of the recess portion.

12. The method according to claim 11, wherein the amorphous layer is formed by ion implantation of a surface layer of the substrate and amorphization of the surface layer.

13. The method according to claim 11, wherein the amorphous layer is composed of an insulating film formed over the substrate.

14. The method according to claim 1, wherein a first amorphous layer, a second amorphous layer, and a third amorphous layer are sequentially formed on the substrate on opposite sides of the recess portion, and the second amorphous layer causes the first amorphous layer and the third amorphous layer to be selectively etched.

15. The method according to claim 1, wherein after laterally growing the second nitride-based III-V compound semiconductor layer, a portion other than a portion above a notched portion of the second nitride-based III-V compound semiconductor layer is removed, the third nitride-based III-V compound semiconductor layer is laterally grown on the second nitride-based III-V compound semiconductor layer left on the notched portion, and the active layer and the fourth nitride-based III-V compound semiconductor layer are sequentially grown on the third nitride-based III-V compound semiconductor layer.

16. The method according to claim 1, wherein after laterally growing the second nitride-based III-V compound semiconductor layer, a portion other than a portion above a notched portion of the second nitride-based III-V compound semiconductor layer is removed, a fifth nitride-based III-V compound semiconductor layer is laterally grown on the second nitride-based III-V compound semiconductor layer left on the notched portion, and the third nitride-based III-V compound semiconductor layer, the active layer, and the fourth nitride-based III-V compound semiconductor layer are sequentially grown on the fifth nitride-based III-V compound semiconductor layer.

17. A method of manufacturing an integrated light emitting diode comprising the steps of:

growing a first nitride-based group III-V compound semiconductor layer in at least one recess portion on one main surface of a substrate, the first nitride-based group III-V compound semiconductor layer being brought into a state of forming a triangle having a bottom face of the recess portion as a base in cross section, thereby burying the recess portion;

laterally growing a second nitride-based III-V compound semiconductor layer from the first nitride-based III-V compound semiconductor layer on the substrate; and

a third nitride-based group III-V compound semiconductor layer having the first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer are sequentially grown on the second nitride-based group III-V compound semiconductor layer.

18. A light emitting diode, comprising:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion; and

a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer,

wherein in the sixth nitride-based group III-V compound semiconductor layer, dislocations occur from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reach a slope of a triangle having the bottom surface of the recess portion as a base or a vicinity thereof, and are bent in a direction parallel to the one main surface.

19. A light emitting diode, comprising:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion; and

a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer,

wherein a first pit having a first width is formed in the substrate at the bottom of the notch portion, and a second pit having a second width larger than the first width is formed in the substrate at the bottom of the notch portion.

20. An integrated light emitting diode integrated with a plurality of light emitting diodes, at least one light emitting diode comprising:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion; and

a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer,

wherein in the sixth nitride-based group III-V compound semiconductor layer, dislocations occur from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reach a slope of a triangle having the bottom surface of the recess portion as a base or a vicinity thereof, and are bent in a direction parallel to the one main surface.

21. A method of growing a nitride-based III-V compound semiconductor layer, comprising the steps of:

providing a substrate having at least one notch portion on one main surface, growing a first nitride-based group III-V compound semiconductor layer by forming a state of a triangle having a bottom face of the notch portion as a base in cross section, and buryingthe notch portion; and

laterally growing a second nitride-based III-V compound semiconductor layer from the first nitride-based III-V compound semiconductor layer on the substrate.

22. A light source unit device comprising a printed circuit board and a plurality of units formed on the printed circuit board, each unit comprising at least one red light emitting diode, at least one green light emitting diode, and at least one blue light emitting diode, wherein at least one of the red light emitting diode, the green light emitting diode, and the blue light emitting diode comprises:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion; and

a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer,

wherein in the sixth nitride-based group III-V compound semiconductor layer, dislocations occur from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reach a slope of a triangle having the bottom surface of the recess portion as a base or a vicinity thereof, and are bent in a direction parallel to the one main surface.

23. A light emitting diode backlight device, comprising:

a plurality of red light emitting diodes, a plurality of green light emitting diodes, and a plurality of blue light emitting diodesarranged in a pattern, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes comprises:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion;

a third nitride-based group III-V compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based group III-V compound semiconductor layer having a second conductivity type formed on the sixth nitride-based group III-V compound semiconductor layer; and

in the sixth nitride-based III-V group compound semiconductor layer, dislocations occur from the interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reach a triangular inclined surface having the bottom surface of the recess portion as a base or a vicinity thereof, and are bent in a direction parallel to the one main surface.

24. A light emitting diode display, comprising:

a plurality of red light emitting diodes, a plurality of green light emitting diodes, and a plurality of blue light emitting diodes arranged in a pattern, wherein at least one of the red light emitting diodes, the green light emitting diodes, and the blue light emitting diodes comprises:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion; and

a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer,

wherein in the sixth nitride-based group III-V compound semiconductor layer, dislocations occur from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reach a slope of a triangle having the bottom surface of the recess portion as a base or a vicinity thereof, and are bent in a direction parallel to the one main surface.

25. An electronic device having at least one light emitting diode, the at least one light emitting diode comprising:

a substrate having at least one notch portion on one main surface;

a sixth nitride-based group III-V compound semiconductor layer grown on the substrate without forming a gap in the recess portion; and

a third nitride-based III-V group compound semiconductor layer having a first conductivity type, an active layer, and a fourth nitride-based III-V group compound semiconductor layer having a second conductivity type formed on the sixth nitride-based III-V group compound semiconductor layer,

wherein in the sixth nitride-based group III-V compound semiconductor layer, dislocations occur from an interface with the bottom surface of the recess portion in a direction perpendicular to the one main surface, reach a slope of a triangle having the bottom surface of the recess portion as a base or a vicinity thereof, and are bent in a direction parallel to the one main surface.

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