CN111933765B - Miniature light-emitting diode and manufacturing method thereof, and miniature LED display module and manufacturing method thereof - Google Patents

Miniature light-emitting diode and manufacturing method thereof, and miniature LED display module and manufacturing method thereof Download PDF

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CN111933765B
CN111933765B CN202010636615.9A CN202010636615A CN111933765B CN 111933765 B CN111933765 B CN 111933765B CN 202010636615 A CN202010636615 A CN 202010636615A CN 111933765 B CN111933765 B CN 111933765B
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layer
electrode
semiconductor
semiconductor layer
electrode structure
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CN111933765A (en
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范伟宏
李东昇
马新刚
赵进超
李超
高默然
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Xiamen Silan Advanced Compound Semiconductor Co Ltd
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Hangzhou Silan Azure Co Ltd
Xiamen Silan Advanced Compound Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes

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Abstract

Disclosed are a micro light emitting diode and a manufacturing method thereof, a micro LED display module and a manufacturing method thereof, wherein the micro light emitting diode comprises: the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer; the second electrode is positioned on the surface of the second semiconductor layer in the epitaxial layer; the reflecting mirror layer is positioned on the surface of the second electrode; the protective layer is positioned on the surface of the reflector layer; and the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, wherein the first electrode in the first electrode structure is connected with the first semiconductor layer. In the micro light-emitting diode, the first electrode of the first electrode structure and the metal connecting layer are jointly used as the conducting layer and the reflecting layer, so that the light-emitting rate of the micro light-emitting diode is improved. The manufacturing method adopts twice photoetching, thus improving the yield and reducing the cost.

Description

Miniature light-emitting diode and manufacturing method thereof, and miniature LED display module and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a miniature light-emitting diode and a manufacturing method thereof, and a miniature LED display module and a manufacturing method thereof.
Background
With the increasing progress of LED epitaxial chip technology, micro LED (micro light emitting diode) display technology as a pixel becomes a hot development direction of a new generation display technology. How to obtain better display effect on small-sized devices is a problem to be solved by many suppliers. Micro LED display technology is just such a convenient technology. Compared with other micro display technologies in the current market, such as an LCD technology, an OLED technology and a laser display technology, the micro LED has great market potential due to the advantages of small volume, high brightness, high response speed, long service life and the like.
With the reduction of the chip size and the unit interval thereof, the chip unit size is reduced to hundreds of microns to tens of microns, and the unit interval is reduced to the level of ten microns, so that on one hand, the edge light emission of the chip and the optical crosstalk (optical crosstalk) caused by the edge light emission are more serious, and the adverse effect is caused on the display; on the other hand, the micro light-emitting diode faces the challenges of process design and equipment limit capacity in the aspects of yield control and mass transfer technology, and the problems seriously restrict the rapid popularization of the micro LED in the field of display application. On the other hand, the micro LED display requires the use of a large number of chips, resulting in high cost thereof. At present, in the middle and small size display application, the chip usage amount is less, and the chip is not very sensitive to the cost, but the price of the large display panel is in the order of hundreds of thousands or even millions of yuan, and a great gap exists from the commercial popularization application.
Disclosure of Invention
In view of the foregoing problems, an object of the present invention is to provide a micro light emitting diode and a manufacturing method thereof, a micro LED display module and a manufacturing method thereof, in which a first electrode and a metal connection layer in a first electrode structure are used as a conductive layer and a reflective layer, so that light extraction rates of the micro light emitting diode and the micro LED display module are improved, and a display effect is improved. In the manufacturing process, the chemical mechanical grinding and thinning technology is adopted to replace the photoetching technology, so that the photoetching times are reduced, the product process yield is improved, and the process is greatly simplified.
According to an aspect of the present invention, there is provided a micro light emitting diode including: the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer; the second electrode is positioned on the surface of the second semiconductor layer in the epitaxial layer; the reflecting mirror layer is positioned on the surface of the second electrode; the protective layer is positioned on the surface of the reflector layer; and the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, wherein the first electrode in the first electrode structure is connected with the first semiconductor layer.
Preferably, the method further comprises the following steps: the epitaxial layer is positioned on the surface of the first substrate.
Preferably, the epitaxial layer comprises in sequence: the semiconductor device includes a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer.
Preferably, the first semiconductor layer is an N-type doped layer, and the second semiconductor layer is a P-type doped layer.
Preferably, the cross-sectional shape of the first electrode structure is trapezoidal.
Preferably, the first electrode structure penetrates through the protective layer, the mirror layer, the second electrode, and a portion of the epitaxial layer.
Preferably, the dielectric layer is located on an outer side wall of the first electrode, and isolates the first electrode from the protective layer, the mirror layer, the second electrode, the second semiconductor layer, the electron blocking layer, and the multiple quantum well layer.
Preferably, the metal connection layer is located on an inner sidewall of the first electrode.
Preferably, the material of the metal connection layer comprises copper.
Preferably, the protective layer is a layer of a physico-chemically inert metal.
According to another aspect of the present invention, there is provided a method for manufacturing a micro light emitting diode, including: sequentially forming an epitaxial layer, a second electrode, a reflector layer and a protective layer on a first substrate, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer; photoetching the surface of the protective layer to form a walkway area; etching the protective layer, the reflector layer, the second electrode and part of the epitaxial layer corresponding to the walkway area to form a groove exposing the first semiconductor layer; forming a first electrode structure in the groove; the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, and the first electrode is connected with the first semiconductor layer.
Preferably, the step of forming the first electrode structure within the recess comprises: forming dielectric layers on the surface of the protective layer and the surface of the groove, wherein the dielectric layers cover the side wall and the bottom of the groove; photoetching the dielectric layer to expose the first semiconductor layer at the bottom of the groove; sequentially forming a first electrode and a metal connecting layer on the dielectric layer and the first semiconductor layer, wherein the first electrode covers the side wall of the dielectric layer and the bottom of the groove, and the metal connecting layer covers the side wall of the first electrode; and thinning part of the dielectric layer, the first electrode and the metal connecting layer to expose the protective layer.
Preferably, the cross-sectional shape of the groove is trapezoidal.
Preferably, the forming of the epitaxial layer on the first substrate includes: a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer are sequentially formed on a first substrate.
Preferably, the first semiconductor layer is an N-type doped layer, and the second semiconductor layer is a P-type doped layer.
Preferably, the first electrode is an N-type electrode and the second electrode is a P-type electrode.
Preferably, the protective layer is a layer of a physico-chemically inert metal.
Preferably, the material of the metal connection layer comprises copper.
According to still another aspect of the present invention, there is provided a micro LED display module, including: a second substrate; a plurality of control units on the second substrate; a plurality of bonding layers on the control unit; and a plurality of micro light emitting diodes bonded to the bonding layer, the micro light emitting diodes comprising: the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer; the second electrode is positioned on the surface of the second semiconductor layer in the epitaxial layer; the reflecting mirror layer is positioned on the surface of the second electrode; the protective layer is positioned on the surface of the reflector layer; and the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, wherein the first electrode in the first electrode structure is connected with the first semiconductor layer, part of the bonding layer is contacted with the protective layer, and part of the bonding layer is contacted with the first electrode structure.
Preferably, the epitaxial layer comprises in sequence: the semiconductor device includes a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer.
Preferably, the first semiconductor layer is an N-type doped layer, and the second semiconductor layer is a P-type doped layer.
Preferably, the cross-sectional shape of the first electrode structure is trapezoidal.
Preferably, the first electrode structure penetrates through the protective layer, the mirror layer, the second electrode, and a portion of the epitaxial layer.
Preferably, the dielectric layer is located on an outer side wall of the first electrode, and isolates the first electrode from the protective layer, the mirror layer, the second electrode, the second semiconductor layer, the electron blocking layer, and the multiple quantum well layer.
Preferably, the metal connection layer is located on an inner sidewall of the first electrode.
Preferably, a portion of the bonding layer is in contact with a metal connection layer in the first electrode structure.
Preferably, a portion of the bonding layer is in contact with the first electrode and the metal connection layer in the first electrode structure.
Preferably, each of the control units is electrically connected with one of the micro light emitting diodes.
Preferably, a surface of the unintentionally doped layer is formed with a photonic crystal structure.
Preferably, the surface of the unintentionally doped layer is a roughened surface.
Preferably, the material of the metal connection layer comprises copper.
Preferably, the protective layer is a layer of a physico-chemically inert metal.
According to still another aspect of the present invention, there is provided a method of manufacturing a micro LED display module, including: sequentially forming an epitaxial layer, a second electrode, a reflector layer and a protective layer on a first substrate, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer; photoetching the surface of the protective layer to form a walkway area; etching the protective layer, the reflector layer, the second electrode and part of the epitaxial layer corresponding to the walkway area to form a groove exposing the first semiconductor layer; forming a first electrode structure in the groove to obtain a first semiconductor structure; the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, wherein the first electrode is connected with the first semiconductor layer; bonding the first semiconductor structure with a second semiconductor structure, the second semiconductor structure comprising a second substrate, a plurality of control cells on the second substrate, and a plurality of bonding layers on the control cells; and removing the first substrate.
Preferably, the step of forming the first electrode structure within the recess comprises: forming dielectric layers on the surface of the protective layer and the surface of the groove, wherein the dielectric layers cover the side wall and the bottom of the groove; photoetching the dielectric layer to expose the first semiconductor layer at the bottom of the groove; sequentially forming a first electrode and a metal connecting layer on the dielectric layer and the first semiconductor layer, wherein the first electrode covers the side wall of the dielectric layer and the bottom of the groove, and the metal connecting layer covers the side wall of the first electrode; and thinning part of the dielectric layer, the first electrode and the metal connecting layer to expose the protective layer.
Preferably, the cross-sectional shape of the groove is trapezoidal.
Preferably, before the step of bonding the first semiconductor structure and the second semiconductor structure, the method further comprises: and cutting the first semiconductor structure to obtain a plurality of micro light-emitting diodes.
Preferably, after the step of bonding the first semiconductor structure and the second semiconductor structure, the method further comprises: and cutting the first semiconductor structure to obtain a plurality of micro light-emitting diodes.
Preferably, each of the control units is electrically connected with one of the micro light emitting diodes.
Preferably, a portion of the bonding layer in a plurality of bonding layers on the control unit is in contact with the protective layer and a portion of the bonding layer is in contact with the first electrode structure.
Preferably, a portion of the bonding layer is in contact with a metal connection layer in the first electrode structure.
Preferably, a portion of the bonding layer is in contact with the first electrode and the metal connection layer in the first electrode structure.
Preferably, the step of forming an epitaxial layer on the first substrate comprises: a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer are sequentially formed on a first substrate.
Preferably, the first semiconductor layer is an N-type doped layer, and the second semiconductor layer is a P-type doped layer.
Preferably, the first electrode is an N-type electrode and the second electrode is a P-type electrode.
Preferably, after the step of removing the first substrate, the method further includes: and removing the buffer layer in the epitaxial layer.
Preferably, after the step of removing the buffer layer, the method further comprises: and forming a photonic crystal structure on the surface of the unintended doped layer.
Preferably, after the step of removing the buffer layer, the method further comprises: etching at the surface of the unintentionally doped layer roughens the surface of the unintentionally doped layer.
Preferably, the protective layer is a layer of a physico-chemically inert metal.
Preferably, the material of the metal connection layer comprises copper.
According to the micro light-emitting diode and the micro LED display module, the first electrode and the metal connecting layer in the first electrode structure are used as the conducting layer and the reflecting layer, and the light emitting rate of the micro light-emitting diode and the micro LED display module is improved. Furthermore, a photonic crystal structure is formed on the light emitting side of the miniature LED display module, so that the axial light emission of the miniature LED display module is enhanced, the optical crosstalk phenomenon in the miniature LED display module is improved, and higher contrast and better display effect are brought.
According to the manufacturing method of the micro light-emitting diode and the micro LED display module, the technology of photoetching twice and chemical mechanical grinding and thinning are combined, the micro light-emitting diode and the micro LED display module are processed, the process is greatly simplified while the product process yield is improved, the production efficiency is improved, and the process manufacturing cost is reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a portion of a micro LED display module according to an embodiment of the invention;
fig. 2a to 2h are cross-sectional views of the stages of the method for manufacturing a part of the micro LED display module according to the embodiment of the invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another area, the expression "directly above … …" or "above and adjacent to … …" will be used herein.
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
Fig. 1 shows a schematic structural diagram of a part of a micro LED display module according to an embodiment of the present invention. The micro LED display module is formed by bonding a micro light-emitting diode and a control unit.
Referring to fig. 1, a portion of the micro LED display module according to the embodiment of the invention sequentially includes, from bottom to top, a second substrate 200, a control unit 109, a bonding layer 108, a metal connection layer 107, a first electrode 106, a dielectric layer 105, a protective layer 104, a mirror layer 103, a second electrode 102, and an epitaxial layer 101.
In this embodiment, the epitaxial layer 101 includes, in order from bottom to top in a direction perpendicular to the surface of the second substrate 200, a second semiconductor layer 16, an electron blocking layer 15, a multiple quantum well layer 14, a first semiconductor layer 13, and an unintentional doping layer 12. The second semiconductor layer 16 is in contact with the second electrode 102.
In this embodiment, the metal connection layer 107, the first electrode 106 and the dielectric layer 105 constitute a first electrode structure of the micro light emitting diode, and the protective layer 104, the mirror layer 103 and the second electrode 102 constitute a second electrode structure of the micro light emitting diode. The first electrode structure penetrates the protective layer 104, the mirror layer 103, the second electrode 102 and a portion of the epitaxial layer 101, and specifically penetrates the second semiconductor layer 16, the electron blocking layer 15 and the mqw layer 14 in the epitaxial layer 101. In the first electrode structure, the dielectric layer 105 is used to isolate the first electrode 106 from the electrical contact between the protective layer 104, the mirror layer 103, the second electrode 102, and the second semiconductor layer 16, the electron blocking layer 15, and the mqw layer 14. At the contact surface of the first electrode structure and the first semiconductor layer 13, the first electrode 106 is in direct contact with the first semiconductor layer 13.
In this embodiment, a plurality of control units 109 are formed on the second substrate 200, two bonding layers 108 are formed on each control unit 109, the bonding layers 108 are pad bonding layers, the first bonding layer 108 is in contact with the protection layer 104, and the second bonding layer 108 is in contact with the metal connection layer 107, that is, each control unit 109 is electrically connected to one micro light emitting diode through the two bonding layers 108. Since the first bonding layer 108 is connected to the second electrode structure and the second bonding layer 108 is in contact with the first electrode structure, the control unit 109 controls light emission of the micro light emitting diode through the bonding layer 108. In particular, the second bonding layer 108 may also be in contact with the first electrode 106 and the metal connection layer 107.
In this embodiment, the metal connection layer 107 in the first electrode structure can increase the conductivity of the first electrode 106, and meanwhile, the metal connection layer 107 and the first electrode 106 prepared on the whole surface are used as a high reflector on the side wall, so as to further enhance the reflection of light and improve the light extraction rate of the micro LED display module.
In this embodiment, a photonic crystal structure is formed on the unintended doping layer 12, or the unintended doping layer 12 is roughened, so that the axial light-emitting effect of the micro LED display module is enhanced, the optical crosstalk phenomenon in the display technology of the micro LED display module is improved, and a higher contrast ratio and a better display effect are brought.
Fig. 2a to 2h are cross-sectional views of the stages of the method for manufacturing a part of the micro LED display module according to the embodiment of the invention.
Referring to fig. 2a, an epitaxial layer 101, a second electrode 102, a mirror layer 103, and a protective layer 104 are sequentially formed on a first substrate 100.
In this step, an epitaxial layer 101 is formed on the surface of the first substrate 100 in a direction perpendicular to the surface of the first substrate 100, for example, by epitaxial growth, and the thickness of the epitaxial layer 101 is, for example, 5 to 10 μm. Methods of epitaxial growth include, for example, metal chemical vapor deposition, laser assisted molecular beam epitaxy, laser sputtering, or hydride vapor phase epitaxy processes.
Further, for example, a second electrode 102, a mirror layer 103 and a protective layer 104 are sequentially formed on the surface of the epitaxial layer 101 by a sputtering method, specifically, the second electrode 102 is prepared on the surface of the epitaxial layer 101 by a sputtering method, and is subjected to a rapid annealing treatment for 1 to 5 minutes in a nitrogen atmosphere, and then the mirror layer 103 is prepared on the second electrode 102 by a sputtering method again, and then the protective layer 104 is prepared on the mirror layer 103 by a sputtering method.
In this embodiment, the first substrate 100 is, for example, a 4-inch sapphire substrate, including but not limited to one of a mirror or micro/nano patterned sapphire substrate, which is preferably a mirror sapphire substrate. The material of the epitaxial layer 101 may be any one of amorphous, polycrystalline or single crystal structure, for example, one or more materials in a reciprocating continuous progressive LED epitaxial structure composed of GaN/InGaN/AlGaN/AlInGaN and other material systems, and the preferred scheme is GaN/InGaN. The total thickness of the epitaxial layer 101 is, for example, 5 to 10 micrometers.
In this embodiment, the epitaxial layer 101 includes, in order from the surface of the first substrate 100 upward, a buffer layer 11, an unintentional doping layer 12, a first semiconductor layer 13, a multiple quantum well layer 14, an electron blocking layer 15, and a second semiconductor layer 16. The unintentional doping layer 12 is made of GaN, the first semiconductor layer 13 is an N-type doping layer made of N-GaN, and the second semiconductor layer 16 is a P-type doping layer made of P-GaN, for example.
In this embodiment, the material of the second electrode 102 is, for example, Indium Tin Oxide (ITO), and the thickness is, for example, 20nm to 1 um. The material of the mirror layer 103 is, for example, silver (Ag), and the thickness is, for example, 100-500 nm. The material of the passivation layer 104 is, for example, TiPtAu, and the thickness is, for example, 200nm-3 um.
In other embodiments, the first substrate 100 is, for example, a 6-inch Si substrate, including but not limited to one of a mirror or micro/nano patterned Si substrate, which is preferably a mirror Si substrate. The different materials of the first substrate 100 may cause different processes to be used for peeling off the first substrate 100 in subsequent steps.
In other embodiments, the first substrate 100 may also be one of a homogeneous or heterogeneous substrate including GaAs, GaN, AlN, Ga2O3SiC and ZnO single crystal substrates and high-temperature resistant metal substrates with pre-deposited AlN films, wherein the substrate size is 1 inch to 8 inches, and the substrate thickness is 300um to 2 um.
In other embodiments, epitaxial layer 101 may also be one or more combinations of binary, ternary, and quaternary alloy materials composed of group iii Al/Ga/In and group v/P/As, and emitting wavelengths ranging from 760nm red to 400nm violet.
In other embodiments, the second electrode 102 is one of a single layer or a multilayer film of NiAu, NiAg, NiO, and a transparent conductive layer, and has a thickness ranging from 10nm to 1 um. The mirror layer 103 is one or more of Al, Ag, Rh, Pt, DBR, ODR, and has a thickness ranging from 100nm to 3 um. The protective layer 104 is one or more of Ti, Pt, Ni, Cr, TiW, Rh that are physically and chemically inert, and has a thickness ranging from 200nm to 3 um.
In fig. 2a and the following drawings, which show a cross-sectional view of a method for manufacturing a micro LED display module having only two micro light emitting diodes, since the micro LED display module includes a plurality of micro light emitting diodes, it can be understood that a person skilled in the art can understand the manufacturing process of the whole micro LED display module according to the example of fig. 2 a.
Further, a patterned mask layer is formed on the surface of the protection layer 104, and a first groove 122 is formed in the semiconductor structure through the patterned mask layer, as shown in fig. 2 b.
In this step, a mask layer is formed on the surface of the protection layer 104, the material of the mask layer is, for example, photoresist, a patterned mask layer is formed by a photolithography technique, and a via region for forming the first electrode structure is exposed. The via area is a partial area of the surface of the protection layer 104, and the subsequent steps are to etch a groove in the via area and form a first electrode structure in the groove.
Further, an etching process, such as wet etching and/or dry etching, is used to form the first recess 122 in the semiconductor structure corresponding to the via region through the patterned mask layer. Specifically, the protective layer 104, the mirror layer 103, and the second electrode 102 corresponding to the via region are removed by wet etching, and the second semiconductor layer 16, the electron blocking layer 15, and the mqw layer 14 are removed by dry etching.
In this embodiment, the first groove 122 penetrates the protective layer 104, the mirror layer 103, the second electrode 102 and a portion of the epitaxial layer 101, specifically, penetrates the second semiconductor layer 16, the electron blocking layer 15 and the multiple quantum well layer 14 in the epitaxial layer 101, and exposes the surface of the first semiconductor layer 13. The cross-sectional shape of the first groove 122 is, for example, a trapezoid. And after the etching is finished, removing the photoresist mask layer.
Further, a dielectric layer 105 is formed on the surface of the semiconductor structure, and a portion of the dielectric layer 105 located at the bottom of the first recess 122 is removed, as shown in fig. 2 c.
In this step, a dielectric layer 105 is formed, for example, by using a thin film preparation technique, such as an atomic layer deposition process, and the dielectric layer 105 covers the surface of the protection layer 104 and the sidewalls and the bottom of the first groove 122.
In this embodiment, the material of the dielectric layer 105 is, for example, SiO2E.g., 500nm to 2um thick, the dielectric layer 105 in the first recess 122 is used to isolate the first electrode 106 and the metal connection layer 107, which are formed subsequently, from the electrical connections between the epitaxial layer 101, the second electrode 102, the mirror 103 and the protection layer 104.
Further, the method further includes removing the dielectric layer 105 at the bottom of the first groove 122 by using a photolithography technique and an etching process, exposing the surface of the first semiconductor layer 13, and forming a second groove 123. In this embodiment, the cross-sectional shape of the second groove 123 is, for example, a trapezoid.
In other embodiments, dielectric layer 105 is made of, for example, SiO2、SiNx、TiO2、AlN、Al2O3、HfO2、MgF2The formed single component orOne of the multi-component films has a thickness ranging from 500nm to 2um, for example, and the thin film preparation technique thereof further includes any one of sputtering, evaporation or CVD, etc.
Further, a first electrode 106 is formed on the surface of the dielectric layer 105, as shown in fig. 2 d.
In this step, an electron beam evaporation process is used to form a first electrode 106 on the surface of the dielectric layer 105, and the material of the first electrode 106 is, for example, craaltiau, and the thickness is, for example, 500nm to 1 um. The first electrode 106 is formed along the surface of the semiconductor structure, and due to the existence of the second groove 123, the formed first electrode 106 forms a third groove 124 at a corresponding position in the second groove 123, and the cross-sectional shape of the third groove 124 is, for example, a trapezoid.
In this embodiment, the sidewall of the first electrode 106 in the second groove 123 is electrically isolated from the mqw layer 14, the electron blocking layer 15, the second semiconductor layer 16, and the second electrode 102, the mirror 103, and the protective layer 104 in the epitaxial layer 101 by the dielectric layer 105, and the bottom of the first electrode 106 in the second groove 123 is in contact with the first semiconductor layer 13.
In this embodiment, the first electrode 106 acts as a sidewall mirror to enhance reflectivity to light.
In other embodiments, the material of the first electrode 106 is, for example, one of binary or multi-element stacked compositions of Cr, Ti, Al, V, Ni, Au, Pt, Sn, Cu, and has a thickness ranging from 500nm to 2um, for example.
Further, a metal connection layer 107 is formed on the surface of the first electrode 106 and in the third recess 124, as shown in fig. 2 e.
In this step, a metal connection layer 107 is formed on the surface of the first electrode 106 and in the third groove 124, for example, by using an electroplating process, and the material of the metal connection layer 107 is Cu and has a thickness of 2um to 10 um.
In this embodiment, the metal connection layer 107 has excellent conductivity, which can increase the conductivity of the first electrode 106, and the metal connection layer 107 and the first electrode 106 prepared on the whole surface act as a high-reflectivity mirror on the side wall, which further enhances the reflection of light.
In other embodiments, the metal connection layer 107 may also be formed by a PVD process, for example, with a thickness ranging from 2um to 20 um.
Further, the dielectric layer 105, the first electrode 106 and the metal connection layer 107 above the surface of the passivation layer 104 are removed to form a first semiconductor structure, as shown in fig. 2 f.
In this step, the dielectric layer 105, the first electrode 106 and the metal connection layer 107 above the surface of the passivation layer 104 are removed by, for example, chemical mechanical polishing, so that the surface of the passivation layer 104 is exposed and planarized.
And as shown in fig. 2f, the fabrication of a plurality of micro-LEDs in a micro-LED wafer is completed.
Further, the first semiconductor structure is bonded to the second semiconductor structure, as shown in fig. 2 g.
In this step, the second semiconductor structure includes a second substrate 200, a control unit 109 on the second substrate 200, and a bonding layer 108 on the control unit 109.
In this embodiment, the bonding layer 108 formed at each pad position of the control unit 109 bonds the second semiconductor structure with the previously formed first semiconductor structure. Specifically, one control unit 109 includes two bonding layers 108, wherein the second bonding layer 108 is in contact with the first electrode 106 and the metal connection layer 107, and the first bonding layer 108 is in contact with the protection layer 104.
In this embodiment, the metal connection layer 107, the first electrode 106 and the dielectric layer 105 constitute a first electrode structure of the micro light emitting diode, and the protective layer 104, the mirror layer 103 and the second electrode 102 constitute a second electrode structure of the micro light emitting diode. The first bonding layer 108 is in contact with the second electrode structure through the protective layer 104, which is equivalent to a P electrode to be led out, and the second bonding layer 108 is in contact with the first electrode structure, which is equivalent to an N electrode to be led out.
In this embodiment, the second substrate 200 is, for example, a Si-CMOS control board or a TFT control board, the operation mode of the second substrate 200 is, for example, one of active or passive control, and the bonding layer 108 is, for example, one of metal films formed by single or multiple (binary, ternary, quaternary) metal components of Au, Ag, Cu, Pd, Sn, In, and has a thickness ranging from 0.5um to 5um, for example. The bonding of the second substrate 200 to the semiconductor structure formed in the preceding step is carried out at a temperature of 290 ℃.
Further, the first substrate 100 and the buffer layer 11 are removed, and a photonic crystal structure is formed on the surface of the unintentionally doped layer 12, as shown in fig. 2 h.
In this step, the first substrate 100 is peeled off from the epitaxial layer 101 using a single beam excimer laser having a square spot with a wavelength of 248nm and a side length of 50 to 100um, and the surface after peeling is treated with dilute hydrochloric acid to remove the buffer layer 11 and expose the surface of the unintentionally doped layer 12. The first substrate 100 in this embodiment is a sapphire substrate.
Further, a photonic crystal structure is formed on the surface of the unintentionally doped layer 12 using a nanoimprint process and a dry etching process. The photonic crystal structure is a microstructure with a periodic pattern, and the control of the light emitting direction is realized by utilizing the periodic change of the refractive index of materials and air.
In other embodiments, when the first substrate 100 is a Si substrate, a CMP process may be used to thin the first substrate 100 to a thickness of 50um, and the remaining first substrate 100 and the buffer layer 11 are etched and removed by a mixed acid of nitric acid and hydrofluoric acid, so as to expose the surface of the unintentional doping layer 12.
In other embodiments, the method further comprises treating the surface of the unintentional doped layer 12 with a heated KOH solution with a concentration ranging from 1 to 6mol/L to obtain a rough surface, thereby achieving the enhancement of the light extraction in the axial direction.
In other embodiments, the removing technique of the first substrate 100 further includes one or more process combinations of laser lift-off, chemical mechanical thinning, chemical wet etching, and electrochemical etching.
And further, the method also comprises the steps of electrifying to test the whole miniature LED display module, marking the defect position, bonding the defective miniature LED by using high-energy small-light-spot laser, supplementing the qualified miniature LED by using a high-precision manipulator, retesting and finishing the processing of the miniature LED display module. The application shows the structure and the manufacturing method of the micro light-emitting diode and the micro LED display module.
In this embodiment, the step of forming the micro LED display module is to form a micro LED wafer, bond the micro LED wafer and the control unit, and then perform processes such as cutting to form the micro LED display module.
In other embodiments, the micro LED wafer may be cut to obtain a plurality of micro LEDs, and then the micro LEDs are bonded to the control unit to form the micro LED display module.
According to the micro light-emitting diode, the metal connecting layer and the corresponding whole surface thinning treatment process are used for machining the micro light-emitting diode, the first electrode prepared on the whole surface of the side wall is combined to serve as the side wall high-reflection mirror, and the reflectivity is increased. Meanwhile, the surface micro-nano technology is adopted to realize the axial light-emitting enhancement of the micro LED display module, the optical crosstalk phenomenon of the micro LED display module in the display technology is improved, and higher contrast and better display effect are brought.
Compared with the existing micro light-emitting diode process, the manufacturing method of the micro light-emitting diode and the micro LED display module adopts the combination of twice photoetching and chemical mechanical grinding and thinning technology, realizes the processing of the micro light-emitting diode and the micro LED display module, replaces part of photoetching steps in the prior art with the chemical mechanical grinding and thinning technology, reduces photoetching times, improves the product process yield, greatly simplifies the process, improves the production efficiency and reduces the process manufacturing cost.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (47)

1. A micro light emitting diode, comprising:
the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer;
the second electrode is positioned on the surface of the second semiconductor layer in the epitaxial layer;
the reflecting mirror layer is positioned on the surface of the second electrode;
the protective layer is positioned on the surface of the reflector layer; and
a first electrode structure including a dielectric layer, a first electrode and a metal connection layer,
the first electrode structure penetrates through the protective layer, the reflector layer, the second electrode, the second semiconductor layer and the multi-quantum well layer, the first electrode in the first electrode structure is connected with the first semiconductor layer, and the first electrode and the metal connecting layer jointly serve as a conductive layer and a side wall reflecting layer;
the second electrode structure comprises the protective layer, the reflector layer and the second electrode, the first electrode structure is far away from the surface of the first semiconductor layer is flushed with the surface of the protective layer in the second electrode structure through a thinning process.
2. The micro light-emitting diode of claim 1, further comprising:
the epitaxial layer is positioned on the surface of the first substrate.
3. The micro light emitting diode of claim 1, wherein the epitaxial layers comprise, in order: the semiconductor device includes a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer.
4. The micro light-emitting diode of claim 1, wherein the first semiconductor layer is an N-doped layer and the second semiconductor layer is a P-doped layer.
5. The micro light-emitting diode of claim 1, wherein the cross-sectional shape of the first electrode structure is trapezoidal.
6. The micro light emitting diode of claim 3, wherein the dielectric layer is located on an outer sidewall of the first electrode to isolate the first electrode from the protective layer, the mirror layer, the second electrode, the second semiconductor layer, the electron blocking layer, and the MQW layer.
7. The micro light-emitting diode of claim 1, wherein the metal connection layer is located on an inner sidewall of the first electrode.
8. The micro light-emitting diode of claim 1, wherein the material of the metal connection layer comprises copper.
9. The micro light-emitting diode of claim 1, wherein the protective layer is a layer of a physico-chemically inert metal.
10. A manufacturing method of a micro light-emitting diode comprises the following steps:
sequentially forming an epitaxial layer, a second electrode, a reflector layer and a protective layer on a first substrate, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer;
photoetching the surface of the protective layer to form a walkway area;
etching the protective layer, the reflector layer, the second electrode and part of the epitaxial layer corresponding to the walkway area to form a groove exposing the first semiconductor layer;
forming a first electrode structure in the groove;
the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, the first electrode structure penetrates through the protective layer, the reflector layer, the second electrode, the second semiconductor layer and the multi-quantum well layer, the first electrode is connected with the first semiconductor layer, and the first electrode and the metal connecting layer are jointly used as a conductive layer and a side wall reflecting layer;
the second electrode structure comprises the protective layer, the reflector layer and the second electrode, the first electrode structure is far away from the surface of the first semiconductor layer is flushed with the surface of the protective layer in the second electrode structure through a thinning process.
11. The method of claim 10, wherein forming a first electrode structure within the recess comprises:
forming the dielectric layer on the surface of the protective layer and the surface of the groove, wherein the dielectric layer covers the side wall and the bottom of the groove;
photoetching the dielectric layer to expose the first semiconductor layer at the bottom of the groove;
sequentially forming the first electrode and the metal connecting layer on the dielectric layer and the first semiconductor layer, wherein the first electrode covers the side wall of the dielectric layer and the bottom of the groove, and the metal connecting layer covers the side wall of the first electrode;
and thinning part of the dielectric layer, the first electrode and the metal connecting layer to expose the protective layer.
12. The production method according to claim 10, wherein the sectional shape of the groove is a trapezoid.
13. The method of manufacturing of claim 10, wherein forming an epitaxial layer on a first substrate comprises:
a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer are sequentially formed on a first substrate.
14. The method of claim 10, wherein the first semiconductor layer is an N-type doped layer and the second semiconductor layer is a P-type doped layer.
15. The method of claim 10, wherein the first electrode is an N-type electrode and the second electrode is a P-type electrode.
16. The method of claim 10, wherein the protective layer is a layer of a metal that is physico-chemically inert.
17. The method of claim 10, wherein the material of the metal connection layer comprises copper.
18. A micro LED display module comprising:
a second substrate;
a plurality of control units on the second substrate;
a plurality of bonding layers on the control unit; and
a plurality of micro light emitting diodes bonded to the bonding layer, the micro light emitting diodes comprising:
the epitaxial layer sequentially comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer;
the second electrode is positioned on the surface of the second semiconductor layer in the epitaxial layer;
the reflecting mirror layer is positioned on the surface of the second electrode;
the protective layer is positioned on the surface of the reflector layer; and
a first electrode structure including a dielectric layer, a first electrode and a metal connection layer,
the first electrode structure penetrates through the protective layer, the mirror layer, the second electrode, the second semiconductor layer and the multi-quantum well layer, the first electrode in the first electrode structure is connected with the first semiconductor layer, and the first electrode and the metal connecting layer in the first electrode structure jointly serve as a conducting layer and a side wall reflecting layer;
the second electrode structure comprises the protective layer, the reflector layer and the second electrode, part of the bonding layer is in contact with the protective layer of the second electrode structure, part of the bonding layer is in contact with the first electrode structure, and the surface of the first electrode structure, which is far away from the first semiconductor layer, is flush with the surface of the protective layer in the second electrode structure through a thinning process.
19. The micro LED display module of claim 18, wherein the epitaxial layers comprise, in order: the semiconductor device includes a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer.
20. The micro LED display module of claim 18, wherein the first semiconductor layer is an N-doped layer and the second semiconductor layer is a P-doped layer.
21. The micro LED display module of claim 18, wherein the cross-sectional shape of the first electrode structure is trapezoidal.
22. The micro LED display module of claim 19, wherein the dielectric layer is located on an outer sidewall of the first electrode, and separates the first electrode from the protective layer, the mirror layer, the second electrode, the second semiconductor layer, the electron blocking layer, and the mqw layer.
23. The micro LED display module of claim 18, wherein the metal connection layer is located on an inner sidewall of the first electrode.
24. The micro LED display module of claim 18, wherein a portion of the bonding layer is in contact with a metal connection layer in the first electrode structure.
25. The micro LED display module of claim 18, wherein a portion of the bonding layer is in contact with the first electrode and the metal connection layer in the first electrode structure.
26. The micro LED display module of claim 18, wherein each of said control units is electrically connected to one of said micro light emitting diodes.
27. The micro LED display module of claim 19, wherein a surface of the unintentional doped layer is formed with a photonic crystal structure.
28. The micro LED display module of claim 19, wherein the surface of the unintentionally doped layer is a roughened surface.
29. The micro LED display module of claim 18, wherein the material of said metal connection layer comprises copper.
30. The micro LED display module of claim 18, wherein the protective layer is a layer of a physico-chemically inert metal.
31. A manufacturing method of a miniature LED display module comprises the following steps:
sequentially forming an epitaxial layer, a second electrode, a reflector layer and a protective layer on a first substrate, wherein the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer;
photoetching the surface of the protective layer to form a walkway area;
etching the protective layer, the reflector layer, the second electrode and part of the epitaxial layer corresponding to the walkway area to form a groove exposing the first semiconductor layer;
forming a first electrode structure in the groove to obtain a first semiconductor structure;
the first electrode structure comprises a dielectric layer, a first electrode and a metal connecting layer, the first electrode structure penetrates through the protective layer, the reflector layer, the second electrode, the second semiconductor layer and the multi-quantum well layer, the first electrode is connected with the first semiconductor layer, and the first electrode and the metal connecting layer are jointly used as a conductive layer and a side wall reflecting layer; the second electrode structure comprises the protective layer, the reflector layer and the second electrode, and the surface of the first electrode structure, which is far away from the first semiconductor layer, is flush with the surface of the protective layer in the second electrode structure through a thinning process;
bonding the first semiconductor structure with a second semiconductor structure, the second semiconductor structure comprising a second substrate, a plurality of control cells on the second substrate, and a plurality of bonding layers on the control cells;
and removing the first substrate.
32. The method of claim 31, wherein forming a first electrode structure within the recess comprises:
forming the dielectric layer on the surface of the protective layer and the surface of the groove, wherein the dielectric layer covers the side wall and the bottom of the groove;
photoetching the dielectric layer to expose the first semiconductor layer at the bottom of the groove;
sequentially forming the first electrode and the metal connecting layer on the dielectric layer and the first semiconductor layer, wherein the first electrode covers the side wall of the dielectric layer and the bottom of the groove, and the metal connecting layer covers the side wall of the first electrode;
and thinning part of the dielectric layer, the first electrode and the metal connecting layer to expose the protective layer.
33. The method of claim 31, wherein the cross-sectional shape of the groove is trapezoidal.
34. The method of fabricating of claim 31, wherein prior to the step of bonding the first semiconductor structure to the second semiconductor structure, further comprising:
and cutting the first semiconductor structure to obtain a plurality of micro light-emitting diodes.
35. The method of fabricating of claim 31, further comprising, after the step of bonding the first semiconductor structure to the second semiconductor structure:
and cutting the first semiconductor structure to obtain a plurality of micro light-emitting diodes.
36. The method of manufacturing of claim 34 or 35, wherein each of the control units is electrically connected to one of the micro light emitting diodes.
37. The method of fabricating of claim 31, wherein a portion of the bonding layer in a plurality of bonding layers on the control unit is in contact with the protective layer and a portion of the bonding layer is in contact with the first electrode structure.
38. The method of making as claimed in claim 37, wherein a portion of the bonding layer is in contact with a metal connection layer in the first electrode structure.
39. The method of making as claimed in claim 37, wherein a portion of the bonding layer is in contact with a first electrode and a metal connection layer in the first electrode structure.
40. The method of claim 31, wherein forming an epitaxial layer on the first substrate comprises:
a buffer layer, an unintentional doping layer, the first semiconductor layer, the multiple quantum well layer, an electron blocking layer, and the second semiconductor layer are sequentially formed on a first substrate.
41. The method of claim 31, wherein the first semiconductor layer is an N-doped layer and the second semiconductor layer is a P-doped layer.
42. The method of claim 31, wherein the first electrode is an N-type electrode and the second electrode is a P-type electrode.
43. The method of manufacturing of claim 40, further comprising, after the step of removing the first substrate:
and removing the buffer layer in the epitaxial layer.
44. The method of claim 43, further comprising, after the step of removing the buffer layer:
and forming a photonic crystal structure on the surface of the unintended doped layer.
45. The method of claim 43, further comprising, after the step of removing the buffer layer:
etching at the surface of the unintentionally doped layer roughens the surface of the unintentionally doped layer.
46. The method of claim 31, wherein the protective layer is a layer of a metal that is physico-chemically inert.
47. The method of claim 31, wherein the material of the metal connection layer comprises copper.
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