CN207782663U - A kind of constant pressure and flow mode switching circuit - Google Patents
A kind of constant pressure and flow mode switching circuit Download PDFInfo
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- CN207782663U CN207782663U CN201820146794.6U CN201820146794U CN207782663U CN 207782663 U CN207782663 U CN 207782663U CN 201820146794 U CN201820146794 U CN 201820146794U CN 207782663 U CN207782663 U CN 207782663U
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Abstract
The utility model discloses a kind of constant pressure and flow mode switching circuit, and chip U1 is internally integrated operational amplifier EA1, operational amplifier EA2, resistance R4, capacitance C2, BUFF module；Operational amplifier EA1, operational amplifier EA2 are electrically connected to the input terminal of BUFF modules through output end；The inverting input of operational amplifier EA1 is connected to FB pins, and output end is grounded after being also sequentially connected in series resistance R4, capacitance C2, uses resistance R4 and capacitance C2 as the compensation network of constant voltage mode；The inverting input of operational amplifier EA2 is connected to CS pins.The utility model is simple in structure, is readily processible to integrated switching circuit, and both of which can realize seamless switching, and stability is strong, at low cost.
Description
Technical field
The utility model is related to electronic technology field more particularly to a kind of constant pressure and flow mode switching circuits.
Background technology
In order to ensure that constant pressure and flow loop is in buck converter vehicle charging source control core to the safety of charging mobile phone battery
Using quite extensively in piece.But existing switch mode mode is relatively more fixed, by Voltage loop error amplifier and electric current loop error
Amplifier is connected to identical exit point, by changing the voltage of this endpoint, is modulated to the peak point current of inductance, to
Realize the switching of constant pressure and flow pattern.
Mainly there are two disadvantages for switching circuit in this way：
1) when system enters constant current mode, constant voltage mode is still working, and the stability of two patterns will be examined at this time
Consider, design is more complicated above；
2) in order to ensure that constant pressure and flow both of which can work normally, generally one can be arranged in charging source managing chip
A concatenated resistance and capacitance carry out loop compensation, and corresponding resistance is compensation resistance, tens kilohms of ranks, corresponding volume electricity
Hold is compensating electric capacity, a few to tens of nanofarad ranks.In this way, system requires to compare to the choosing value of resistance in loop compensation and capacitance
Height, underaction, and resistance in the circuit and capacitance are comparatively larger, if it is desired to resistance and capacitance are built into chip
The inside, difficulty is larger, is unfavorable for integra-tion application.
In summary, there is inconvenience in the constant pressure and flow mode switching circuit, it is therefore necessary to be subject in practice
It improves.
Utility model content
The purpose of this utility model is to provide a kind of constant pressure and flow mode switching circuit, simple in structure, is readily processible to
Integrated switching circuit, both of which can realize seamless switching, and stability is strong, at low cost.
To achieve the above object, using following technical scheme：
A kind of constant pressure and flow mode switching circuit, including chip U1, inductance L1, resistance R1, resistance R2, resistance R3, capacitance
C1；One end of the inductance L1 and the SW pins of chip U1 are electrically connected, the other end respectively with the one end resistance R1, the one end capacitance C1
It is electrically connected；The resistance R1 other ends are electrically connected with the FB pins of the one end resistance R2, chip U1 respectively；The resistance R2's
The other end, capacitance C1 the other end be grounded；The one end the resistance R3 and the CS pins of chip U1 are electrically connected, another termination
Ground；The VIN pins of the chip U1 are electrically connected external power supply, GND pin ground connection；The chip U1 is internally integrated operation amplifier
Device EA1, operational amplifier EA2, resistance R4, capacitance C2, BUFF module；The operational amplifier EA1, operational amplifier EA2 are equal
The input terminal of BUFF modules is electrically connected to through output end；The inverting input of the operational amplifier EA1 is connected to FB pins,
Its output end is grounded after being also sequentially connected in series resistance R4, capacitance C2；The inverting input of the operational amplifier EA2 is connected to CS and draws
Foot.
Preferably, the BUFF modules include current source Is1, transistor Q3, transistor Q4, transistor Q5, transistor Q6,
Transistor Q7；The output end of the current source Is1 respectively with the source electrode of transistor Q3, the source electrode of transistor Q4, transistor Q5
Source electrode is electrically connected；The grid of the transistor Q3 is electrically connected with the output end of operational amplifier EA1；The transistor Q4's
The output end of grid and operational amplifier EA2 is electrically connected；The drain electrode of the transistor Q3, the drain electrode of transistor Q4 are electrically connected
It is electrically connected respectively with the drain electrode of transistor Q6 afterwards；The grid of the transistor Q6 and drain electrode are electrically connected；The transistor Q5
Drain electrode and grid be electrically connected；The drain electrode of the transistor Q7 is electrically connected with the drain electrode of transistor Q5, grid and crystal
The grid of pipe Q6 is electrically connected；The source electrode of the transistor Q6, the source grounding of transistor Q7.
Preferably, the BUFF modules include current source Is2, current source Is3, transistor Q8, transistor Q9, transistor
Q10, transistor Q11, transistor Q12, transistor Q13；The output end of the current source Is2 respectively with the source electrode of transistor Q8,
The source electrode of transistor Q9, the source electrode of transistor Q10 are electrically connected；The grid of the transistor Q8 is defeated with operational amplifier EA1's
Outlet is electrically connected；The grid of the transistor Q9 is electrically connected with the grid of operational amplifier EA2；The current source Is3's
Output end is electrically connected with the drain electrode of the grid of transistor Q10, transistor Q11 respectively；The drain electrode of the transistor Q8, transistor
The drain electrode of Q9 is electrically connected with the grid of the drain electrode of transistor Q12, transistor Q11 respectively after being electrically connected；The transistor Q10
The drain electrode of drain electrode and transistor Q13 be electrically connected；The drain and gate of the transistor Q13 is electrically connected；The transistor
The grid of Q12 is electrically connected with the grid of transistor Q13；The source electrode of the transistor Q11, source electrode, the transistor of transistor Q11
The source grounding of Q13.
Preferably, be also integrated with inside the chip U1 comparator COMP, OSC module, LOGIC modules, DRIVER modules,
Transistor Q1, transistor Q2；The inverting input of the comparator COMP is electrically connected with the output end of BUFF modules, comparator
The output end of COMP is connected to DRIVER modules one end after being electrically connected with LOGIC modules；The DRIVER modules other end point
It is not electrically connected with the grid of the grid of transistor Q1, transistor Q2；The source electrode of the transistor Q1 is connected to pin VIN,
Drain electrode and the drain electrode of transistor Q2 are then connected to SW pins after being electrically connected；The source electrode of the transistor Q2 is grounded；The OSC moulds
Block is electrically connected with LOGIC modules.
Preferably, the transistor Q3, transistor Q4, transistor Q5 are PMOS tube；The transistor Q6, transistor Q7
It is NMOS tube.
Preferably, the transistor Q8, transistor Q9, transistor Q10 are PMOS tube；The transistor Q11, transistor
Q12, transistor Q13 are NMOS tube.
Preferably, the transistor Q1 is PMOS tube；The transistor Q2 is NMOS tube.
Using the above scheme, the utility model has the beneficial effects that：
Circuit structure is simple, is readily processible to integrated switching circuit, and the stability of both of which is strong, it can be achieved that constant pressure
The seamless switching of pattern and constant current mode, it is at low cost.
Description of the drawings
Fig. 1 is the circuit diagram of the utility model；
Fig. 2 is BUFF module circuit diagrams in the embodiments of the present invention 1；
Fig. 3 is BUFF module circuit diagrams in the embodiments of the present invention 2；
Fig. 4 is the input and output voltage oscillogram of the BUFF modules of the utility model；
Specific implementation mode
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail.
Shown in 3, the utility model provides a kind of constant pressure and flow mode switching circuit, including chip U1, inductance
L1, resistance R1, resistance R2, resistance R3, capacitance C1；One end of the inductance L1 is electrically connected with the SW pins of chip U1, another
End is electrically connected with the one end resistance R1, the one end capacitance C1 respectively；The resistance R1 other ends respectively with the one end resistance R2, chip U1
FB pins be electrically connected；The other end of the resistance R2, the other end of capacitance C1 are grounded；The one end the resistance R3 and chip
The CS pins of U1 are electrically connected, other end ground connection；The VIN pins of the chip U1 are electrically connected external power supply, and GND pin connects
Ground；The chip U1 is internally integrated operational amplifier EA1, operational amplifier EA2, resistance R4, capacitance C2, BUFF module；It is described
Operational amplifier EA1, operational amplifier EA2 are electrically connected to the input terminal of BUFF modules through output end；The operation amplifier
The inverting input of device EA1 is connected to FB pins, and output end is grounded after being also sequentially connected in series resistance R4, capacitance C2；The operation
The inverting input of amplifier EA2 is connected to CS pins.
Embodiment 1：
The BUFF modules include current source Is1, transistor Q3, transistor Q4, transistor Q5, transistor Q6, transistor
Q7；The output end of the current source Is1 is electric with the source electrode of the source electrode of transistor Q3, the source electrode of transistor Q4, transistor Q5 respectively
Property connection；The grid of the transistor Q3 is electrically connected with the output end of operational amplifier EA1；The grid of the transistor Q4 with
The output end of operational amplifier EA2 is electrically connected；The drain electrode of the transistor Q3, the drain electrode of transistor Q4 are distinguished after being electrically connected
Drain electrode with transistor Q6 is electrically connected；The grid of the transistor Q6 and drain electrode are electrically connected；The drain electrode of the transistor Q5
It is electrically connected with grid；The drain electrode of the transistor Q7 is electrically connected with the drain electrode of transistor Q5, and grid is with transistor Q6's
Grid is electrically connected；The source electrode of the transistor Q6, the source grounding of transistor Q7.The transistor Q3, transistor Q4, crystalline substance
Body pipe Q5 is PMOS tube；The transistor Q6, transistor Q7 are NMOS tube.
Embodiment 2：
The BUFF modules include current source Is2, current source Is3, transistor Q8, transistor Q9, transistor Q10, crystal
Pipe Q11, transistor Q12, transistor Q13；The output end of the current source Is2 respectively with the source electrode of transistor Q8, transistor Q9
Source electrode, transistor Q10 source electrode be electrically connected；The output end of the grid and operational amplifier EA1 of the transistor Q8 is electrical
Connection；The grid of the transistor Q9 is electrically connected with the grid of operational amplifier EA2；The output end of the current source Is3 point
It is not electrically connected with the drain electrode of the grid of transistor Q10, transistor Q11；The drain electrode of the transistor Q8, the drain electrode of transistor Q9
It is electrically connected respectively with the grid of the drain electrode of transistor Q12, transistor Q11 after electric connection；The drain electrode of the transistor Q10 with
The drain electrode of transistor Q13 is electrically connected；The drain and gate of the transistor Q13 is electrically connected；The grid of the transistor Q12
It is electrically connected with the grid of transistor Q13；The source electrode of the source electrode of the transistor Q11, the source electrode of transistor Q11, transistor Q13
It is grounded.The transistor Q8, transistor Q9, transistor Q10 are PMOS tube；The transistor Q11, transistor Q12, crystal
Pipe Q13 is NMOS tube.
To sum up, be also integrated with inside chip U1 described in embodiment 1-2 comparator COMP, OSC module, LOGIC modules,
DRIVER modules, transistor Q1, transistor Q2；The inverting input and the output end of BUFF modules of the comparator COMP is electrical
Connection is connected to DRIVER modules one end after the output end of comparator COMP and the electric connection of LOGIC modules；The DRIVER moulds
The block other end is electrically connected with the grid of the grid of transistor Q1, transistor Q2 respectively；The source electrode of the transistor Q1 is connected to
The drain electrode of pin VIN, drain electrode and transistor Q2 are then connected to SW pins after being electrically connected；The source electrode of the transistor Q2 connects
Ground；The OSC modules are electrically connected with LOGIC modules.The transistor Q1 is PMOS tube；The transistor Q2 is NMOS tube.
Utility model works principle：
Operational amplifier EA1, operational amplifier EA2 in chip U1 are exported to BUFF modules, and BUFF modules are used as and follow
Device；LOGIC modules control the work of entire chip other component as Logic control module, and OSC modules are exported as oscillator
To LOGIC modules；DRIVER modules receive the control instruction of LOGIC modules to driving transistor Q1, crystal as driver
The work of pipe Q2.
As shown in Figure 1, being the device of chip U1 in dotted line frame in figure, use resistance R4 and capacitance C2 as the benefit of constant voltage mode
Network is repaid, the output end series resistance R4 and capacitance C2 of operational amplifier EA1, resistance R4 is about hundreds of kilohms here, and
Capacitance C2 only has tens pico farads.Resistance R4 compared with prior art in external compensation resistance for the order of magnitude it is similar, but it is electric
For external compensating electric capacity in holding C2 compared with prior art, capacitance is 50~100 times small, is very easy to be integrated into chip U1
Portion.In addition, constant current mode does not need any compensation network (output of operational amplifier EA2 does not have to what additional circuit taken over) then,
And increased inside chip U1 is only a BUFF module.
As shown in Fig. 2, it is the BUFF modules in embodiment 1, transistor Q3 (PMOS tube), transistor Q4 (PMOS tube),
Transistor Q5's (PMOS tube) is equal sized, transistor Q6 (NMOS tube), transistor Q7 (NMOS tube) it is equal sized.In figure
IN1 terminates the output end of operational amplifier EA1, and IN2 terminates the output end of operational amplifier EA2.Work as VIN1>When=VIN2,
VOUT=VIN2；Work as VIN1<When VIN2, VOUT=VIN1.The output voltage of VOUT is followed by smaller in VIN1 and VIN2 always
Value.The voltage value of VIN1 is control constant voltage mode, and the voltage value of VIN2 is control constant current mode.VOUT is output voltage, is used
To control inductive current size.
As shown in figure 3, it is the BUFF modules in embodiment 2, the output end of the IN1 termination operational amplifiers EA1 in figure,
IN2 terminates the output end of operational amplifier EA2.Transistor Q8 (PMOS tube), transistor Q9 (PMOS tube), transistor Q10 (PMOS
Pipe) it is equal sized, transistor Q12 (NMOS tube), transistor Q13 (NMOS tube) it is equal sized.
As shown in figure 4, OUT output voltages are indicated with solid black lines, IN1 is the input of constant voltage mode, and IN2 is constant current mode
Input, constant current mode and constant voltage mode can be with bumpless transfers (OUT output voltages do not break), to ring after BUFF is handled
Road stability does not have any influence.
The above is only the preferred embodiments of the present utility model only, is not intended to limit the utility model, all in this practicality
All any modification, equivalent and improvement etc., should be included in the guarantor of the utility model made by within novel spirit and principle
Within the scope of shield.
Claims (7)
1. a kind of constant pressure and flow mode switching circuit, which is characterized in that including chip U1, inductance L1, resistance R1, resistance R2, electricity
Hinder R3, capacitance C1；One end of the inductance L1 and the SW pins of chip U1 are electrically connected, the other end respectively with the one end resistance R1,
The one end capacitance C1 is electrically connected；The resistance R1 other ends are electrically connected with the FB pins of the one end resistance R2, chip U1 respectively；Institute
The other end of the other end, capacitance C1 of stating resistance R2 is grounded；The one end the resistance R3 and the CS pins of chip U1 are electrically connected,
The other end is grounded；The VIN pins of the chip U1 are electrically connected external power supply, GND pin ground connection；The chip U1 is internally integrated
Operational amplifier EA1, operational amplifier EA2, resistance R4, capacitance C2, BUFF module；The operational amplifier EA1, operation amplifier
Device EA2 is electrically connected to the input terminal of BUFF modules through output end；The inverting input of the operational amplifier EA1 is connected to
FB pins, output end are grounded after being also sequentially connected in series resistance R4, capacitance C2；The inverting input of the operational amplifier EA2 connects
It is connected to CS pins.
2. constant pressure and flow mode switching circuit according to claim 1, which is characterized in that the BUFF modules include electric current
Source Is1, transistor Q3, transistor Q4, transistor Q5, transistor Q6, transistor Q7；The output end of the current source Is1 is distinguished
It is electrically connected with the source electrode of the source electrode of transistor Q3, the source electrode of transistor Q4, transistor Q5；The grid and fortune of the transistor Q3
The output end for calculating amplifier EA1 is electrically connected；The grid of the transistor Q4 electrically connects with the output end of operational amplifier EA2
It connects；The drain electrode of the transistor Q3, the drain electrode of transistor Q4 are electrically connected with the drain electrode of transistor Q6 respectively after being electrically connected；Institute
The grid and drain electrode for stating transistor Q6 are electrically connected；The drain electrode of the transistor Q5 is electrically connected with grid；The transistor Q7
The drain electrode of drain electrode and transistor Q5 be electrically connected, the grid of grid and transistor Q6 is electrically connected；The transistor Q6's
The source grounding of source electrode, transistor Q7.
3. constant pressure and flow mode switching circuit according to claim 1, which is characterized in that the BUFF modules include electric current
Source Is2, current source Is3, transistor Q8, transistor Q9, transistor Q10, transistor Q11, transistor Q12, transistor Q13；Institute
Source electrode of the output end of current source Is2 respectively with the source electrode of transistor Q8, the source electrode of transistor Q9, transistor Q10 is stated electrically to connect
It connects；The grid of the transistor Q8 is electrically connected with the output end of operational amplifier EA1；The grid of the transistor Q9 and operation
The grid of amplifier EA2 is electrically connected；The output end of the current source Is3 respectively with the grid of transistor Q10, transistor Q11
Drain electrode be electrically connected；Leakage with transistor Q12 respectively after the drain electrode of the transistor Q8, the drain electrode of transistor Q9 are electrically connected
The grid electric connection of pole, transistor Q11；The drain electrode of the transistor Q10 is electrically connected with the drain electrode of transistor Q13；It is described
The drain and gate of transistor Q13 is electrically connected；The grid of the transistor Q12 is electrically connected with the grid of transistor Q13；Institute
State the source grounding of the source electrode of transistor Q11, the source electrode of transistor Q11, transistor Q13.
4. constant pressure and flow mode switching circuit according to claim 1, which is characterized in that also integrated inside the chip U1
There are comparator COMP, OSC module, LOGIC modules, DRIVER modules, transistor Q1, transistor Q2；The comparator COMP's
Inverting input and the output end of BUFF modules are electrically connected, after output end and LOGIC the modules electric connection of comparator COMP
It is connected to DRIVER modules one end；The DRIVER modules other end respectively with the grid of transistor Q1, the grid of transistor Q2
It is electrically connected；The source electrode of the transistor Q1 is connected to pin VIN, and the drain electrode with transistor Q2 that drains connects again after being electrically connected
It is connected to SW pins；The source electrode of the transistor Q2 is grounded；The OSC modules are electrically connected with LOGIC modules.
5. constant pressure and flow mode switching circuit according to claim 2, which is characterized in that the transistor Q3, transistor
Q4, transistor Q5 are PMOS tube；The transistor Q6, transistor Q7 are NMOS tube.
6. constant pressure and flow mode switching circuit according to claim 3, which is characterized in that the transistor Q8, transistor
Q9, transistor Q10 are PMOS tube；The transistor Q11, transistor Q12, transistor Q13 are NMOS tube.
7. constant pressure and flow mode switching circuit according to claim 4, which is characterized in that the transistor Q1 is PMOS
Pipe；The transistor Q2 is NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820146794.6U CN207782663U (en) | 2018-01-29 | 2018-01-29 | A kind of constant pressure and flow mode switching circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820146794.6U CN207782663U (en) | 2018-01-29 | 2018-01-29 | A kind of constant pressure and flow mode switching circuit |
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| Publication Number | Publication Date |
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| CN207782663U true CN207782663U (en) | 2018-08-28 |
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| CN201820146794.6U Active CN207782663U (en) | 2018-01-29 | 2018-01-29 | A kind of constant pressure and flow mode switching circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109149935A (en) * | 2018-09-07 | 2019-01-04 | 深圳市德赛微电子技术有限公司 | A kind of control circuit of Switching Power Supply different working modes free switching |
| CN110429687A (en) * | 2019-08-26 | 2019-11-08 | 无锡烽合健行科技有限公司 | A kind of battery charging management circuit |
| CN113972629A (en) * | 2021-11-05 | 2022-01-25 | 深圳市卓芯微科技有限公司 | ACDC converter and management chip thereof |
| CN115224940A (en) * | 2022-07-22 | 2022-10-21 | 厦门英麦科芯集成科技有限公司 | Constant-current constant-voltage output circuit and power supply chip |
-
2018
- 2018-01-29 CN CN201820146794.6U patent/CN207782663U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109149935A (en) * | 2018-09-07 | 2019-01-04 | 深圳市德赛微电子技术有限公司 | A kind of control circuit of Switching Power Supply different working modes free switching |
| CN109149935B (en) * | 2018-09-07 | 2020-10-23 | 深圳市德赛微电子技术有限公司 | Control circuit for freely switching different working modes of switching power supply |
| CN110429687A (en) * | 2019-08-26 | 2019-11-08 | 无锡烽合健行科技有限公司 | A kind of battery charging management circuit |
| CN110429687B (en) * | 2019-08-26 | 2023-10-31 | 无锡烽合健行科技有限公司 | Battery charging management circuit |
| CN113972629A (en) * | 2021-11-05 | 2022-01-25 | 深圳市卓芯微科技有限公司 | ACDC converter and management chip thereof |
| CN115224940A (en) * | 2022-07-22 | 2022-10-21 | 厦门英麦科芯集成科技有限公司 | Constant-current constant-voltage output circuit and power supply chip |
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Address after: 518000 15c05, 15th floor, Shenye Tairan building, Tairan 8th Road, chegong temple, Shatou street, Futian District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Weiyuan Semiconductor Co.,Ltd. Address before: 518000 15c05, 15th floor, Shenye Tairan building, Tairan 8th Road, chegong temple, Shatou street, Futian District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN INNOVATION LOWPOWER SEMICONDUCTOR Co.,Ltd. |