CN207781576U - A kind of chip-packaging structure - Google Patents
A kind of chip-packaging structure Download PDFInfo
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- CN207781576U CN207781576U CN201721795133.8U CN201721795133U CN207781576U CN 207781576 U CN207781576 U CN 207781576U CN 201721795133 U CN201721795133 U CN 201721795133U CN 207781576 U CN207781576 U CN 207781576U
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- layer
- chip
- packing colloid
- metallic radiating
- pin
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
A kind of chip-packaging structure is disclosed, including, metallic radiating layer；Chip structure, is located at the upper surface of metallic radiating layer, and chip structure includes multiple first electric contacts positioned at upper surface；Pin layer, including multiple second electric contacts and the metal derby of multiple separation, multiple second electric contacts are located at the lower surface of metal derby, and multiple second electric contacts are coupled to multiple first electric contacts of chip structure by multiple conductive columns；And packing colloid, envelope chip structure, the metallic radiating layer and pin layer at least partly, pin layer is at least partly exposed to the upper surface of packing colloid, and the lower surface of metallic radiating layer is exposed to outside packing colloid.The side of metallic radiating layer includes flange, for metallic radiating layer and packing colloid to be combined closely.It using the technology mode of graphic plating, forms pin layer or is formed in distribution layer, under the premise of ensureing chip-packaging structure performance, enable to manufacturing process easy, to reduce manufacturing cost.
Description
Technical field
The utility model is related to technical field of semiconductors, relate more specifically to a kind of chip-packaging structure.
Background technology
In the chip structure of the prior art, generally it is packaged using wire bonding structure or inverted structure, not
Heat dissipation design only relies on approach of the chip with extraneous contact as natural heat dissipation.It is advanced however as the progress of science and technology
Technique can produce the smaller and more complicated chip of function, therefore the pin spacing of chip package opposite must reduce.Relatively
For, the thermal energy for the chip running generation that each pin must endure as increases.After long-time service, pin accumulates a large amount of thermal energy
The normal operation of chip will be destroyed.Typical damage is that pin easy tos produce electron transfer phenomenon.In addition, using wire bonding knot
Structure or inverted structure are packaged manufacturing process complexity, to which manufacturing cost is relatively high.
Therefore, it for the progress of semiconductor technology, provides a kind of with high cooling efficiency and the simple core of manufacturing process
Chip package is vital.
Utility model content
The utility model solves the problems, such as to be to provide a kind of chip-packaging structure and its manufacturing method, using graphic plating
Technology mode, formed pin layer or formed redistributing layer enabled under the premise of ensureing chip-packaging structure performance
Manufacturing process is easy, to reduce manufacturing cost.
According to a kind of chip-packaging structure provided by the utility model, wherein including metallic radiating layer；Chip structure, position
In the upper surface of the metallic radiating layer, the chip structure includes multiple first electric contacts positioned at upper surface；Pin layer, packet
Multiple second electric contacts and the metal derby of multiple separation are included, the multiple second electric contact is located at the following table of the metal derby
Face, multiple second electric contacts are coupled to multiple first electric contacts of the chip structure by multiple conductive columns；With
And packing colloid, envelope the chip structure, the metallic radiating layer and the pin layer at least partly, the pin
Layer is at least partly exposed to the upper surface of the packing colloid, and the lower surface of the metallic radiating layer is exposed to the packing colloid
It is external.
Preferably, the side of the metallic radiating layer includes flange.
Preferably, the flange of the metallic radiating layer extends along the direction perpendicular to the side of the metallic radiating layer, institute
Flange is stated to be located in the packing colloid.
Preferably, the flange of the metallic radiating layer extends along the direction for the side for being parallel to the metallic radiating layer, institute
State the side that flange surrounds the packing colloid.
Preferably, further include sealing pin, be located at the upper surface of the flange, and extend to the packing colloid upper table
The periphery in face so that the metallic radiating layer, the flange and the sealing pin form the cavity for accommodating packing colloid.
Preferably, the upper surface with the upper surface of the pin layer of the sealing pin is highly consistent.
Preferably, further include：Redistributing layer, between the chip structure and the pin layer, the redistributing layer
Direction along the upper surface for being parallel to the chip structure extends, and the redistributing layer will be located at the core by the conductive column
First electric contact at chip architecture upper surface center and second electrical contact couples of the pin layer, second electricity touch
Top of the point positioned at the top at the chip structure center or positioned at the chip structure edge.
Preferably, the multiple conductive column includes：First conductive column, first conductive column will be under the redistributing layers
Surface is electrically coupled with the chip structure；And second conductive column, second conductive column is by the upper surface of the redistributing layer
It is electrically coupled with surface below the pin layer.
Preferably, further include：Insulating layer is located at the lower surface of the metallic radiating layer.
Preferably, the upper surface of the metallic radiating layer is connect with the chip structure by adhesive layer.
Preferably, the packing colloid includes the first packing colloid and the second packing colloid, second packing colloid
On first packing colloid, first packing colloid coats the chip structure and the metallic radiating layer, institute
It states the second packing colloid and coats the redistributing layer.
Chip-packaging structure according to the present utility model by using graphic plating technology mode, formed pin layer or
It is formed in distribution layer, under the premise of ensureing chip-packaging structure performance, enables to manufacturing process easy, to reduce manufacture
Cost.Metallic radiating layer below chip structure is at least partly exposed to except packing colloid, can make entire core
The heat dissipation of chip package improves.Extended along the direction for the upper surface for being parallel to chip structure through redistributing layer, quite
In the laying area for increasing electrode；Chip electrode is led to the top at chip structure edge so that external pin is mutual
Spacing increase, it is not easy to be in contact equal abnormal accidents and chip-packaging structure caused to can not work normally.
In one embodiment in the utility model, metallic radiating layer setting is along perpendicular to the side of the metallic radiating layer
Direction extend flange so that heat dissipation metal surface layer increase, can not only further increase chip-packaging structure dissipate
Hot property, and the binding force of metallic radiating layer and packing colloid can be reinforced.
In another embodiment in the utility model, the edge edge of metallic radiating layer is parallel to the metallic radiating layer
The flange that the direction of side extends, flange surround the side of packing colloid, and metallic radiating layer, flange and sealing pin form and hold
It receives the cavity of packing colloid, can not only further increase the heat dissipation performance of chip-packaging structure, but also metal can be reinforced and dissipated
The binding force of thermosphere and packing colloid.In addition, the sealing ring that metallic radiating layer, flange and sealant are formed can obtain well
Capability of electromagnetic shielding and airtight protective value.In the application scenario that needs are electromagnetically shielded, the prior art can be replaced extensively
In Can and ceramic cartridge encapsulation.
Description of the drawings
By referring to the drawings to the description of the utility model embodiment, above-mentioned and other mesh of the utility model
, feature and advantage will be apparent from.
Fig. 1 a show the sectional view of the chip-packaging structure of the first embodiment of the utility model；
Fig. 1 b to Fig. 1 j show each rank of the making method for chip encapsulation structure of the different first embodiment of the utility model
The sectional view of section；
Fig. 2 a show the sectional view of the chip-packaging structure of the second embodiment of the utility model；
Fig. 2 b to Fig. 2 i show each stage of the making method for chip encapsulation structure of the second embodiment of the utility model
Sectional view.
Specific implementation mode
Hereinafter reference will be made to the drawings is more fully described the utility model.In various figures, identical element is using similar
Reference numeral indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.In addition, may in figure
Certain well known parts are not shown.
Many specific details of the utility model, such as the structure of component, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand,
The utility model can not be realized according to these specific details.
It should be appreciated that when describing the structure of component, it is known as positioned at another floor, another area when by a floor, a region
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also include other layers or region between a region.Also, if by part turnover, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If, herein will be using " A is directly on B in order to describe located immediately at another layer, another region above scenario
The form of presentation of face " or " A is on B and abuts therewith ".In this application, " A is in B " indicates that A is located in B, and
And A and B is abutted directly against rather than A is located in the doped region formed in B.
In this application, term " semiconductor structure " refers to entire half formed in each step of manufacture semiconductor devices
The general designation of conductor structure, including all layers formed or region.Term " being laterally extended " refers to along being approximately perpendicular to ditch
The direction in groove depth direction extends.
Many specific details of the utility model, such as the structure of device, material, size, place are described hereinafter
Science and engineering skill and technology, to be more clearly understood that the utility model.But just as the skilled person will understand,
The utility model can not be realized according to these specific details
The utility model can be presented in a variety of manners, some of them example explained below.
Fig. 1 a show the sectional view of the chip-packaging structure of the first embodiment of the utility model.
A referring to Fig.1, chip structure 140 are located at the upper surface of metallic radiating layer 120, by adhesive layer 130 by chip structure
140 affix to the upper surface of metallic radiating layer 120.Chip structure 140 includes multiple first electric contacts 141 positioned at upper surface.
Redistributing layer 170 is located on chip structure 140, passes through 141 electricity of the first electric contact of multiple conductive columns 180 and chip structure 140
Coupling.Pin layer 150 is located on redistributing layer 170, and pin layer 150 includes multiple metal derbies and multiple second electric contacts 151,
Multiple second electric contacts 151 are located at the lower surface of multiple metal derbies, and multiple second electric contacts 151 pass through 180 electricity of multiple conductive columns
It is coupled to the upper surface of redistributing layer 170.Redistributing layer 170 extends along the direction for the upper surface for being parallel to chip structure 140, then
Distribution layer 170 will be positioned at first electric contact 141 and pin layer 150 at 140 upper surface center of chip structure by conductive column 180
Second electric contact 151 couples, and the second electric contact 151 is located at the top at 140 center of chip structure or is located at 140 side of chip structure
The top of edge.Wherein, multiple conductive columns 180 include the first conductive column 180a and the second conductive column 180b, the first conductive column
The lower surface of redistributing layer 170 and chip structure 140 are electrically coupled by 180a, and the second conductive column 180b is by the upper of redistributing layer 170
Surface is electrically coupled with surface below pin layer 150.Packing colloid 160 envelopes chip structure 140, metallic radiating layer 120, again
At least partly, wherein pin layer 150 is at least partly exposed to the upper table of packing colloid 160 for distribution layer 170 and pin layer 150
The lower surface in face, metallic radiating layer 120 is exposed to outside packing colloid 160.Specifically, packing colloid 160 includes the first encapsulation
Colloid 160a and the second packing colloid 160b, the second packing colloid 160b are located on the first packing colloid 160a, the first encapsulation
Colloid 160a coating chips structure 140 and metallic radiating layer 120 at least partly, described in the second packing colloid 160b cladding
Redistributing layer 170.
Extended along the direction for the upper surface for being parallel to chip structure 140 through redistributing layer 170, equivalent to increase electrode
Laying area；Chip electrode is led to the top at 140 edge of chip structure so that the mutual spacing of external pin increases
Greatly, it is not easy to be in contact equal abnormal accidents and chip-packaging structure is caused to can not work normally.
Redistributing layer 170 in the present embodiment is selectable structure, if being not provided with redistributing layer in the present embodiment
170, chip structure 140 can be directly electrically coupled with the second electric contact 151 of pin layer 150 by multiple conductive columns 180.
The side of metallic radiating layer 120 includes flange 121, and flange 121 is along the side perpendicular to the side of metallic radiating layer 120
To extension, flange 121 is located in the packing colloid 160, for metallic radiating layer 120 and packing colloid 160 to be combined closely.
The flange 121 of metallic radiating layer 120 can be two in the present embodiment, are distributed up and down, and groove is formed between two flanges 121, recessed
It can be full of packing colloid 160 in slot, further increase the thermal diffusivity and enhancing metallic radiating layer 120 of the chip-packaging structure
With 160 binding force of packing colloid.
Fig. 1 b to Fig. 1 j show each stage of the making method for chip encapsulation structure of the first embodiment of the utility model
Sectional view.
As shown in Figure 1 b, metallic radiating layer 120 is affixed to the upper surface of substrate 110 by adhesive linkage.Metallic radiating layer
120 include the flange 121 positioned at side, and flange 121 is along the direction extension perpendicular to the side of metallic radiating layer 120, flange 121
Development length be no more than substrate 110 side.Metallic radiating layer 120 in the present embodiment may be used copper, aluminium or other
Suitable material is made.
Then, as illustrated in figure 1 c, chip structure 140 is affixed to the upper table of metallic radiating layer 120 by adhesive linkage 130
Face.The upper surface of chip structure 140 has multiple electrodes connection structure, for drawing the electrode of chip outward.Electrode connects
The structure and composition part of structure can be diversified forms.In the present embodiment, electrode connecting structure includes being located at upper surface
Multiple first electric contacts 141 and it is placed on multiple first conductive column 180a on the first electric contact 141.Wherein, adhesive layer 130
Can be insulation adhesive, the material of insulation bonding can be epoxy resin, which may be used gluing process
(Dispensing) it is formed in the upper of metallic radiating layer 120, the epoxy resin of formation has certain thickness, so that it is guaranteed that the core
The performance of piece；Adhesive layer 130 can also be that conductive adhesives is made, and is electrically connected with metallic radiating layer 120, and
With good thermal diffusivity.
Then, as shown in Figure 1 d, the first packing colloid 160a is formed, the upper surface and metal for enveloping substrate 110 dissipate
The whole of thermosphere 120, chip structure 140, multiple first conductive column 180a.Wherein, the first packing colloid 160a materials can be
Polyimides, silica gel or epoxy modeling fat or other suitable materials；First packing colloid 160a, which may be used, to be compressed into
Type technique, transfer shaping technology, hydraulic seal moulding process or other suitable techniques are made.
Then, as shown in fig. le, using mechanical treatment, such as the modes such as grinding or drilling, chip structure 140 will be located at
The upper surface of multiple first conductive column 180a of upper surface is exposed to the upper surface of the first packing colloid 160a, and multiple first
The upper surface of conductive column 180a and the upper surface of the first packing colloid 160a are generally aligned in the same plane.
Then, as shown in Figure 1 f, using graphic plating or other it is suitable by the way of, multiple first conductive column 180a's
Upper surface and the upper surface of the first packing colloid 160a form redistributing layer 170 so that chip structure 140 passes through multiple first
Conductive column 180a and the lower surface of redistributing layer 170 are electrically coupled.Either using graphic plating or other it is suitable by the way of, more
The upper surface of a first conductive column 180a and the upper surface of the first packing colloid 160a form pin layer so that chip structure
140 are electrically coupled by multiple first conductive column 180a with pin layer.Wherein, the step of graphic plating is：First multiple first
The upper surface of conductive column 180a and the upper surface of the first packing colloid 160a form the first metal layer by depositing operation；Lead to again
It crosses electroplating technology and forms second metal layer on the first metal layer.
Then, as shown in Figure 1 g, the second packing colloid 160b is formed, redistributing layer 170 is enveloped.Second packing colloid
160b is located on the first packing colloid 160a, and the first packing colloid 160a and the second packing colloid 160b form packing colloid 160.
First packing colloid 160a and the second packing colloid 160b can be made of same material.
Then, as shown in figure 1h, using the modes such as drilling or etching, at least partly upper surface of redistributing layer 170 is sudden and violent
It is exposed to except the second packing colloid 160b, the upper surface of the second packing colloid 160b is higher than the upper surface of redistributing layer 170.
Then, as shown in figure 1i, by modes such as above-mentioned graphic platings, the second conductive column 180b and pin are formed simultaneously
Layer 150, pin layer 150 is located on the second conductive column 180b, and the second conductive column 180b is located at the through-hole of the second packing colloid 160b
It is interior, and it is connected to the upper surface that redistributing layer 170 is exposed to except the second packing colloid 160b, so that chip structure
140 are electrically coupled by redistributing layer 170 and pin layer 150.Pin layer 150 can by multiple separation metal block shaped at.
Then, as shown in fig. ij, substrate 110 and the bonding between substrate 110 and metallic radiating layer 120 are removed
Object so that the lower surface of metallic radiating layer 120 is exposed to except the first packing colloid 160a.
Then, as shown in Figure 1a, it by chemical treatment or the modes such as physics is coated, such as is vapor-deposited, is dissipated in metal
The lower surface of thermosphere 120 forms insulating layer 190,190 layers of the insulation for by the lower surface electrical isolation of metallic radiating layer 120 to
The generation of electrostatic is prevented, and is made of with good thermally conductive materials, can be polyimides, silica gel or epoxy modeling
Fat or other suitable materials.
In first embodiment in the utility model, the setting of metallic radiating layer 120 is along perpendicular to the metallic radiating layer 120
Side direction stretch flange formability 121 so that 120 surface area of metallic radiating layer increase, can not only further increase chip envelope
The heat dissipation performance of assembling structure, and the binding force of metallic radiating layer 120 and packing colloid 160 can be reinforced.
Fig. 2 a show the sectional view of the chip-packaging structure of second embodiment according to the present utility model.
With reference to Fig. 2 a, chip structure 240 is located at the upper surface of metallic radiating layer 220, by adhesive layer 230 by chip structure
240 affix to the upper surface of metallic radiating layer 220.Chip structure 240 includes multiple first electric contacts 241 positioned at upper surface.
Redistributing layer 270 is located on chip structure 240, passes through 241 electricity of the first electric contact of multiple conductive columns 280 and chip structure 240
Coupling.Pin layer 250 is located on redistributing layer 270, and pin layer 250 includes multiple metal derbies and multiple second electric contacts 251,
Multiple second electric contacts 251 are located at the lower surface of multiple metal derbies, and multiple second electric contacts 251 pass through 280 electricity of multiple conductive columns
It is coupled to the upper surface of redistributing layer 270.Redistributing layer 270 extends along the direction for the upper surface for being parallel to chip structure 240, then
Distribution layer 270 will be positioned at first electric contact 241 at 240 upper surface center of chip structure and positioned at chip knot by conductive column 280
The second electric contact of pin layer 251 of 240 upper surface center of structure or/and top surface edge couples.Wherein, multiple conductive columns 280 wrap
The first conductive column 280a and the second conductive column 280b, the first conductive column 280a are included by the lower surface of redistributing layer 270 and chip
Structure 240 is electrically coupled, and the upper surface of redistributing layer 270 and surface below pin layer 250 are electrically coupled by the second conductive column 280b.
Packing colloid 260 envelopes whole chip structures 240, the upper surface of metallic radiating layer 220, whole redistributing layers 270 and draws
At least partly, wherein packing colloid 260 can be located at the upper surface of metallic radiating layer 220, metallic radiating layer 220 to foot layer 250
Lower surface be exposed to outside packing colloid 260, pin layer 250 is at least partly exposed to the upper surface of packing colloid 260.Specifically
Ground, packing colloid 160 includes the first packing colloid 160a and the second packing colloid 160b, the second packing colloid 160b are located at the
On one packing colloid 160a, the first packing colloid 160a coating chips structure 140, described in the second packing colloid 160b cladding
Redistributing layer 170.
Extended along the direction for the upper surface for being parallel to chip structure 240 through redistributing layer 270, equivalent to increase electrode
Laying area；Chip electrode is led to the top at 240 edge of chip structure so that the mutual spacing of external pin increases
Greatly, it is not easy to be in contact equal abnormal accidents and chip-packaging structure is caused to can not work normally.
Redistributing layer 270 in the present embodiment is selectable structure, if being not provided with redistributing layer in the present embodiment
270, chip structure 240 can be directly electrically coupled with the second electric contact 251 of pin layer 250 by multiple conductive columns 280.
The side of metallic radiating layer 220 includes flange 221, and flange 221 is along the direction for being parallel to 220 side of metallic radiating layer
Extend, flange 221 surrounds the side of packing colloid 260.Sealing pin 222 is located at the upper surface of flange 221, and extends to envelope
The periphery of colloid 260 upper surface is filled, the highly consistent of the upper surface of pin 222 and the upper surface of pin layer 250 is sealed.Metal dissipates
Thermosphere 220, flange 221 and sealing pin 222 form the cavity for accommodating packing colloid 260, and packing colloid 260 is located at the chamber
Body, and packing colloid 260 and 220 portion of upper surface of metallic radiating layer, the medial surface of flange 221 and sealing pin 222
Portion lower surface connects, to improve the thermal diffusivity of the chip-packaging structure and enhance metallic radiating layer 220 and packing colloid
260 binding forces.Sealing pin 222 can be made with the flange 221 of metallic radiating layer 220 of same material.
Fig. 2 b to Fig. 2 i show each of the making method for chip encapsulation structure of second embodiment according to the present utility model
The sectional view in stage.
As shown in Figure 2 b, metallic radiating layer 220 is affixed to the upper surface of substrate 210 by sticky object.Metallic radiating layer
220 include the flange 221 positioned at side, and flange 221 extends along the direction for the side for being parallel to metallic radiating layer 220 so that gold
Belong to heat dissipating layer 220 and forms a cavity with flange 221.Copper, aluminium, Huo Zheqi may be used in metallic radiating layer 220 in the present embodiment
The material that he is suitble to is made.
Then, as shown in Figure 2 c, chip structure 240 is affixed to the upper table of metallic radiating layer 220 by adhesive linkage 230
Face.Chip structure 240 includes multiple first electric contacts 241 positioned at upper surface, and multiple first are placed on the first electric contact 241
Conductive column 280a, the upper surface of the first conductive column 280a are sustained height with the upper surface of flange 221.Wherein, adhesive layer 230 can
To be insulation adhesive, the material of insulation bonding can be epoxy resin, which may be used gluing process
(Dispensing) it is formed on metallic radiating layer 220, the epoxy resin of formation has certain thickness, so that it is guaranteed that the chip
Performance；Adhesive layer 230 can also be that conductive adhesives is made, and is electrically connected with metallic radiating layer 220, and have
There is good thermal diffusivity.
Then, as shown in Figure 2 d, the first packing colloid 260a is formed, the upper surface and metal for enveloping substrate 210 dissipate
The whole of thermosphere 220, chip structure 240, multiple first conductive column 280a.Wherein, the first packing colloid 260a materials can be
Polyimides, silica gel or epoxy modeling fat or other suitable materials；First packing colloid 260a, which may be used, to be compressed into
Type technique, transfer shaping technology, hydraulic seal moulding process or other suitable techniques are made.
Then, as shown in Figure 2 e, using mechanical treatment, such as the modes such as grinding or drilling, chip structure 240 will be located at
The upper surface of multiple first conductive column 280a and the upper surface of flange 221 of upper surface are exposed to the first packing colloid 260a's
Upper surface, it is preferred that the upper surface of multiple first conductive column 280a, 221 upper surface of flange and the first packing colloid 260a
Upper surface is generally aligned in the same plane.
Then, as shown in figure 2f, using graphic plating or other it is suitable by the way of, multiple first conductive column 280a's
Upper surface and the upper surface of the first packing colloid 260a form redistributing layer 270 so that chip structure 240 passes through multiple first
Conductive column 280a and the lower surface of redistributing layer 270 are electrically coupled.Using graphic plating or other it is suitable by the way of, make flange
211 growths, it is preferred that the upper surface of 211 upper surface of flange and redistributing layer 270 after growth is sustained height.Or it uses
Graphic plating or other suitable modes, in the upper surface of multiple first conductive column 280a and the first packing colloid 260a
Upper surface forms pin layer so that chip structure 240 is electrically coupled by multiple first conductive column 280a with pin layer.Wherein, scheme
Shape be electroplated the step of be：It is logical in the upper surface of multiple first conductive column 280a and the upper surface of the first packing colloid 260a first
It crosses depositing operation and forms the first metal layer；Second metal layer is formed by electroplating technology on the first metal layer again.
Then, as shown in Figure 2 g, the second packing colloid 260b is formed, redistributing layer 270, flange 221 are enveloped.Second envelope
Dress colloid 260b is located on the first packing colloid 260a, and the first packing colloid 260a and the second packing colloid 260b form packaging plastic
Body 260.
Then, as shown in fig. 2h, using the modes such as drilling or etching, the through-hole positioned at the second packing colloid is formed, is made
The upper surface for obtaining at least partly upper surface of redistributing layer 270 and flange 211 is exposed to except the second packing colloid 260b, and second
The upper surface of packing colloid 260b is higher than 211 upper surface of upper surface and flange of redistributing layer 270.
Then, as shown in fig. 2i, by modes such as above-mentioned graphic platings, the second conductive column 280b and pin are formed simultaneously
Layer 250, pin layer 250 is located on the second conductive column 280b, and the second conductive column 280b is located at the through-hole of the second packing colloid 260b
It is interior, and it is connected to the upper surface that redistributing layer 270 is exposed to except the second packing colloid 260b, so that chip structure
240 are electrically coupled by redistributing layer 270 and pin layer 250.Pin layer 250 can by multiple separation metal block shaped at.Using
Graphic plating or other suitable modes, make flange 211 regrow, it is preferred that the flange 211 after hyperplasia length is upper again
Surface and the second packing colloid 260b and the second upper surfaces conductive column 280b it is highly consistent.It is formed in 211 upper surface of flange
Pin 222 is sealed, and extends to the periphery of 260 upper surface of packing colloid, seals upper surface and the pin layer 250 of pin 222
Upper surface it is highly consistent.Metallic radiating layer 220, flange 221 and sealing pin 222 form the chamber for accommodating packing colloid
Body, packing colloid 260 are located at the cavity, and packing colloid 260 and 220 portion of upper surface of metallic radiating layer, flange 221 it is interior
Side and the portion lower surface connection for sealing pin 222.
Then, as shown in Figure 2 a, remove substrate 210, the adhesive between substrate 210 and metallic radiating layer 220 with
And the packing colloid 260 of 221 lateral surface of flange so that the lower surface of metallic radiating layer 220 and 221 lateral surface of flange are exposed to
Except packing colloid 260.It by chemical treatment or the modes such as physics is coated, such as is vapor-deposited, in metallic radiating layer 220
The lateral surface of lower surface and flange 221 forms protective layer, which can be that inert metal is formed, such as Ni, Au, avoid
Exposed metallic radiating layer 220 and flange 221 aoxidizes.
In second embodiment in the utility model, the edge edge of metallic radiating layer 220 is parallel to metallic radiating layer 220
Side direction extend flange 221, flange 221 surround packing colloid 260 side, metallic radiating layer 220, flange 221
And sealing pin 222 forms the cavity for accommodating packing colloid 260, can further increase the thermal diffusivity of chip-packaging structure
Energy, capability of electromagnetic shielding and air-tightness, and the binding force of metallic radiating layer 220 and packing colloid 260 can be reinforced, to
So that the reliability higher of chip product, it can extensive substituted metal shell or ceramic cartridge encapsulating structure.
Chip-packaging structure according to the present utility model by using graphic plating technology mode, formed pin layer or
It is formed in distribution layer, under the premise of ensureing chip-packaging structure performance, enables to manufacturing process easy, to reduce manufacture
Cost.Metallic radiating layer below chip structure is at least partly exposed to except packing colloid, can make entire core
The heat dissipation of chip package improves.In addition, the chip-packaging structure of this implementation is all sealed using Metal Packaging, have good
The reliability of good appearance and product.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to
Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also include other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
It is as described above according to the embodiments of the present invention, these embodiments there is no all details of detailed descriptionthe,
The specific embodiment that the utility model is only described is not limited yet.Obviously, as described above, many modification and change can be made
Change.These embodiments are chosen and specifically described to this specification, is in order to preferably explain the principles of the present invention and actually to answer
With to enable skilled artisan to utilize the utility model and repairing on the basis of the utility model well
Change use.The utility model is limited only by the claims and their full scope and equivalents.
Claims (11)
1. a kind of chip-packaging structure, wherein including,
Metallic radiating layer；
Chip structure, is located at the upper surface of the metallic radiating layer, and the chip structure includes positioned at multiple the first of upper surface
Electric contact；
Pin layer, including multiple second electric contacts and the metal derby of multiple separation, the multiple second electric contact are located at described
The lower surface of metal derby, multiple second electric contacts are coupled to multiple described the of the chip structure by multiple conductive columns
One electric contact；And
Packing colloid envelopes the chip structure, the metallic radiating layer and the pin layer at least partly, described to draw
Foot layer is at least partly exposed to the upper surface of the packing colloid, and the lower surface of the metallic radiating layer is exposed to the packaging plastic
Outside body.
2. chip-packaging structure according to claim 1, wherein the side of the metallic radiating layer includes flange.
3. chip-packaging structure according to claim 2, wherein the flange of the metallic radiating layer is along perpendicular to the gold
The direction for belonging to the side of heat dissipating layer extends, and the flange is located in the packing colloid.
4. chip-packaging structure according to claim 2, wherein the flange edge of the metallic radiating layer is parallel to the gold
The direction for belonging to the side of heat dissipating layer extends, and the flange surrounds the side of the packing colloid.
5. chip-packaging structure according to claim 4, wherein further include sealing pin, be located at the upper table of the flange
Face, and extend to the periphery of the packing colloid upper surface so that the metallic radiating layer, the flange and the sealing
Pin forms the cavity for accommodating packing colloid.
6. chip-packaging structure according to claim 5, wherein the upper surface of the sealing pin and the pin layer
Upper surface it is highly consistent.
7. chip-packaging structure according to claim 1, wherein further include：
Redistributing layer, between the chip structure and the pin layer, the redistributing layer edge is parallel to the chip knot
The direction of the upper surface of structure extends, and the redistributing layer will be positioned at described in the chip structure upper surface by the conductive column
Second electrical contact couples of first electric contact and the pin layer, second electric contact are located at the chip structure center
Top or top positioned at the chip structure edge.
8. chip-packaging structure according to claim 7, wherein the multiple conductive column includes：
The lower surface of the redistributing layer and the chip structure are electrically coupled by the first conductive column, first conductive column；And
Second conductive column, second conductive column is by surface thermocouple below the upper surface of the redistributing layer and the pin layer
It closes.
9. chip-packaging structure according to claim 1, wherein further include：
Insulating layer is located at the lower surface of the metallic radiating layer.
10. chip-packaging structure according to claim 1, wherein the upper surface of the metallic radiating layer with it is described
Chip structure is connected by adhesive layer.
11. chip-packaging structure according to claim 7, wherein the packing colloid include the first packing colloid and
Second packing colloid, second packing colloid are located on first packing colloid, described in the first packing colloid cladding
Chip structure and the metallic radiating layer, second packing colloid coat the redistributing layer.
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| CN201721795133.8U CN207781576U (en) | 2017-12-20 | 2017-12-20 | A kind of chip-packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993991A (en) * | 2017-12-20 | 2018-05-04 | 合肥矽迈微电子科技有限公司 | A kind of chip-packaging structure and its manufacture method |
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2017
- 2017-12-20 CN CN201721795133.8U patent/CN207781576U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107993991A (en) * | 2017-12-20 | 2018-05-04 | 合肥矽迈微电子科技有限公司 | A kind of chip-packaging structure and its manufacture method |
| US11239140B2 (en) | 2017-12-20 | 2022-02-01 | Hefei Smat Technology Co., Ltd. | Chip packaging structure with heat dissipation layer, flange and sealing pin |
| US11735503B2 (en) | 2017-12-20 | 2023-08-22 | Hefei SMAT Technology Co., LTD | Method of manufacturing chip packaging structure with dissipation layer, flange and sealing pin |
| CN107993991B (en) * | 2017-12-20 | 2024-10-01 | 合肥矽迈微电子科技有限公司 | Chip packaging structure and manufacturing method thereof |
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