CN207235234U - Multilayer circuit board lamination processing structure - Google Patents
Multilayer circuit board lamination processing structure Download PDFInfo
- Publication number
- CN207235234U CN207235234U CN201721093353.6U CN201721093353U CN207235234U CN 207235234 U CN207235234 U CN 207235234U CN 201721093353 U CN201721093353 U CN 201721093353U CN 207235234 U CN207235234 U CN 207235234U
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- CN
- China
- Prior art keywords
- clamp plate
- pin
- lower clamp
- upper clamp
- dowel hole
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model provides a kind of multilayer circuit board lamination processing structure, including：Upper clamp plate, lower clamp plate, pin and multiple circuit laminates to be laminated, the corresponding position of the upper clamp plate, the lower clamp plate and the circuit laminate is respectively respectively formed with dowel hole, the upper clamp plate, the lower clamp plate, the pin are from top to bottom set gradually, and the pin is threaded through in the dowel hole, the dowel hole of the circuit laminate and the dowel hole of the lower clamp plate of the upper clamp plate.The utility model has the characteristics that to make simply, using simple, reduction interlayer offset during clamping plate is contributed to move, especially when producing high multilayer and closely spaced to the line wiring board in hole, good guarantee is provided to the quality of plate, it can be ensured that interlayer offset is in controlled range.
Description
Technical field
Circuit board processing technique field is the utility model is related to, more particularly to a kind of multilayer circuit board lamination processing structure.
Background technology
Most domestic circuit board plant is also immature for high multiple-plate production technology at present, this very big factor
It is that high multi-layer board easily occurs larger interlayer offset in lamination.Reach more than 10 layers for the number of plies, hole is smaller than to line
The plate of 0.178MM, general wiring board manufactory commercial city can not produce or scrappage is very high, and let alone some are ten several layers of,
Twenties layers of wiring board.
Utility model content
The utility model provides a kind of multilayer circuit board lamination processing structure, to solve multilayer circuit board in the prior art
During lamination process, the problem of larger interlayer deviates easily occurs.
A kind of to solve the above problems, one side as the utility model, there is provided multilayer circuit board lamination processing
Structure, including：Upper clamp plate, lower clamp plate, pin and multiple circuit laminates to be laminated, the upper clamp plate, the lower clamp plate and institute
The corresponding position of circuit laminate is stated respectively respectively formed with dowel hole, the upper clamp plate, the lower clamp plate, the pin are by upper
Set gradually under, the pin is threaded through the dowel hole of the upper clamp plate, the dowel hole of the circuit laminate and described
In the dowel hole of lower clamp plate.
Preferably, the length of the pin is more than the gross thickness after the multiple circuit laminate is stacked and is less than on described
The distance between the upper surface of clamping plate to lower surface of the lower clamp plate.
Preferably, the length of the pin is 4 millimeters bigger than the gross thickness.
Preferably, the thickness of the upper clamp plate and the lower clamp plate is 3 millimeters.
The utility model have the characteristics that to make it is simple, using simple, it is dynamic to help to reduce during clamping plate interlayer offset, especially
When producing high multilayer and closely spaced to the line wiring board in hole, good guarantee is provided to the quality of plate, it can be ensured that interlayer
Offset is in controlled range.
Brief description of the drawings
Fig. 1 schematically shows the top view of the utility model；
Fig. 2 schematically shows the layer structure schematic diagram of the utility model.
Reference numeral in figure：1st, upper clamp plate；2nd, lower clamp plate；3rd, pin；4th, circuit laminate；5th, dowel hole.
Embodiment
The embodiment of the utility model is described in detail below in conjunction with attached drawing, but the utility model can be by right
It is required that the multitude of different ways for limiting and covering is implemented.
The utility model provides a kind of multilayer circuit board lamination processing structure, including：Upper clamp plate 1, lower clamp plate 2, pin 3
With multiple circuit laminates 4 to be laminated, the correspondence position of the upper clamp plate 1, the lower clamp plate 2 and the circuit laminate 4 is punished
Do not set gradually from top to bottom formed with dowel hole 5, the upper clamp plate 1, the lower clamp plate 2, the pin 3 respectively, the pin
Nail 3 is threaded through the dowel hole 5, the dowel hole 5 of the circuit laminate 4 and the positioning pin of the lower clamp plate 2 of the upper clamp plate 1
In hole 5.
Preferably, the length of the pin 3 is more than the gross thickness after the multiple circuit laminate 4 is stacked and less than described
The distance between the upper surface of upper clamp plate 1 to lower surface of the lower clamp plate 2.
Preferably, the length of the pin 3 is 4 millimeters bigger than the gross thickness.
Preferably, the thickness of the upper clamp plate 1 and the lower clamp plate 2 is 3 millimeters.
In lamination, lamination is carried out with upper clamp plate 1 and lower clamp plate 2, circuit laminate 4 to be laminated is clipped in the middle.Lamination
When, first pin 3 is inserted in the dowel hole 5 of lower clamp plate 2, stacks circuit laminate 4 successively further according to lamination order, after having folded again
Upper clamp plate 1 is set to the upper end of pin 3.
By adopting the above-described technical solution, the utility model is without riveting plate, but directly positioned with pin 3,
Pin 3 can resist the various tension force and pulling force that are subject in lamination process well during lamination, so as to reduce layer caused by lamination
Partially.
The utility model have the characteristics that to make it is simple, using simple, it is dynamic to help to reduce during clamping plate interlayer offset, especially
When producing high multilayer and closely spaced to the line wiring board in hole, good guarantee is provided to the quality of plate, it can be ensured that interlayer
Offset is in controlled range.
The above descriptions are merely preferred embodiments of the present invention, is not intended to limit the present invention, for this
For the technical staff in field, various modifications and changes may be made to the present invention.It is all in the spirit and principles of the utility model
Within, any modification, equivalent replacement, improvement and so on, should be included within the scope of protection of this utility model.
Claims (4)
- A kind of 1. multilayer circuit board lamination processing structure, it is characterised in that including：Upper clamp plate (1), lower clamp plate (2), pin (3) With multiple circuit laminates (4) to be laminated, the correspondence of the upper clamp plate (1), the lower clamp plate (2) and the circuit laminate (4) Respectively respectively formed with dowel hole (5) at position, the upper clamp plate (1), the lower clamp plate (2), the pin (3) are from top to bottom Set gradually, the pin (3) is threaded through the dowel hole (5) of the upper clamp plate (1), the positioning pin of the circuit laminate (4) In the dowel hole (5) of hole (5) and the lower clamp plate (2).
- 2. multilayer circuit board lamination processing structure according to claim 1, it is characterised in that the length of the pin (3) More than gross thickness of the multiple circuit laminate (4) after stacked and less than the upper clamp plate (1) upper surface to the lower clamp plate (2) the distance between lower surface.
- 3. multilayer circuit board lamination processing structure according to claim 2, it is characterised in that the length of the pin (3) It is 4 millimeters bigger than the gross thickness.
- 4. multilayer circuit board lamination processing structure according to claim 1, it is characterised in that the upper clamp plate (1) and institute The thickness for stating lower clamp plate (2) is 3 millimeters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721093353.6U CN207235234U (en) | 2017-08-29 | 2017-08-29 | Multilayer circuit board lamination processing structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721093353.6U CN207235234U (en) | 2017-08-29 | 2017-08-29 | Multilayer circuit board lamination processing structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207235234U true CN207235234U (en) | 2018-04-13 |
Family
ID=61859565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721093353.6U Active CN207235234U (en) | 2017-08-29 | 2017-08-29 | Multilayer circuit board lamination processing structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207235234U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109618493A (en) * | 2018-11-30 | 2019-04-12 | 广东骏亚电子科技股份有限公司 | Drilling displacement ameliorative way |
-
2017
- 2017-08-29 CN CN201721093353.6U patent/CN207235234U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109618493A (en) * | 2018-11-30 | 2019-04-12 | 广东骏亚电子科技股份有限公司 | Drilling displacement ameliorative way |
| CN109618493B (en) * | 2018-11-30 | 2021-02-05 | 广东骏亚电子科技股份有限公司 | Drilling displacement improvement method |
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