CN207233729U - A kind of semiconductor die package - Google Patents
A kind of semiconductor die package Download PDFInfo
- Publication number
- CN207233729U CN207233729U CN201720889075.9U CN201720889075U CN207233729U CN 207233729 U CN207233729 U CN 207233729U CN 201720889075 U CN201720889075 U CN 201720889075U CN 207233729 U CN207233729 U CN 207233729U
- Authority
- CN
- China
- Prior art keywords
- chip body
- plastic packaging
- semiconductor die
- die package
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
It the utility model is related to technical field of manufacturing semiconductors, especially a kind of semiconductor die package, with chip body, there is plastic packaging layer at the back side of chip body by injecting glue plastic packaging, it is in grid-like trace layer that the front of chip body, which is equipped with, and pin is welded with trace layer, and encapsulation flow is short, speed is fast, and overall generation problem probability is low；Without die-attach area or resin substrate, Master Cost is saved, reduces packaging cost；Encapsulation precision is high, and uniformity is good, particularly the product to product perception, capacitive character sensitivity.
Description
Technical field
Technical field of manufacturing semiconductors is the utility model is related to, especially a kind of semiconductor die package.
Background technology
Existing semiconductor chip is packaged by die-attach area or resin substrate, its shortcoming is：Semiconductor package at present
Dress is substantially what is be packaged based on die-attach area or resin substrate as the bottom plate or prop of semiconductor.Existing half
Conductor chip die-attach area or resin substrate encapsulation shortcoming are：This packaging technology flow is long, in process often
Die-attach area or the various side effects of resin substrate can be brought, cause some products bad.To avoid this side effect, often need
Great amount of cost is spent in terms of these die-attach areas or resin substrate is handled.
Utility model content
The technical problems to be solved in the utility model is：Overcoming deficiency in the prior art, there is provided one kind encapsulation flow is short,
Speed is fast, and the overall problem probability that produces is low, without die-attach area or resin substrate, saves Master Cost, reduces packaging cost
Semiconductor die package.
Technical solution is used by the utility model solves its technical problem：A kind of semiconductor die package, has core
Piece body, it is characterised in that：There is plastic packaging layer at the back side of the chip body by injecting glue plastic packaging, and the front of chip body is equipped with
In grid-like trace layer, pin is welded with trace layer.
Further, in order to which ductility is good, thermal conductivity and electric conductivity are high, and the trace layer is using made of copper product；
At the same time in order to which without die-attach area or resin substrate, saving Master Cost, reduces packaging cost, pin uses tin ball or plating
Scolding tin is made；The material that plastic packaging layer uses is resin.
Further, the chip body is formed by semiconductor crystal wafer scribing is good according to four side spacing diffusion of grade.
The beneficial effects of the utility model are：The utility model 1) encapsulation flow is short, and speed is fast, and overall to produce problem several
Rate is low；
2) saves Master Cost, reduces packaging cost without die-attach area or resin substrate；
3) encapsulation precisions are high, and uniformity is good, particularly the product to product perception, capacitive character sensitivity.
Brief description of the drawings
The utility model is further illustrated with embodiment below in conjunction with the accompanying drawings.
Fig. 1 is the structure diagram of the utility model.
1. chip body in figure, 2. plastic packaging layers, 3. trace layers, 4. pins.
Embodiment
The utility model is further described presently in connection with attached drawing.These attached drawings are simplified schematic diagram only to show
Meaning mode illustrates the basic structure of the utility model, therefore it only shows the composition related with the utility model.
A kind of semiconductor die package as shown in Figure 1, has chip body 1, it is characterised in that：The chip body
There is plastic packaging layer 2 at 1 back side by injecting glue plastic packaging, and it is in grid-like trace layer 3 that the front of chip body 1, which is equipped with, is welded in trace layer 3
It is connected to pin 4.
Trace layer 3 is using made of copper product；Pin 4 is made of tin ball or plated solder；The material that plastic packaging layer 2 uses
For resin.
Chip body 1 is formed by semiconductor crystal wafer scribing is good according to four side spacing diffusion of grade.
It is specific as follows：Chip body 1 is by after semiconductor crystal wafer scribing is good, according still further to waiting four side spacing
Diffusion, whole chip body 1 are adhered to above sticking container, and sticking container refers to UV films and other sticking media
(kiver), is then directly injected into the plastic packaging layer 2 being made of resin material at 1 back side of chip body, and the front of chip body 1 is logical
Plant tin ball or plated solder are crossed as pin 4, then scratching for injection formed is become as workable finished product.
Can reach that encapsulation flow is short, and speed is fast, the overall problem probability that produces is low, and without die-attach area or resin base
Plate, saves Master Cost, reduces packaging cost, and encapsulation precision is high, and uniformity is good, particularly to product perception, capacitive character
Sensitive product.
The above embodiment is only the technical concepts and features for illustrating the utility model, and its object is to allow be familiar with this skill
The personage of art can understand the content of the utility model and be carried out, and the protection model of the utility model can not be limited with this
Enclose, all equivalent change or modifications made according to the utility model Spirit Essence, should all cover the protection model in the utility model
In enclosing.
Claims (3)
1. a kind of semiconductor die package, has chip body (1), it is characterised in that：The back side of the chip body (1) leads to
Crossing injecting glue plastic packaging has plastic packaging layer (2), and it is in grid-like trace layer (3) that the front of chip body (1), which is equipped with, and trace layer is welded on (3)
It is connected to pin (4).
A kind of 2. semiconductor die package according to claim 1, it is characterised in that：The trace layer (3) uses copper
Made of material；Pin (4) is made of tin ball or plated solder；The material that plastic packaging layer (2) uses is resin.
A kind of 3. semiconductor die package according to claim 1, it is characterised in that：The chip body (1) is by half
Semiconductor wafer scribing is good according to four side spacing diffusion composition of grade.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720889075.9U CN207233729U (en) | 2017-07-20 | 2017-07-20 | A kind of semiconductor die package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720889075.9U CN207233729U (en) | 2017-07-20 | 2017-07-20 | A kind of semiconductor die package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207233729U true CN207233729U (en) | 2018-04-13 |
Family
ID=61853663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720889075.9U Expired - Fee Related CN207233729U (en) | 2017-07-20 | 2017-07-20 | A kind of semiconductor die package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207233729U (en) |
-
2017
- 2017-07-20 CN CN201720889075.9U patent/CN207233729U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180413 Termination date: 20210720 |