CN207217548U - Transistor device with local p-type cap layers - Google Patents
Transistor device with local p-type cap layers Download PDFInfo
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- CN207217548U CN207217548U CN201721265684.3U CN201721265684U CN207217548U CN 207217548 U CN207217548 U CN 207217548U CN 201721265684 U CN201721265684 U CN 201721265684U CN 207217548 U CN207217548 U CN 207217548U
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Abstract
The utility model, which provides a kind of transistor device with local p-type cap layers, includes substrate, transition zone, channel layer, barrier layer and source electrode, grid, drain electrode and p-type cap layers above barrier layer, p-type cap layers include at least one first p type island region and at least one second p type island region, first p type island region and the second p type island region are adjacent and are respectively positioned between grid and drain electrode, from grid to draining, first first p type island region electrically connects with source electrode；The doping face concentration of p type impurity is more than the doping face concentration of p type impurity in the second p type island region in first p type island region, two-dimensional electron gas face concentration simultaneously greater than below the first p type island region, the doping face concentration of p type impurity is less than the two-dimensional electron gas face concentration below the second p type island region in the second p type island region.Transistor device of the present utility model can resolve into the higher high electric field area in an electric field peak of gate edge in the relatively low high electric field area in multiple electric field peaks, improve the breakdown voltage, reliability and dynamic characteristic of transistor device.
Description
Technical field
Field of semiconductor devices is the utility model is related to, is to be related to a kind of crystal with local p-type cap layers specifically
Tube device.
Background technology
Power device usually requires the ability with high-breakdown-voltage, low on-resistance and high-speed switch.Conventional electric power
Semi-conductor market is based on the power device of silicon, past 20 years, and the performance of Si power device is already close to theoretical limit, further
It is extremely difficult to lift its performance.
Compared to silicon or GaAs, gallium nitride（GaN）Semiconductor has band gap wide（Eg=3.4eV）, excellent heat endurance,
High-breakdown-voltage, high electronics saturation drift velocity and excellent radiation resistance.In addition, compare silicon power semiconductor, GaN power
Semiconductor has low temperature resistant characteristic, and power conversion loss caused by power semiconductor can be reduced by having, and accomplishes that power is changed
The advantages that systematic electricity loss is minimized.GaN semiconductor devices is with low-loss, high withstand voltage, high-speed switch ability, hot operation energy
The advantages such as power turn into power device of new generation.The fields such as industrial electronic, power transmission, smart home, electric automobile, track traffic
The needs of GaN semiconductors are constantly expanded.
Referring to Fig. 1, existing GaN high electron mobility transistor（GaN High Electron Mobility
Transistor, GaN HEMT）Device in the off case, if to drain electrode 103 apply a high voltages, the grid of device
102 edges can produce a high electric field area.The high electric field at the edge of grid 102 causes the leakage current of device to increase, and breakdown voltage subtracts
It is small, and serious dynamic electric resistor can be caused to degenerate, and integrity problem.The electric field for reducing device inside is that acquisition is highly reliable
The key of the GaN HEMT devices of property.
Utility model content
The purpose of this utility model is to provide a kind of transistor device with local p-type cap layers, transistor device tool
There are high-breakdown-voltage and high reliability, while the dynamic electric resistor for being capable of suppression device is degenerated.
To achieve the above object, the utility model provides a kind of transistor device with local p-type cap layers, transistors
Part includes substrate, transition zone, channel layer, barrier layer and source electrode, grid, drain electrode and p-type cap layers above barrier layer, P
Type cap layers include at least one first p type island region and at least one second p type island region, the first p type island region and the adjoining of the second p type island region, the first P
Type area and the second p type island region are respectively positioned between grid and drain electrode, and from grid to draining, first first p type island region electrically connects with source electrode；The
The doping face concentration of p type impurity is more than the doping face concentration of p type impurity in the second p type island region, p-type in the first p type island region in one p type island region
The doping face concentration of impurity is more than the two-dimensional electron gas face concentration below the first p type island region, the doping of p type impurity in the second p type island region
Face concentration is less than the two-dimensional electron gas face concentration below the second p type island region.
One preferable scheme is that the quantity of the first p type island region and the quantity of the second p type island region are more than two, from grid
To drain electrode, the first p type island region is alternately arranged successively with the second p type island region.
One preferential scheme is that, from grid to draining, first p type island region is the first p type island region.
Further scheme is that the quantity of the first p type island region is more than or equal to the quantity of the second p type island region.
One preferable scheme is the region on p-type cap layers part covering barrier layer between grid and drain electrode.
One preferable scheme is that the doping face concentration of p type impurity is the average acceptor of the first p type island region in the first p type island region
Concentration and the product of the thickness of the first p type island region；In second p type island region the doping face concentration of p type impurity for the second p type island region it is average by
Main concentration and the product of the thickness of the second p type island region.
One preferable scheme is, formed with dielectric layer on barrier layer, the first p type island region, the second p type island region, source electrode, grid with
And drain electrode is respectively positioned between dielectric layer and barrier layer, dielectric layer is provided with metal level, and metal level is by source electrode and first first p type island region
Electrical connection.
Further scheme is that dielectric layer offers first through hole above source electrode, and dielectric layer is in first first p type island region
Top offer the second through hole；Metal level includes the first extension, the second extension and is connected to the first extension and the
Connecting portion between two extensions, the first extension insertion first through hole are simultaneously connected with source electrode, the second extension insertion second
Through hole is simultaneously connected with first first p type island region.
Further scheme is, metal level also includes the 3rd extension, the 3rd extension parallel to connecting portion and along
The upper surface of dielectric layer is from the second extension to close to the extension of the side of drain electrode.
One preferable scheme is that grid is at Schottky gate or p-type grid or metal medium grid or trench gate or fluorine ion
The grid managed.
The beneficial effects of the utility model are：
Transistor device of the present utility model can be by the higher height in an electric field peak of gate edge in transistor device
Resolve into the relatively low high electric field area in multiple electric field peaks in electric field region.By forming new electric field peak, the height electricity of gate edge is reduced
So that the Electric Field Distribution on transistor device surface is more uniform, so as to improve the breakdown voltage of transistor device, reliability
And dynamic characteristic.On the other hand, when transistor device is in conducting state, the surface charge of transistor device surface capture can be with
By the electrical connection with source electrode and quick release, so that the dynamic electric resistor of suppression device is degenerated.
Brief description of the drawings
Fig. 1 is the structural representation of existing GaN high electron mobility transistor device.
Fig. 2 is the structural representation of the utility model transistor device embodiment.
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Embodiment
Referring to Fig. 2, the transistor device with local p-type cap layers of the present embodiment is the extension being produced on substrate 121
Sandwich construction, the transistor device include substrate 121 and the transition zone 122, the ditch that are grown successively from bottom to top on substrate 121
Channel layer 123, barrier layer 124 and dielectric layer 125, transistor device also include the source between barrier layer 124 and dielectric layer 125
Pole 11, grid 12, drain electrode 13 and p-type cap layers.P-type cap layers are located between grid 12 and drain electrode 13, and p-type cap layers part covers
Region on barrier layer 124 between grid 12 and drain electrode 13.
P-type cap layers include three the first p type island regions 14 and three the second p type island regions 15, the first p type island region 14 and in the present embodiment
Two p type island regions 15 are abutted, and the first p type island region 14 and the second p type island region 15 are respectively positioned between grid 12 and drain electrode 13, from grid 12 to leakage
Pole 13, the first p type island region 14 are alternately arranged successively with the second p type island region 15.And from grid 12 to drain electrode 13, first p type island region is the
One p type island region 14, first first p type island region 14 electrically connect with source electrode 11.
The doping face concentration of p type impurity is more than the doping face concentration of p type impurity in the second p type island region 15 in first p type island region 14.
The doping face concentration of p type impurity is the average acceptor concentration of the first p type island region 14 in first p type island region 14N PAWith the first p type island region 14
Thicknesst PAProduct.Two-dimensional electron gas face concentration positioned at the lower section of the first p type island region 14 isn sA, p type impurity in the first p type island region 14
Doping face concentration（N PA×t PA）More than the two-dimensional electron gas face concentration of the lower section of the first p type island region 14n sA。
The doping face concentration of p type impurity is the average acceptor concentration of the second p type island region 15 in second p type island region 15N PBWith the 2nd P
The thickness in type area 15t PBProduct.Two-dimensional electron gas face concentration positioned at the lower section of the second p type island region 15 isn sB, in the second p type island region 15
The doping face concentration of p type impurity（N PB×t PB）Less than the two-dimensional electron gas face concentration of the lower section of the second p type island region 15n sB。
In addition, dielectric layer 125 is provided with metal level 16, metal level 16 electrically connects source electrode 11 with first first p type island region 14.
Dielectric layer 125 offers first through hole in the top of source electrode 11, and dielectric layer 125 offers in the top of first first p type island region 14
Second through hole.Metal level 16 includes the first extension 161, the second extension 162, the 3rd extension 163 and is connected to first
Connecting portion 164 between the extension 162 of extension 161 and second.First extension 161 insert first through hole and with the phase of source electrode 11
Connection, the second extension 162 insert the second through hole and are connected with first first p type island region 14, and the 3rd extension 163 is parallel to even
Socket part 164 simultaneously extends along the upper surface of dielectric layer 125 from the second extension 162 to close to the side of drain electrode 13.Metal level 16
The 3rd extension 163 to stretch out is set, is due to that the end that metal level 16 is difficult in actual process just terminates in
The edge of second through hole, set one section of the 3rd extension 163 to stretch out that the processing technology of transistor device can be caused to become
Obtain simply, in addition, the 3rd extension 163 serves the effect of field plate structure, the collection of the leakage fringe field of side grid 12 can be weakened
In, reduce the injection of the electron charge into barrier layer 124 of grid 12, help to optimize the Electric Field Distribution of transistor device.
Alternatively, grid 12 is the Schottky gate being directly arranged on barrier layer 124 in the present embodiment.In practical application,
Grid can also use p-type grid or metal medium grid（MIS grid）Or the grid or other grid that trench gate or fluorine ion treat
Pole structure.
When transistor device of the present utility model in the off case, drain electrode 13 to transistor device applies voltage, by
The doping concentration of p type impurity is larger in the first p type island region 14, and the first p type island region 14 will not be completely depleted.In the off case,
Voltage is applied to drain electrode 13, the second p type island region 15 will be depleted, after the second p type island region 15 is depleted, if continuing increase to drain electrode 13
The voltage of application, then it can produce a high electric field near the edge of the first p type island region 14 of grid 12；Now, if continuing to increase
The voltage applied to drain electrode 13, then it can produce one high electricity from grid 12 to second the first p type island region 14 edge of drain electrode 13
；By that analogy, then from grid 12 to drain electrode 13, first p type island region 14 edge farther apart from grid 12 produces a height
Electric field.
In addition, the quantity of the first p type island region 14 and the quantity of the second p type island region 15 are at least one, and the first p type island region 14
And second p type island region 15 be respectively positioned on grid 12 and drain electrode 13 between.When first p type island region is the first p type island region 14, the first p type island region 14
Quantity be more than or equal to the second p type island region 15 quantity, therefore, in p-type cap layers near drain electrode 13 sides p type island region can be
First p type island region 14 can also be the second p type island region 15.In addition, first p type island region is alternatively the second p type island region 15.
Therefore transistor device of the present utility model can be by an electric field peak of gate edge in transistor device
Resolve into the relatively low high electric field area in multiple electric field peaks in higher high electric field area.By forming new electric field peak, grid side is reduced
The high electric field of edge so that the Electric Field Distribution on transistor device surface is more uniform, so as to improve the breakdown potential of transistor device
Pressure, reliability and dynamic characteristic.On the other hand, when transistor device is in conducting state, the table of transistor device surface capture
Surface charge can be by the electrical connection with source electrode and quick release, so that the dynamic electric resistor of suppression device is degenerated.
Finally it should be noted that above-described is only preferred embodiment of the present utility model, it is noted that for
For one of ordinary skill in the art, without departing from the concept of the premise utility, can also make it is some deformation and
Improve, these belong to the scope of protection of the utility model.
Claims (10)
1. the transistor device with local p-type cap layers, the transistor device includes substrate, transition zone, channel layer, potential barrier
Layer；
It is characterized in that：
The transistor device also includes source electrode, grid, drain electrode and the p-type cap layers above the barrier layer, the p-type cap
Layer includes at least one first p type island region and at least one second p type island region, first p type island region and second p type island region adjoining,
First p type island region and second p type island region are respectively positioned between the grid and the drain electrode, from the grid to the leakage
Pole, first first p type island region electrically connect with the source electrode；
The doping face concentration of p type impurity is more than the doping face concentration of p type impurity in second p type island region in first p type island region,
The doping face concentration of p type impurity is more than the two-dimensional electron gas face concentration below first p type island region, institute in first p type island region
The doping face concentration of p type impurity in the second p type island region is stated less than the two-dimensional electron gas face concentration below second p type island region.
2. transistor device according to claim 1, it is characterised in that：
The quantity of first p type island region and the quantity of second p type island region are more than two, from the grid to the leakage
Pole, first p type island region are alternately arranged successively with second p type island region.
3. transistor device according to claim 1, it is characterised in that：
From the grid to the drain electrode, first p type island region is first p type island region.
4. transistor device according to claim 3, it is characterised in that：
The quantity of first p type island region is more than or equal to the quantity of second p type island region.
5. according to the transistor device described in any one of Claims 1-4, it is characterised in that：
The p-type cap layers part covers the region between the grid and the drain electrode on the barrier layer.
6. according to the transistor device described in any one of Claims 1-4, it is characterised in that：
The doping face concentration of p type impurity is the average acceptor concentration and described first of first p type island region in first p type island region
The product of the thickness of p type island region；The doping face concentration of p type impurity is the average acceptor of second p type island region in second p type island region
Concentration and the product of the thickness of second p type island region.
7. according to the transistor device described in any one of Claims 1-4, it is characterised in that：
Formed with dielectric layer on the barrier layer, first p type island region, second p type island region, the source electrode, the grid with
And the drain electrode is respectively positioned between the dielectric layer and the barrier layer, the dielectric layer is provided with metal level, the metal level
The source electrode is electrically connected with first first p type island region.
8. transistor device according to claim 7, it is characterised in that：
The dielectric layer offers first through hole above the source electrode, and the dielectric layer is in first first p type island region
Top offers the second through hole；
The metal level includes the first extension, the second extension and is connected to first extension and second extension
Connecting portion between portion, first extension insert the first through hole and are connected with the source electrode, second extension
Portion inserts second through hole and is connected with first first p type island region.
9. transistor device according to claim 8, it is characterised in that：
The metal level also includes the 3rd extension, and the 3rd extension is parallel to the connecting portion and along the dielectric layer
Upper surface from second extension to close to the drain electrode side extend.
10. according to the transistor device described in any one of Claims 1-4, it is characterised in that：
The grid that the grid is Schottky gate or p-type grid or metal medium grid or trench gate or fluorine ion treats.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721265684.3U CN207217548U (en) | 2017-09-28 | 2017-09-28 | Transistor device with local p-type cap layers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721265684.3U CN207217548U (en) | 2017-09-28 | 2017-09-28 | Transistor device with local p-type cap layers |
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| Publication Number | Publication Date |
|---|---|
| CN207217548U true CN207217548U (en) | 2018-04-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721265684.3U Withdrawn - After Issue CN207217548U (en) | 2017-09-28 | 2017-09-28 | Transistor device with local p-type cap layers |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644915A (en) * | 2017-09-28 | 2018-01-30 | 英诺赛科（珠海）科技有限公司 | Transistor device with local p-type cap layers |
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2017
- 2017-09-28 CN CN201721265684.3U patent/CN207217548U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644915A (en) * | 2017-09-28 | 2018-01-30 | 英诺赛科（珠海）科技有限公司 | Transistor device with local p-type cap layers |
| WO2019061216A1 (en) * | 2017-09-28 | 2019-04-04 | 英诺赛科（珠海）科技有限公司 | Transistor device with local p-type cap layer |
| CN107644915B (en) * | 2017-09-28 | 2019-09-13 | 英诺赛科(苏州)半导体有限公司 | Transistor device with local p-type cap layers |
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| GR01 | Patent grant | ||
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| AV01 | Patent right actively abandoned |
Granted publication date: 20180410 Effective date of abandoning: 20190913 |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20180410 Effective date of abandoning: 20190913 |
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| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |