CN207052606U - A kind of encapsulating structure of CIS chips - Google Patents
A kind of encapsulating structure of CIS chips Download PDFInfo
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- CN207052606U CN207052606U CN201721016520.7U CN201721016520U CN207052606U CN 207052606 U CN207052606 U CN 207052606U CN 201721016520 U CN201721016520 U CN 201721016520U CN 207052606 U CN207052606 U CN 207052606U
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Abstract
The utility model discloses a kind of encapsulating structure of CIS chips, it is related to technical field of semiconductors, the encapsulating structure includes：Transparent slide；CIS chip dies, its pad and photosensitive area are arranged at the first surface of CIS chip dies；Cofferdam, it is arranged between the first surface of CIS chip dies and the first surface of transparent slide, the first surface of first surface, transparent slide with CIS chip dies forms closed cavity；Metallic circuit layer, is arranged at the second surface of CIS chip dies, and metallic circuit layer is connected by the plain conductor through CIS chip dies with the pad of CIS chip die first surfaces；Insulating barrier, it is arranged at metallic circuit layer surface.The utility model connects the metallic circuit layer of CIS chip die second surfaces and the pad of CIS chip dies by the plain conductor through CIS chip dies, and electric signal is drawn out to the second surface of CIS chip dies.The encapsulating structure will not produce larger mechanical stress, so as to form hidden split；Pad is high with wafer bonding strength, is unlikely to deform.
Description
Technical field
It the utility model is related to technical field of semiconductors, and in particular to a kind of encapsulating structure of CIS chips.
Background technology
CIS (English full name：CMOS Image Sensor, Chinese：Cmos image sensor) chip encapsulation process
In, it is necessary to isolate to its photosensitive area, in order to avoid photosensitive area is polluted by microparticle.
Chinese patent (A of CN 104465581) discloses a kind of CIS encapsulating structures.As shown in figure 1,102 be CIS chips
Wafer, its photosensitive area 103 are located at same surface with pad 104.100 be cover plate, and 101 be bonding glue, wherein bonding glue 101 exists
CIS chip dies surface forms cofferdam, and cavity 100c is formed together with CIS chip dies surface, cover plate 100.In addition, 106 are
Metal level, 108 be soldered ball, and pad 104 and soldered ball 108 are connected by metal level 106, so as to which the picture signal of CIS chips be drawn
Go out.107 be welding resisting layer.
Because photosensitive area 103 and the pad 104 of CIS chip dies be located at same surface, therefore needs will be with encapsulation
Pad 104 leads to the second surface relative with first surface.Shown in Fig. 1 in the prior art, the metal level for drawing pad 104 is set
Put in the outside of CIS chip dies, and metal level is formed in the outside of CIS chip dies for ease of technological process, to CIS cores
Wafer side is chamfer, and forms the metal level 106 being connected with pad 104 on this basis.
But, on the one hand, larger mechanical stress can be produced during being cut to pad 104, forms hidden split；Separately
On the one hand, pad and the connection area of CIS chip dies are smaller, and bonding strength reduces, due to the heat of metal pad and Silicon Wafer
The coefficient of expansion is inconsistent, and structure is easily deformed at pad.
The content of the invention
In view of this, the utility model embodiment provides a kind of encapsulating structure of CIS chips, is sealed with solving existing CIS
Can be formed during dress mode it is hidden split and pad at the problem of being easily deformed.
The utility model first aspect provides a kind of encapsulating structure of CIS chips, including：Transparent slide；CIS chips are brilliant
Circle, its pad and photosensitive area are arranged at the first surface of the CIS chip dies；Cofferdam, it is arranged at the CIS chip dies
Between first surface and the first surface of the transparent slide, first surface, the transparent slide with the CIS chip dies
First surface formed closed cavity；Metallic circuit layer, it is arranged at the second surface of the CIS chip dies, the metal wire
Road floor is connected by the plain conductor through the CIS chip dies with the pad of the CIS chip dies first surface；Insulation
Layer, is arranged at the metallic circuit layer surface.
Alternatively, the pad of the CIS chip dies protrudes from first surface；Also, the cofferdam coats the pad.
Alternatively, the lateral surface of the CIS chip dies, the cofferdam and the transparent slide is from top to bottom to extension
The inclined-plane stretched；The insulating barrier and/or the metallic circuit layer cover the inclined-plane.
Alternatively, the inclined-plane is extended between the first surface and second surface of the transparent slide；Second table
Face is oppositely arranged with the first surface.
Alternatively, the second surface of the CIS chip dies is provided with the first opening, exposes the pad；The metal
Wire is arranged at the inwall of first opening.
Alternatively, the bottom of the plain conductor covering first opening.
Alternatively, between the CIS chip dies and the metallic circuit layer, in the second table of the CIS chip dies
The side wall of face and first opening is additionally provided with inorganic dielectric layer；The inorganic dielectric layer includes SiO2And/or SiN.
Alternatively, extremely flushed in first opening filled with epoxy resin with the second surface of the metallic circuit layer.
Alternatively, the surface of insulating layer is provided with the second opening for exposing metallic circuit layer conductor；The encapsulating structure
Also include：Metal salient point, it is connected by the described second opening with the metallic circuit layer.
Alternatively, the transparent slide is glass.
The encapsulating structure for the CIS chips that the utility model embodiment is provided, by the first surface of CIS chip dies,
The first surface of transparent slide and cofferdam form closed cavity and carry out insulation blocking to the photosensitive area of CIS chip dies；And pass through
Plain conductor through CIS chip dies connects the metallic circuit layer of CIS chip die second surfaces and the weldering of CIS chip dies
Disk, electric signal is drawn out to the second surface of CIS chip dies.Because the formation of plain conductor need not be cut, more will not
The larger pad of hardness is cut to, therefore larger mechanical stress will not be produced, so as to which hidden split will not be formed；Pad and CIS chips
The connection area of wafer is larger, and pad surrounding is connected with CIS chip dies, and bonding strength is higher, is unlikely to deform.
Brief description of the drawings
Feature and advantage of the present utility model can be more clearly understood by reference to accompanying drawing, accompanying drawing be schematically without
It is interpreted as carrying out any restrictions to the utility model, in the accompanying drawings：
Fig. 1 shows the schematic diagram of existing CIS chip-packaging structures；
Fig. 2 shows CIS chip structure schematic diagrames to be packaged；
Fig. 3 shows the schematic diagram after forming metallic circuit layer；
Fig. 4 is shown to be cut to obtain the schematic diagram on inclined-plane to CIS chip dies, cofferdam and transparent slide；
Fig. 5 shows the signal after filling epoxy resin；
Fig. 6 shows the schematic diagram to form insulating barrier and set after metal salient point.
Embodiment
In order that the purpose of this utility model, advantage, preparation method are clearer, it is new to this practicality below in conjunction with accompanying drawing
The implementation example of type is described in detail, and the example of the embodiment is shown in the drawings, and wherein part-structure is direct in accompanying drawing
Giving preferable structural material, it is clear that described embodiment is the utility model part of the embodiment, rather than whole
Embodiment.It should be noted that the embodiment being described with reference to the drawings is exemplary, the structural material shown in embodiment is also
Exemplary, it is only used for explaining the utility model, and can not be construed to limitation of the present utility model, each reality of the utility model
The accompanying drawing of example is applied merely to the purpose of signal, therefore is not necessarily to scale.Based on the embodiment in the utility model,
The every other embodiment that those skilled in the art are obtained under the premise of creative work is not made, it is new to belong to this practicality
The scope of type protection.
The utility model embodiment provides a kind of encapsulating structure of CIS chips.As shown in Fig. 2 CIS chip dies 10 are wrapped
Include the photosensitive area 11 for being arranged at first surface and the pad 12 for being similarly provided at first surface.In addition to the CIS chip dies,
As shown in Figures 3 to 6, the encapsulating structure of the CIS chips also includes transparent slide 20, cofferdam 30, metallic circuit layer 40 and insulation
Layer 50.
Cofferdam 30 is arranged between the first surface of CIS chip dies 10 and the first surface of transparent slide 20, with CIS cores
The first surface of wafer 10, the first surface of transparent slide 20 form closed cavity 70.
Metallic circuit layer 40 is arranged at the second surface of CIS chip dies 10, and metallic circuit layer 40 passes through through CIS chips
The plain conductor of wafer 10 is connected with the pad 12 of the first surface of CIS chip dies 10, should be through the metal of CIS chip dies 10
Wire is a part for metallic circuit layer 40.
Insulating barrier 50 is arranged at the surface of metallic circuit layer 40.
It is pointed out that " first surface " described herein is to be towards the surface of cavity 70, " second surface "
The surface being oppositely arranged with first surface.
The encapsulating structure for the CIS chips that the utility model embodiment is provided, by the first surface of CIS chip dies,
The first surface of transparent slide and cofferdam form closed cavity and carry out insulation blocking to the photosensitive area of CIS chip dies；And pass through
Plain conductor through CIS chip dies connects the metallic circuit layer of CIS chip die second surfaces and the weldering of CIS chip dies
Disk, electric signal is drawn out to the second surface of CIS chip dies.Because the formation of plain conductor need not be cut, more will not
The larger pad of hardness is cut to, therefore larger mechanical stress will not be produced, so as to which hidden split will not be formed；Pad and CIS chips
The connection area of wafer is larger, and pad surrounding is connected with CIS chip dies, and bonding strength is higher, is unlikely to deform.
The pad 12 of CIS chip dies 10 protrudes from first surface, and it can be located in cavity 70, can also be located at cofferdam
In 30.As a kind of optional embodiment of the present embodiment, the pad 12 of CIS chip dies 10 is located in cofferdam 30, and encloses
Weir 30 coats pad 12, difficult for drop-off so as to anchor pad 12, and the width for reducing cavity 70 (i.e. encapsulates shown in Fig. 6
The lateral length of cavity 70 in the vertical section of structure).Cofferdam 30, then can be at it still using the slightly long material of solidification required time
The pad of CIS chip dies 10 is arranged in cofferdam 30 when not being fully cured.
In the encapsulating structure, the lateral surface of CIS chip dies 10, cofferdam 30 and transparent slide 20 can be vertical plane,
It can be inclined plane.As a kind of optional embodiment of the present embodiment, CIS chip dies 10, cofferdam 30 and transparent slide 20
Lateral surface be the inclined-plane that stretches out from top to bottom.Insulating barrier 50 or metallic circuit layer 40 cover the inclined-plane, so as to cover
The insulating barrier 50 or metallic circuit layer 40 on inclined-plane can be formed with the first surface of transparent slide 20 and be enclosed in outside cavity 70
Enclosed construction, further improve CIS chip dies photosensitive area 11 isolating seal, air-tightness is good, reliability is high.
Alternatively, inclined-plane is extended between the first surface and second surface of transparent slide 20, to improve peripheral containment knot
The sealing of structure.
It is pointed out that because above-mentioned inclined-plane does not manifest pad, therefore will not be cut to during inclined-plane formation
The larger pad of hardness；Chip bonding pad, which needs not move through mechanical stress effect, can form interconnection, therefore will not form hidden split.
As a kind of optional embodiment of the present embodiment, the second surface of CIS chip dies 10 is provided with the first opening,
Exposed pad 12.Plain conductor is arranged at the inwall of the first opening, one end and the metal wire of the second surface of CIS chip dies 10
Road floor 40 is connected, and the other end is connected with the pad 12 of the first open bottom.Alternatively, plain conductor can cover the first opening
Internal side wall.
Alternatively, plain conductor can also cover the bottom of the first opening, fully be contacted with pad 12.
As a kind of optional embodiment of the present embodiment, between CIS chip dies 10 and metallic circuit layer 40, in CIS
The side wall of the second surface of chip die 10 and the first opening is additionally provided with inorganic dielectric layer.The inorganic dielectric layer can be SiO2
Layer or SiN layer, or SiO2With SiN stepped construction.
Further, extremely flushed in above-mentioned first opening filled with epoxy resin with the second surface of metallic circuit layer 40,
So as to reduce the technology difficulty that smooth insulating barrier is further formed on metallic circuit layer 40.It is in addition, relatively low using cost
The opening of epoxy resin filling first rather than process costs can be reduced using the opening of plating metal process filling first；Moreover,
First opening is filled and led up the stress that can also reduce the first opening.
As a kind of optional embodiment of the present embodiment, the surface of insulating barrier 50, which is provided with, exposes the wire of metallic circuit layer 40
Second opening.The encapsulating structure also includes metal salient point 60, and the metal salient point 60 is connected by the second opening with metallic circuit layer
Connect.
Alternatively, transparent slide 20 is glass.
Although being described in detail on example embodiment and its advantage, those skilled in the art can not depart from
In the case of protection domain of the present utility model spiritual and defined in the appended claims to these embodiments carry out various change,
Substitutions and modifications, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples,
While one of ordinary skill in the art be should be readily appreciated that in holding scope of protection of the utility model, time of processing step
Sequence can change.
In addition, application of the present utility model be not limited to the technique of the specific embodiment described in specification, mechanism,
Manufacture, material composition, means, method and step.From disclosure of the present utility model, as one of ordinary skill in the art
Will readily appreciate that, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means,
Method or step, the function or obtain substantially that wherein their execution are substantially the same with the corresponding embodiment of the utility model description
Identical result, they can be applied according to the utility model.Therefore, the appended claims for the utility model be intended to by
These techniques, mechanism, manufacture, material composition, means, method or step are included in its protection domain.
Claims (10)
- A kind of 1. encapsulating structure of CIS chips, it is characterised in that including：Transparent slide；CIS chip dies, its pad and photosensitive area are arranged at the first surface of the CIS chip dies；Cofferdam, it is arranged between the first surface of the CIS chip dies and the first surface of the transparent slide, it is and described The first surface of CIS chip dies, the first surface of the transparent slide form closed cavity；Metallic circuit layer, is arranged at the second surface of the CIS chip dies, and the metallic circuit layer passes through through the CIS The plain conductor of chip die is connected with the pad of the CIS chip dies first surface；Insulating barrier, it is arranged at the metallic circuit layer surface.
- 2. the encapsulating structure of CIS chips according to claim 1, it is characterised in that the pad of the CIS chip dies is dashed forward For first surface；Also, the cofferdam coats the pad.
- 3. the encapsulating structure of CIS chips according to claim 1, it is characterised in that the CIS chip dies, described enclose The lateral surface of weir and the transparent slide is the inclined-plane to stretch out from top to bottom；The insulating barrier and/or the metallic circuit Layer covers the inclined-plane.
- 4. the encapsulating structure of CIS chips according to claim 3, it is characterised in that the inclined-plane extends to described transparent Between the first surface and second surface of slide glass；The second surface is oppositely arranged with the first surface.
- 5. the encapsulating structure of CIS chips according to claim 1, it is characterised in that the second table of the CIS chip dies Face is provided with the first opening, exposes the pad；The plain conductor is arranged at the inwall of first opening.
- 6. the encapsulating structure of the CIS chips according to claim with regard to 5, it is characterised in that described in the plain conductor covering The bottom of first opening.
- 7. the encapsulating structure of CIS chips according to claim 5, it is characterised in that the CIS chip dies and the gold Between belonging to line layer, inorganic medium is additionally provided with the second surface of the CIS chip dies and the side wall of first opening Layer；The inorganic dielectric layer includes SiO2And/or SiN.
- 8. the encapsulating structure of the CIS chips according to claim with regard to 5, it is characterised in that be filled with first opening Epoxy resin extremely flushes with the second surface of the metallic circuit layer.
- 9. the encapsulating structure of CIS chips according to claim 1, it is characterised in that the surface of insulating layer is provided with dew Go out the second opening of metallic circuit layer conductor；The encapsulating structure also includes：Metal salient point, it is connected by the described second opening with the metallic circuit layer.
- 10. the encapsulating structure of CIS chips according to claim 1, it is characterised in that the transparent slide is glass.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721016520.7U CN207052606U (en) | 2017-08-14 | 2017-08-14 | A kind of encapsulating structure of CIS chips |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721016520.7U CN207052606U (en) | 2017-08-14 | 2017-08-14 | A kind of encapsulating structure of CIS chips |
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| Publication Number | Publication Date |
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| CN207052606U true CN207052606U (en) | 2018-02-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201721016520.7U Active CN207052606U (en) | 2017-08-14 | 2017-08-14 | A kind of encapsulating structure of CIS chips |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110649055A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving glare problem of CIS chip |
| CN113471347A (en) * | 2021-05-14 | 2021-10-01 | 南通越亚半导体有限公司 | LED embedded packaging substrate and manufacturing method thereof |
-
2017
- 2017-08-14 CN CN201721016520.7U patent/CN207052606U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110649055A (en) * | 2019-09-27 | 2020-01-03 | 华天科技（昆山）电子有限公司 | Wafer-level packaging method and packaging structure for improving glare problem of CIS chip |
| CN113471347A (en) * | 2021-05-14 | 2021-10-01 | 南通越亚半导体有限公司 | LED embedded packaging substrate and manufacturing method thereof |
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