CN207052599U - A kind of wire structures and the wafer with the wire structures - Google Patents
A kind of wire structures and the wafer with the wire structures Download PDFInfo
- Publication number
- CN207052599U CN207052599U CN201720994180.9U CN201720994180U CN207052599U CN 207052599 U CN207052599 U CN 207052599U CN 201720994180 U CN201720994180 U CN 201720994180U CN 207052599 U CN207052599 U CN 207052599U
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- China
- Prior art keywords
- insulating barrier
- wire structures
- wiring layer
- wire
- opening
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
The utility model discloses a kind of wire structures and with the wire structures wafer, be related to technical field of semiconductors, wherein the wire structures include：First insulating barrier, cover crystal column surface；First insulating barrier offers the first opening, exposes the metal pad of the first insulating barrier bottom；Wiring layer again, first surface of insulating layer is arranged at, is connected by the described first opening with the metal pad；Second insulating barrier, be sheathed on it is described connect up layer surface again, and when the distance between adjacent wires of wiring layer are more than preset value again, second interlayer that insulate being sheathed on adjacent wires is provided with spacing.The wire structures that the utility model embodiment is provided, the second insulating barrier is sheathed on connects up layer surface again, depends on again the arrangement of conductors of wiring layer so that the stress of each wire of wiring layer again of crystal column surface can uncoupling, so as to reduce silicon wafer warpage degree.
Description
Technical field
It the utility model is related to technical field of semiconductors, and in particular to a kind of wire structures and the crystalline substance with the wire structures
Circle.
Background technology
Wafer chip level chip-scale package (English full name：Wafer Level Chip Scale Packaging, referred to as：
WLCSP it is) a kind of advanced package technologies for developing rapidly in recent years, the technology includes many special manufacturing process, such as cloth again
Line layer (English full name：Redistribution Layer, referred to as：RDL) making, salient point preparation etc..Wafer is undergoing these works
Internal after skill process to accumulate larger stress, the macro manifestations of stress are the buckling deformation of wafer.Larger silicon wafer warpage
Precision and the automation mechanized operation of subsequent technique can be had a strong impact on, while brings many integrity problems.At present, with integrated chip
The continuous improvement of degree, and the use of large scale wafer, silicon wafer warpage problem also become increasingly severeer, it has also become WLCSP is sent out
One of faced significant challenge of exhibition.
Warpage essence is caused by the thermal coefficient of expansion difference of each encapsulating material.The existing side for solving silicon wafer warpage
Method is usually：Design novel wafer class encapsulation structure, modified technique flow and technological parameter etc..
The utility model proposes a kind of wire structures that can reduce silicon wafer warpage degree, Neng Gou in terms of wire structures
Silicon wafer warpage degree is further reduced on the basis of existing settling mode.
The content of the invention
In view of this, the utility model embodiment provides a kind of wire structures and the wafer with the wire structures, with
Solves the problems, such as the silicon wafer warpage of wafer-level packaging technique.
In a first aspect, the utility model embodiment provides a kind of wire structures, including：First insulating barrier, cover wafer
Surface；First insulating barrier offers the first opening, exposes the metal pad of the first insulating barrier bottom；Wiring layer again,
First surface of insulating layer is arranged at, is connected by the described first opening with the metal pad；Second insulating barrier, is sheathed on
It is described to connect up layer surface again, and when the distance between adjacent wires of wiring layer are more than preset value again, it is sheathed on adjacent lead
The second insulation interlayer on line is provided with spacing.
Alternatively, second insulating barrier offers the second opening, exposes the second insulating barrier bottom wiring layer again
Wire；The wire structures also include：Soldered ball or salient point, second opening is arranged at, is connected with the wire exposed.
Second aspect, the utility model embodiment are provided with first aspect or first aspect any one optional implementation
The wafer of wire structures described in mode.
The wire structures that the utility model embodiment is provided, the second insulating barrier is sheathed on connects up layer surface again, depends on
The arrangement of conductors of wiring layer again so that the stress of each wire of wiring layer again of crystal column surface can uncoupling, so as to reduce wafer
Angularity.
Brief description of the drawings
Feature and advantage of the present utility model can be more clearly understood by reference to accompanying drawing, accompanying drawing be schematically without
It is interpreted as carrying out any restrictions to the utility model, in the accompanying drawings：
Fig. 1 shows the structural representation of preceding road supplied materials wafer；
Fig. 2 shows the schematic diagram that the first insulating barrier is formed in preceding road supplied materials crystal column surface；
Fig. 3 shows the schematic diagram that wiring layer is formed again in the first surface of insulating layer；
Fig. 4 is shown is connecting up the schematic diagram of layer surface the second insulating barrier of formation again；
Fig. 5 shows the schematic diagram that soldered ball or salient point are set in the second surface of insulating layer；
Fig. 6 shows the top view of a wire in wire structures shown in Fig. 5.
Embodiment
In order that the purpose of this utility model, advantage, preparation method are clearer, it is new to this practicality below in conjunction with accompanying drawing
The implementation example of type is described in detail, and the example of the embodiment is shown in the drawings, and wherein part-structure is direct in accompanying drawing
Giving preferable structural material, it is clear that described embodiment is the utility model part of the embodiment, rather than whole
Embodiment.It should be noted that the embodiment being described with reference to the drawings is exemplary, the structural material shown in embodiment is also
Exemplary, it is only used for explaining the utility model, and can not be construed to limitation of the present utility model, each reality of the utility model
The accompanying drawing of example is applied merely to the purpose of signal, therefore is not necessarily to scale.Based on the embodiment in the utility model,
The every other embodiment that those skilled in the art are obtained under the premise of creative work is not made, it is new to belong to this practicality
The scope of type protection.
The utility model embodiment provide it is a kind of reduce silicon wafer warpage degree wire structures, the wire structures be arranged at as
Preceding road supplied materials crystal column surface shown in Fig. 1, the preceding road supplied materials wafer include insulating barrier 10 and are arranged at the surface of insulating barrier 10 gold
Belong to pad 20.30 be the other structures of preceding road supplied materials wafer insulating barrier bottom.
As shown in figure 5, the wire structures include the first insulating barrier 40, the again insulating barrier 60 of wiring layer 50 and second.
As shown in Fig. 2 the first insulating barrier 40 covers crystal column surface, and the first insulating barrier 40 offers the first opening, dew
Go out the metal pad of the bottom of the first insulating barrier 40.It is pointed out that the first insulating barrier 40 and preceding road supplied materials wafer herein is former
Some insulating barriers 10 are not same layers.
As shown in figure 3, wiring layer 50 is arranged at the surface of the first insulating barrier 40 again, connected by the first opening with metal pad 20
Connect.
As shown in figure 4, the second insulating barrier 60 is sheathed on again the surface of wiring layer 50, and ought wiring layer 50 again adjacent wires
The distance between when being more than preset value, be provided with spacing between the second insulating barrier 60 being sheathed on adjacent wires.
As a kind of optional embodiment of the present embodiment, as shown in figure 5, the second insulating barrier 60 offers the second opening,
Expose the wire of the bottom of the second insulating barrier 60 wiring layer 50 again.The wire structures also include soldered ball or salient point 70, are arranged at second
Opening, it is connected with the wire exposed.
Fig. 6 shows the top view of a wire in wire structures shown in Fig. 5.Wherein, 20 be wire structures by the
The metal pad 20,50 that the opening opened up on one insulating barrier 40 is exposed is the wire of wiring layer 50 again, and 60 be to be set in cloth again
Second insulating barrier 60 on the surface of line layer 50.As can be seen that the second insulating barrier 60 depends on again wiring layer 50 from Fig. 5 and Fig. 6
Arrangement of conductors, when the distance between adjacent two wires of wiring layer 50 are larger again, be sheathed on this two wires second
The disconnection of insulating barrier 60, spaced, and be not connected to, covering is again comprehensively with the second insulating barrier 60 in existing way for this
The surface of wiring layer 50 is different.
The wire structures that the utility model embodiment is provided, the second insulating barrier is sheathed on connects up layer surface again, depends on
The arrangement of conductors of wiring layer again so that the stress of each wire of wiring layer again of crystal column surface can uncoupling, so as to reduce wafer
Angularity.
The wire structures that the utility model embodiment is provided are in the preparation, first as shown in Figure 2 in preceding road supplied materials wafer table
Face forms the first insulating barrier 40, and forms the first opening on the surface of the first insulating barrier 40 to expose the gold of the bottom of the first insulating barrier 40
Belong to pad 20；Then as shown in figure 3, forming wiring layer 50 again on the surface of the first insulating barrier 40, then wiring layer 50 is opened by first
Mouth is connected with metal pad 20；Finally as shown in figure 4, forming the second insulating barrier on the surface of 50 and first insulating barrier of wiring layer 40 again
60, and carry out photoetching to the second insulating barrier 60 or corrode to make its patterning so that when between the adjacent wires of wiring layer 50 again
When spacing is more than predetermined threshold value, the second insulating barrier 60 between the adjacent wires is removed, and is formed the second insulating barrier 60 and is arranged
The wire structures of the distribution of wiring layer 50 are depended on again in the surface of wiring layer 50 again, the second insulating barrier 60.
Alternatively, the second opening can also be opened up to expose on the second insulating barrier 60 on the basis of structure shown in Fig. 4
The wire of bottom wiring layer 50 again, and set soldered ball or salient point it is connected with the wire exposed in the second opening.
Although being described in detail on example embodiment and its advantage, those skilled in the art can not depart from
In the case of protection domain of the present utility model spiritual and defined in the appended claims to these embodiments carry out various change,
Substitutions and modifications, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples,
While one of ordinary skill in the art be should be readily appreciated that in holding scope of protection of the utility model, time of processing step
Sequence can change.
In addition, application of the present utility model be not limited to the technique of the specific embodiment described in specification, mechanism,
Manufacture, material composition, means, method and step.From disclosure of the present utility model, as one of ordinary skill in the art
Will readily appreciate that, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means,
Method or step, the function or obtain substantially that wherein their execution are substantially the same with the corresponding embodiment of the utility model description
Identical result, they can be applied according to the utility model.Therefore, the appended claims for the utility model be intended to by
These techniques, mechanism, manufacture, material composition, means, method or step are included in its protection domain.
Claims (3)
- A kind of 1. wire structures, it is characterised in that including：First insulating barrier, cover crystal column surface；First insulating barrier offers the first opening, exposes the first insulating barrier bottom The metal pad in portion；Wiring layer again, first surface of insulating layer is arranged at, is connected by the described first opening with the metal pad；Second insulating barrier, be sheathed on it is described connect up layer surface again, and the distance between adjacent wires of wiring layer ought be more than again During preset value, the second insulation interlayer being sheathed on adjacent wires is provided with spacing.
- 2. wire structures according to claim 1, it is characterised in that second insulating barrier offers the second opening, dew Go out the wire of the second insulating barrier bottom wiring layer again；The wire structures also include：Soldered ball or salient point, second opening is arranged at, is connected with the wire exposed.
- 3. the wafer with the wire structures described in claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720994180.9U CN207052599U (en) | 2017-08-09 | 2017-08-09 | A kind of wire structures and the wafer with the wire structures |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720994180.9U CN207052599U (en) | 2017-08-09 | 2017-08-09 | A kind of wire structures and the wafer with the wire structures |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207052599U true CN207052599U (en) | 2018-02-27 |
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ID=61500151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720994180.9U Active CN207052599U (en) | 2017-08-09 | 2017-08-09 | A kind of wire structures and the wafer with the wire structures |
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| Country | Link |
|---|---|
| CN (1) | CN207052599U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951787A (en) * | 2021-01-27 | 2021-06-11 | 上海先方半导体有限公司 | Low-stress surface passivation structure for three-dimensional chip stacking |
-
2017
- 2017-08-09 CN CN201720994180.9U patent/CN207052599U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112951787A (en) * | 2021-01-27 | 2021-06-11 | 上海先方半导体有限公司 | Low-stress surface passivation structure for three-dimensional chip stacking |
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