CN103311131B - The method of micro convex point side direction undercutting is prevented in a kind of micro convex point manufacture process - Google Patents
The method of micro convex point side direction undercutting is prevented in a kind of micro convex point manufacture process Download PDFInfo
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- CN103311131B CN103311131B CN201310182205.1A CN201310182205A CN103311131B CN 103311131 B CN103311131 B CN 103311131B CN 201310182205 A CN201310182205 A CN 201310182205A CN 103311131 B CN103311131 B CN 103311131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
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Abstract
The invention discloses a kind of formation method of micro convex point, comprising: s1, form pad on a semiconductor substrate; S2, form dielectric layer at pad and semiconductor substrate surface, described dielectric layer offers window, and described window is corresponding with pad; S3, form Seed Layer on the surface of dielectric layer and pad; S4, form micro convex point at described Seed Layer electroplating surface; S5, Seed Layer around micro convex point in certain distance form barrier layer; S6, etching be not by Seed Layer that barrier layer covers; S7, reflux solder.The present invention proposes by the Seed Layer around micro convex point covers one deck etching barrier layer, like this when carrying out Seed Layer etching, Seed Layer below it can be protected from etching, thus prevent the phenomenon of side direction undercutting.Improve reliability and the yields of micro convex point processing and manufacturing.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, particularly prevent micro convex point side direction undercutting method in a kind of micro convex point manufacture process.
Background technology
Traditionally, IC chip and outside electrical connection in the mode of bonding the I/O on chip are connected to package carrier with metal lead wire and realize through packaging pin.Along with the expansion with integrated scale of reducing of IC chip feature sizes, I/O asks apart from constantly reduction, quantity are on the increase.When I/O spacing narrows down to below 70 μm, Wire Bonding Technology is just no longer applicable, must seek new technological approaches.
Wafer-Level Packaging Technology utilizes film distribution process again, I/O can be distributed on the whole surface of IC, and no longer only be confined to the neighboring area of narrow IC chip, thus solve the electrical connection problem of high density, thin space I/O chip.
In existing encapsulation technology, during plating micro convex point, side direction undercutting (undercutting) is very serious, and when micro convex point pitch is more and more less, the reliability of micro convex point will go wrong, and the self-strength of micro convex point and yield will decline.Owing to there will be side direction undercutting problem, so when carrying out Seed Layer etching, the selection of etching liquid and the control of etching technics will be restricted.
Summary of the invention
For the deficiencies in the prior art, the technical problem that the present invention solves is to provide in a kind of micro convex point manufacture process and prevents micro convex point side direction undercutting method, to improve reliability and the yields of micro convex point processing and manufacturing.
For solving above-mentioned technical problem, technical scheme of the present invention is achieved in that
A formation method for micro convex point, comprising:
S1, form pad on a semiconductor substrate;
S2, form dielectric layer at pad and semiconductor substrate surface, described dielectric layer offers window, and described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form micro convex point at described Seed Layer electroplating surface;
S5, Seed Layer around micro convex point in certain distance form barrier layer, and described certain distance meets: after the etching of step s6, and the end of Seed Layer just and the justified margin of micro convex point or be positioned at the outside of micro convex point;
S6, etching be not by Seed Layer that barrier layer covers;
S7, reflux solder.
Preferably, in the formation method of above-mentioned micro convex point, described step s5 specifically comprises: on the formation barrier layer, surface of micro convex point and Seed Layer, graphical described barrier layer, and the barrier layer stayed at least is covered in the Seed Layer around micro convex point in certain distance.
Preferably, in the formation method of above-mentioned micro convex point, described graphical barrier layer adopts photoetching process to carry out, by the barrier layer in certain distance around the barrier layer above photoetching reservation micro convex point and micro convex point, now the material on described barrier layer is light-sensitive material, in described step s7, also comprise the step removing barrier layer.
Preferably, in the formation method of above-mentioned micro convex point, described graphical barrier layer adopts dry etch process to carry out, and only retain the barrier layer around micro convex point in certain distance by dry etching, now the material on described barrier layer is polymeric material.
Preferably, in the formation method of above-mentioned micro convex point, described polymeric material is PI(polyimides) or PBO(polyphenyl and chew azoles).
Preferably, in the formation method of above-mentioned micro convex point, described semiconductor base is also formed with a layer insulating, described pad is positioned on this insulating barrier.
Preferably, in the formation method of above-mentioned micro convex point, described insulating barrier material is selected from silica or carborundum.
Preferably, in the formation method of above-mentioned micro convex point, described micro convex point is copper tin micro convex point.
Correspondingly, the invention also discloses the encapsulating structure preventing the undercutting of micro convex point side direction in a kind of micro convex point manufacture process, semiconductor base there is a layer insulating, on insulating barrier, preparation has metal pad, metal pad is electroplated one deck Seed Layer, in Seed Layer, preparation has micro convex point, covers etching barrier layer on the Seed Layer around micro convex point, and the Seed Layer covered by described etching barrier layer in its end after over etching just and the justified margin of micro convex point or be positioned at the outside of micro convex point.
Compared with prior art, the present invention proposes by the Seed Layer around micro convex point covers one deck etching barrier layer, like this when carrying out Seed Layer etching, Seed Layer below it can be protected from etching, thus prevent the phenomenon of side direction undercutting.Improve reliability and the yields of micro convex point processing and manufacturing.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 a ~ Fig. 1 l is depicted as in first embodiment of the invention the structural representation forming micro convex point;
Figure 2 shows that in the specific embodiment of the invention schematic flow sheet forming micro convex point;
To Figure 3 shows that in second embodiment of the invention by dry etching the structural representation after barrier etch;
Figure 4 shows that in second embodiment of the invention the structural representation after Seed Layer etching;
Fig. 5 is the structural representation being depicted as the barrier layer formed in third embodiment of the invention;
Figure 6 shows that barrier layer in third embodiment of the invention be etched after structural representation.
Embodiment
The present invention proposes by the Seed Layer around micro convex point covers one deck etching barrier layer, like this when carrying out Seed Layer etching, Seed Layer below it can be protected from etching, thus prevent the phenomenon of side direction undercutting.
Particularly, the embodiment of the invention discloses a kind of formation method of micro convex point, comprising:
S1, form pad on a semiconductor substrate;
S2, form dielectric layer at pad and semiconductor substrate surface, described dielectric layer offers window, and described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form micro convex point at described Seed Layer electroplating surface;
S5, Seed Layer around micro convex point in certain distance form barrier layer, and described certain distance meets: after the etching of step s6, and the end of Seed Layer just and the justified margin of micro convex point or be positioned at the outside of micro convex point;
S6, etching be not by Seed Layer that barrier layer covers;
S7, reflux solder.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be described in detail the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not making creative work, all belongs to the scope of protection of the invention.
Shown in ginseng Fig. 1 and Fig. 2, in the first embodiment of the invention, the formation method of micro convex point, comprising:
1) semiconductor base 101 being formed with insulating barrier 102 is on the surface provided, shown in ginseng Fig. 1 a.
Semiconductor base 101 is be formed with some semiconductor device and required wire structures, and material can be the various semi-conducting materials such as silicon, SiGe and silicon-on-insulator.
Insulating barrier material can be silica, carborundum etc., and its effect is conducting of barrier metal pad and substrate.
2) metal pad 201 is made on the insulating layer, shown in ginseng Fig. 1 b.
Metal pad 201 is tie point, can be the material such as aluminium or copper.
3) form dielectric layer 301 at metal pad and surface of insulating layer, and by the dielectric layer of photoetching above metal pad makes window, window is positioned at the top of metal pad, shown in ginseng Fig. 1 c.
Dielectric layer 301 is not damaged in encapsulation process for the protection of semiconductor base 101; the material of dielectric layer 301 can be insulating material or the benzocyclobutane olefine resin (Benzocyclobutene such as silica, silicon nitride, silicon oxynitride; BCB), the various organic polymer insulating material such as polyimides (polyimide, PI).
4) Seed Layer 401 is formed on the surface of dielectric layer and metal pad, shown in ginseng Fig. 1 d.
Seed Layer 401 is made by sputtering method or evaporation technology, and the material of Seed Layer is preferably Ti/Cu, and the effect of Ti is that its adhesive attraction and barrier metal copper enter silicon base, and the electrode when effect of Cu is for electroplating.
5) make Other substrate materials 501, and carry out micro convex point graphically by photoetching, electro-coppering tin micro convex point 601, shown in ginseng Fig. 1 e and Fig. 1 f.
6) stripping photolithography glue material 501, shown in ginseng Fig. 1 g.
7) on the formation barrier layer, surface 701 of micro convex point and Seed Layer, the material on barrier layer 701 is light-sensitive material, shown in ginseng Fig. 1 h.Light-sensitive material can be positive photoresist or negative photoresist.
8) carry out graphically by photoetching to barrier material, to retain the barrier layer around barrier material above micro convex point and micro convex point in certain distance, the certain distance at this place refers to the size can avoiding side direction undercutting when etching Seed Layer, that is meet: after the etching of step 9), the end of Seed Layer just with the justified margin of micro convex point or the outside being positioned at micro convex point, join shown in Fig. 1 i.
9) etching is not by the Seed Layer that barrier layer covers, and is positioned at the outside of micro convex point by the Seed Layer that barrier layer covers in its end after over etching, shown in ginseng Fig. 1 j.
10) barrier material be not etched is peeled off, shown in ginseng Fig. 1 k.
11) reflux solder, shown in ginseng Fig. 1 l.
In second embodiment of the invention, the formation method of micro convex point, comprising:
1) semiconductor base being formed with insulating barrier is on the surface provided.
Semiconductor base is be formed with some semiconductor device and required wire structures, and material can be the various semi-conducting materials such as silicon, SiGe and silicon-on-insulator.
Insulating barrier material can be silica, carborundum etc., and its effect is conducting of barrier metal pad and substrate.
2) metal pad is made on the insulating layer.
Metal pad is tie point, can be the material such as aluminium or copper.
3) form dielectric layer at metal pad and surface of insulating layer, and by the dielectric layer of photoetching above metal pad makes window, window is positioned at the top of metal pad.
Dielectric layer is not damaged in encapsulation process for the protection of semiconductor base; the material of dielectric layer can be insulating material or the benzocyclobutane olefine resin (Benzocyclobutene such as silica, silicon nitride, silicon oxynitride; BCB), the various organic polymer insulating material such as polyimides (polyimide, PI).
4) Seed Layer is formed on the surface of dielectric layer and metal pad.
Seed Layer is made by sputtering method or evaporation technology, and the material of Seed Layer is preferably Ti/Cu, and the effect of Ti is that its adhesive attraction and barrier metal copper enter silicon base, and the electrode when effect of Cu is for electroplating.
5) make Other substrate materials, and carry out micro convex point graphically by photoetching, electro-coppering tin micro convex point.
6) stripping photolithography glue material.
7) on the formation barrier layer, surface of micro convex point and Seed Layer, in the present embodiment, the material on barrier layer only needs common polymeric material.Such as PI(polyimides), PBO(polyphenyl and chew azoles) etc., can certainly be the light-sensitive material in execution mode one.
8) by dry etching, barrier material is etched, only retain the etching barrier layer materials on the Seed Layer around micro convex point in certain distance, the certain distance at this place refers to the size can avoiding side direction undercutting when etching Seed Layer, that is meet: after the etching of step 9), the end of Seed Layer is just and the justified margin of micro convex point or be positioned at the outside of micro convex point.
On the formation barrier layer, surface of micro convex point and Seed Layer, the thickness on the barrier layer of micro convex point and Seed Layer junction can be greater than the thickness of other position blocks layers, when therefore being undertaken etching by dry etching, the barrier layer of micro convex point and Seed Layer junction due to thickness larger, still exist after the barrier layer of other positions is etched away, shown in ginseng Fig. 3.
9) etching is not by the Seed Layer that barrier layer covers, and is positioned at the outside of micro convex point by the Seed Layer that barrier layer covers in its end after over etching, shown in ginseng Fig. 4.
10) reflux solder.
It is to be noted herein, in step (8), only take into account while the barrier layer of bottom is etched to expose Seed Layer, barrier layer above micro convex point is also etched clean situation in the lump, therefore in subsequent step, do not increase the step removed residue and stop, but in actual applications, if the thickness on barrier layer is greater than the thickness being positioned at barrier layer above Seed Layer above micro convex point, then in process barrier layer etched by dry etching, barrier etch above Seed Layer completes, but still there is barrier layer above micro convex point, now also need to comprise the step to remaining barrier layer above micro convex point and removing.
In third embodiment of the invention, compared with the first embodiment, the thickness on the barrier layer 802 formed in step 7) is heterogeneous, and the end face on barrier layer is positioned at same plane, shown in concrete ginseng Fig. 5.As shown in Figure 6, remaining barrier layer is positioned at upper surface and the sidewall of micro convex point on barrier layer 902 after etching.
In sum, the present invention proposes by the Seed Layer around micro convex point covers one deck etching barrier layer, like this when carrying out Seed Layer etching, Seed Layer below it can be protected from etching, thus prevent the phenomenon of side direction undercutting.Improve reliability and the yields of micro convex point processing and manufacturing.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present invention or essential characteristic, the present invention can be realized in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present invention is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the present invention.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (7)
1. prevent a method for micro convex point side direction undercutting in micro convex point manufacture process, it is characterized in that, comprising:
S1, form pad on a semiconductor substrate;
S2, form dielectric layer at pad and semiconductor substrate surface, described dielectric layer offers window, and described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form micro convex point at described Seed Layer electroplating surface;
S5, Seed Layer around micro convex point in certain distance form barrier layer, and described certain distance meets: after the etching of step s6, the end of Seed Layer just and the justified margin of micro convex point or be positioned at the outside of micro convex point,
Described step s5 specifically comprises: on the formation barrier layer, surface of micro convex point and Seed Layer, graphical described barrier layer, and make the barrier layer stayed at least be covered in the Seed Layer around micro convex point in certain distance, wherein, described graphical barrier layer adopts dry etch process to carry out, the barrier layer around micro convex point in certain distance is at least retained by dry etching, now the material on described barrier layer is polymeric material, and the thickness on the barrier layer of described micro convex point and Seed Layer junction can be greater than the thickness of other position blocks layers;
S6, etching be not by Seed Layer that barrier layer covers;
S7, reflux solder.
2. prevent the method for micro convex point side direction undercutting in micro convex point manufacture process according to claim 1, it is characterized in that: described polymeric material is PI or PBO.
3. in micro convex point manufacture process according to claim 1, prevent the method for micro convex point side direction undercutting, it is characterized in that: described semiconductor base is also formed with a layer insulating, described pad is positioned on this insulating barrier, and described insulating barrier material is selected from silica or carborundum.
4. prevent the method for micro convex point side direction undercutting in micro convex point manufacture process according to claim 1, it is characterized in that: described micro convex point is copper tin micro convex point.
5. prevent a method for micro convex point side direction undercutting in micro convex point manufacture process, it is characterized in that, comprising:
S1, form pad on a semiconductor substrate;
S2, form dielectric layer at pad and semiconductor substrate surface, described dielectric layer offers window, and described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form micro convex point at described Seed Layer electroplating surface;
S5, Seed Layer around micro convex point in certain distance form barrier layer, and described certain distance meets: after the etching of step s6, the end of Seed Layer just and the justified margin of micro convex point or be positioned at the outside of micro convex point,
Described step s5 specifically comprises: on the formation barrier layer, surface of micro convex point and Seed Layer, graphical described barrier layer, and making the barrier layer stayed at least be covered in the Seed Layer around micro convex point in certain distance, the thickness on the barrier layer of described micro convex point and Seed Layer junction can be greater than the thickness of other position blocks layers;
S6, etching be not by Seed Layer that barrier layer covers;
S7, reflux solder;
Wherein, described graphical barrier layer adopts photoetching process to carry out, by the barrier layer in certain distance around the barrier layer above photoetching reservation micro convex point and micro convex point, now the material on described barrier layer is light-sensitive material, and in described step S7, also comprise the step on the barrier layer of removing in described certain distance.
6. in micro convex point manufacture process according to claim 5, prevent the method for micro convex point side direction undercutting, it is characterized in that: described semiconductor base is also formed with a layer insulating, described pad is positioned on this insulating barrier, and described insulating barrier material is selected from silica or carborundum.
7. prevent the method for micro convex point side direction undercutting in micro convex point manufacture process according to claim 5, it is characterized in that: described micro convex point is copper tin micro convex point.
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762197B (en) * | 2013-12-24 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | The manufacture method of a kind of novel Damascus copper copper bonding structure |
| CN103943578B (en) * | 2014-04-04 | 2017-01-04 | 华进半导体封装先导技术研发中心有限公司 | Copper pillar bump structure and forming method |
| CN105810601A (en) * | 2016-04-19 | 2016-07-27 | 南通富士通微电子股份有限公司 | Semiconductor chip packaging structure and manufacturing method thereof |
| CN112045329B (en) * | 2020-09-07 | 2022-03-11 | 中国电子科技集团公司第二十四研究所 | Flip-chip bonding process method for ball mounting on metal substrate |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| US5872404A (en) * | 1994-06-02 | 1999-02-16 | Lsi Logic Corporation | Interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
| US6426281B1 (en) * | 2001-01-16 | 2002-07-30 | Taiwan Semiconductor Manufacturing Company | Method to form bump in bumping technology |
| CN101110376A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | Method for forming soldering projection and its etchant |
| CN101211798A (en) * | 2006-12-29 | 2008-07-02 | 台湾积体电路制造股份有限公司 | Solder tappet structure and its making method |
| CN101241865A (en) * | 2007-02-05 | 2008-08-13 | 百慕达南茂科技股份有限公司 | Flat top protrusion block structure and its making method |
| CN102315182A (en) * | 2010-07-08 | 2012-01-11 | 台湾积体电路制造股份有限公司 | Semiconductor chip and manufacturing method thereof |
| CN102842531A (en) * | 2011-06-23 | 2012-12-26 | 新科金朋有限公司 | Semiconductor device and method of forming interconnect structure over seed layer |
| CN102867757A (en) * | 2011-07-07 | 2013-01-09 | 台湾积体电路制造股份有限公司 | UBM etching methods for eliminating undercut |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6818545B2 (en) * | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
| US20070210450A1 (en) * | 2006-03-13 | 2007-09-13 | Jang Woo-Jin | Method of forming a bump and a connector structure having the bump |
-
2013
- 2013-05-15 CN CN201310182205.1A patent/CN103311131B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5872404A (en) * | 1994-06-02 | 1999-02-16 | Lsi Logic Corporation | Interconnect bump for flip-chip integrated circuit including integral standoff and hourglass shaped solder coating |
| US5656858A (en) * | 1994-10-19 | 1997-08-12 | Nippondenso Co., Ltd. | Semiconductor device with bump structure |
| US6426281B1 (en) * | 2001-01-16 | 2002-07-30 | Taiwan Semiconductor Manufacturing Company | Method to form bump in bumping technology |
| CN101110376A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | Method for forming soldering projection and its etchant |
| CN101211798A (en) * | 2006-12-29 | 2008-07-02 | 台湾积体电路制造股份有限公司 | Solder tappet structure and its making method |
| CN101241865A (en) * | 2007-02-05 | 2008-08-13 | 百慕达南茂科技股份有限公司 | Flat top protrusion block structure and its making method |
| CN102315182A (en) * | 2010-07-08 | 2012-01-11 | 台湾积体电路制造股份有限公司 | Semiconductor chip and manufacturing method thereof |
| CN102842531A (en) * | 2011-06-23 | 2012-12-26 | 新科金朋有限公司 | Semiconductor device and method of forming interconnect structure over seed layer |
| CN102867757A (en) * | 2011-07-07 | 2013-01-09 | 台湾积体电路制造股份有限公司 | UBM etching methods for eliminating undercut |
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