CN104091793B - Improve micro bump and the manufacture method of reliability - Google Patents
Improve micro bump and the manufacture method of reliability Download PDFInfo
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- CN104091793B CN104091793B CN201410346165.4A CN201410346165A CN104091793B CN 104091793 B CN104091793 B CN 104091793B CN 201410346165 A CN201410346165 A CN 201410346165A CN 104091793 B CN104091793 B CN 104091793B
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- pad
- passivation layer
- seed layer
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- micro bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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Abstract
The present invention relates to a kind of micro bump improving reliability and manufacture method, including semiconductor substrate, semiconductor substrate front is provided with passivation layer, arranging micro bump in passivation layer, micro bump includes being arranged at the pad of semiconductor substrate surface, the Seed Layer being arranged at bond pad surface and the micro convex point being arranged in Seed Layer；It is characterized in that: on the passivation layer of the periphery of described micro bump, etching groove is set.The manufacture method of described micro bump, uses following steps: make pad and passivation layer on a semiconductor substrate；Etching formation is windowed over the passivation layer, the position windowed and pad one_to_one corresponding；Surface makes Seed Layer over the passivation layer；Coat photoresist on the seed layer；Photoresist above pad is removed, the photoresist around pad, Seed Layer and passivation layer are removed；Pad makes salient point, carries out Reflow Soldering, form micro convex point.The present invention effectively prevents the extension of micro convex point crackle, improves micro convex point reliability.
Description
Technical field
The present invention relates to a kind of micro bump improving reliability and manufacture method, belong to high-density electronic package technical field.
Background technology
In order to adapt to electronic product to gentlier, less, thinner, the higher direction of reliability develop, high-density packages is had higher requirement by Electronic Packaging.Pitch micro convex point technology is the inexorable trend of future technical advances.The effect of micro convex point acts as IC(integrated circuit, integrated circuit) and circuit board between mechanically interconnected, be electrically interconnected effect.Owing to the thermal coefficient of expansion (CTE) of chip and base material is different, micro convex point can be caused in cold cycling test process to be subject to mutual effect of contraction so that it is can not free to contract and expand completely, thus deform upon, ultimately result in micro convex point fracture, reduce the reliability of micro convex point.
In order to prevent micro convex point from deforming and ftracture, encapsulation process needs fill underfill(underfill) material, thus protect the stability of micro bump.But, there is drawback in traditional method and structure, underfill material and passivation material adhesiveness each other is poor, easily at Interface Cracking, thus adds the hidden danger that micro convex point lost efficacy.
Summary of the invention
It is an object of the invention to overcome the deficiencies in the prior art, a kind of micro bump improving reliability and manufacture method are provided, solve underfill material and the poor defect of passivation material adhesiveness, make encapsulating structure more stable, and, this structure is effectively prevented the extension of micro convex point crackle, improves the reliability of micro convex point.
The technical scheme provided according to the present invention, the micro bump of described raising reliability, including semiconductor substrate, it is provided with passivation layer in semiconductor substrate front, micro bump is set in the passivation layer；Described micro bump includes being arranged at the pad of semiconductor substrate surface, the Seed Layer being arranged at bond pad surface and the micro convex point being arranged in Seed Layer；It is characterized in that: arrange etching groove in the periphery of described micro bump, etching groove is positioned on passivation layer, and etching groove is extended to the surface of semiconductor substrate by the upper surface of passivation layer.
Further, described etching groove is the annular etching groove around micro bump, or is multiple circular etch grooves being distributed in around micro bump.
Further, in described micro bump, pad is positioned in passivation layer, and Seed Layer covers passivation layer.
The manufacture method of the micro bump of described raising reliability, is characterized in that, uses following processing step:
(1) pad is made at semiconductor substrate；
(2) making passivation layer at semiconductor substrate and pad front, passivation layer thickness is 5～20 μm；
(3) etching formation is windowed over the passivation layer, the position windowed and pad one_to_one corresponding, windows and is extended to the upper surface of pad by the upper surface of passivation layer；
(4) surface makes Seed Layer over the passivation layer, and Seed Layer covers passivation layer and the surface of pad exposure, and seed layer thickness is 100nm～300nm；
(5) coating a layer photoetching glue on the seed layer, photoresist thickness is 15 μm～100 μm；
(6) make figure opening on a photoresist, and the photoresist above pad is removed；Meanwhile, the photoresist around pad, Seed Layer and passivation layer are removed, exposes the surface of semiconductor substrate, at the peripheral etching groove forming annular or multiple circular etching groove being distributed in around pad of pad；
(7) on pad, make salient point, salient point is carried out reflow soldering process, forms micro convex point；Meanwhile, photoresist and unnecessary Seed Layer are removed.
Further, the material of described pad is copper.
Further, the material of described passivation layer is PI.
Further, the material of described Seed Layer is copper.
Further, the material of described micro convex point is Sn.
The micro bump of raising reliability of the present invention and manufacture method, solve underfill material and the poor defect of passivation material adhesiveness so that encapsulating structure is more stable, and, this structure is effectively prevented the extension of micro convex point crackle, improves the reliability of micro convex point.
Accompanying drawing explanation
Fig. 1～Fig. 8 is the schematic diagram of micro bump manufacture process of the present invention.
Fig. 1 is the schematic diagram obtaining pad on a semiconductor substrate.
Fig. 2 is the schematic diagram making passivation layer on semiconductor substrate and pad.
Fig. 3 is to make the schematic diagram windowed over the passivation layer.
Fig. 4 is the schematic diagram making Seed Layer.
Fig. 5 is the schematic diagram at Seed Layer surface-coated photoresist.
Fig. 6 is the schematic diagram forming etching groove.
Fig. 7 is the schematic diagram forming salient point on pad.
Fig. 8 is the sectional view of a kind of embodiment of micro bump of the present invention.
Fig. 9 is the top view of Fig. 8.
Figure 10 is the top view of micro bump another kind embodiment of the present invention.
Serial number in figure: semiconductor substrate 1, micro bump 2, pad 3, passivation layer 4, Seed Layer 5, micro convex point 6, annular etching groove 7-1, circular etch groove 7-2.
Detailed description of the invention
Below in conjunction with concrete accompanying drawing, the invention will be further described.
As shown in Figure 8: the micro bump of described raising reliability includes semiconductor substrate 1, it is provided with passivation layer 4 in semiconductor substrate 1 front, passivation layer 4 arranges micro bump 2；Described micro bump 2 includes being arranged at the pad 3 on semiconductor substrate 1 surface, the Seed Layer 5 being arranged at pad 3 surface and the micro convex point 6 being arranged in Seed Layer 5；In described micro bump 2, pad 3 is positioned in passivation layer 4, and Seed Layer 5 covers passivation layer 4；
Being positioned on passivation layer 4 as it is shown in figure 9, arrange annular etching groove 7-1, annular etching groove 7-1 in the periphery of described micro bump 2, the bottom of annular etching groove 7-1 extends to the surface of semiconductor substrate 1；As shown in Figure 10, being arranged around multiple circular etch groove 7-2 in described micro bump 2, circular etch groove 7-2 is positioned on passivation layer 4, and the bottom of circular etch groove 7-2 extends to the surface of semiconductor substrate 1.
The operation principle of the present invention is: when micro convex point deforms or ftractures, and crackle typically can be extending transversely at underfill and passivation layer interface；In the present invention, being removed by passivation layer and arrange etching groove around micro bump, such underfill directly can contact with semiconductor substrate, increases adhesion；Time at cracks can spread to circular etch groove 7-2 or annular etching groove 7-1, the lateral transfer speed of crackle is restricted, and only along etching groove vertical migration, therefore, greatly reduces the speed of cracks can spread, improves the reliability of micro convex point.
The manufacture method of the micro bump of above-mentioned raising reliability, uses following processing step:
(1) as it is shown in figure 1, use plating or chemical plating method to make pad 3 in semiconductor substrate 1 front, the material of pad 3 is copper；
(2) as in figure 2 it is shown, at semiconductor substrate 1 and pad 3 front spin coating or one layer of passivation layer 4 of spraying, passivation layer 4 thickness is 5～20 μm, and the material of passivation layer 4 is PI(polyimides)；
(3) as it is shown on figure 3, etch formation on passivation layer 4 and window, the position windowed and pad 3 one_to_one corresponding, window and extended to the upper surface of pad 3 by the upper surface of passivation layer 4；
(4) as shown in Figure 4, using PVD electroplating technology to make Seed Layer 5 at passivation layer 4 upper surface, Seed Layer 5 thickness is 100nm～300nm, and Seed Layer 5 covers passivation layer 4 and the surface of pad 3 exposure, and the material of Seed Layer 5 is copper；
(5) as it is shown in figure 5, coat a layer photoetching glue in Seed Layer 4, depending on thickness is according to the height of salient point, photoresist thickness is 15 μm～100 μm；
(6) as shown in Figure 6, make figure opening on a photoresist, and the photoresist above pad 3 is removed；Meanwhile, the photoresist around pad 3, Seed Layer 5 and passivation layer 4 are removed, exposes the surface of semiconductor substrate 1；The shape of described figure opening as shown in Figure 9, Figure 10, for surrounding the annular of pad 3, or multiple circle being distributed in around pad 3；
(7) as it is shown in fig. 7, use the mode of plating or chemical plating to make salient point on pad 3, the material of salient point is Sn；
(8) as shown in Figure 8, above-mentioned salient point is carried out reflow soldering process, form micro convex point 6；Meanwhile, photoresist and unnecessary Seed Layer are removed.
Claims (5)
1. improve a manufacture method for the micro bump of reliability, it is characterized in that, use following processing step:
(1) pad (3) is made at semiconductor substrate (1)；
(2) making passivation layer (4) at semiconductor substrate (1) and pad (3) front, passivation layer thickness is 5～20 μm；
(3) window in passivation layer (4) upper etching formation, the position windowed and pad (3) one_to_one corresponding, window and extended to the upper surface of pad (3) by the upper surface of passivation layer (4)；
(4) making Seed Layer (5) at passivation layer (4) upper surface, the surface that Seed Layer (5) covers passivation layer (4) and pad (3) exposes, Seed Layer (5) thickness is 100nm～300nm；
(5) at Seed Layer (4) upper coating one layer photoetching glue, photoresist thickness is 15 μm～100 μm；
(6) make figure opening on a photoresist, and the photoresist of pad (3) top is removed；Meanwhile, pad (3) photoresist, Seed Layer (5) and passivation layer (4) around is removed, exposes the surface of semiconductor substrate (1), at the peripheral etching groove forming annular or multiple circular etching groove being distributed in around pad (3) of pad (3)；
(7) on pad (3), make salient point, salient point is carried out reflow soldering process, form micro convex point (6)；Meanwhile, photoresist and unnecessary Seed Layer are removed.
2. the manufacture method of the micro bump improving reliability as claimed in claim 1, is characterized in that: the material of described pad (3) is copper.
3. the manufacture method of the micro bump improving reliability as claimed in claim 1, is characterized in that: the material of described passivation layer (4) is PI.
4. the manufacture method of the micro bump improving reliability as claimed in claim 1, is characterized in that: the material of described Seed Layer (5) is copper.
5. the manufacture method of the micro bump improving reliability as claimed in claim 1, is characterized in that: the material of described micro convex point (6) is Sn.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410346165.4A CN104091793B (en) | 2014-07-18 | 2014-07-18 | Improve micro bump and the manufacture method of reliability |
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| CN201410346165.4A CN104091793B (en) | 2014-07-18 | 2014-07-18 | Improve micro bump and the manufacture method of reliability |
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| CN104091793A CN104091793A (en) | 2014-10-08 |
| CN104091793B true CN104091793B (en) | 2016-09-21 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107316817B (en) | 2016-04-26 | 2020-08-25 | 中芯国际集成电路制造(上海)有限公司 | Package and method of manufacturing the same |
| CN109148389B (en) * | 2018-07-11 | 2020-02-07 | 上海华虹宏力半导体制造有限公司 | Device and process for preventing crack generation during temperature cycle test |
Citations (4)
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|---|---|---|---|---|
| TWI244725B (en) * | 2004-05-26 | 2005-12-01 | Advanced Semiconductor Eng | Structure and method of forming metal buffering layer |
| CN1909223A (en) * | 2005-08-01 | 2007-02-07 | 三星电子株式会社 | Semiconductor package with ferrite shielding structure |
| CN1988143A (en) * | 2005-12-20 | 2007-06-27 | 富士通株式会社 | Semiconductor device and manufacturing method of the same |
| CN103545277A (en) * | 2012-07-11 | 2014-01-29 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI244725B (en) * | 2004-05-26 | 2005-12-01 | Advanced Semiconductor Eng | Structure and method of forming metal buffering layer |
| CN1909223A (en) * | 2005-08-01 | 2007-02-07 | 三星电子株式会社 | Semiconductor package with ferrite shielding structure |
| CN1988143A (en) * | 2005-12-20 | 2007-06-27 | 富士通株式会社 | Semiconductor device and manufacturing method of the same |
| CN103545277A (en) * | 2012-07-11 | 2014-01-29 | 矽品精密工业股份有限公司 | Semiconductor package and fabrication method thereof |
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