CN207020566U - Terminal resistance calibrates circuit - Google Patents
Terminal resistance calibrates circuit Download PDFInfo
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- CN207020566U CN207020566U CN201720802193.1U CN201720802193U CN207020566U CN 207020566 U CN207020566 U CN 207020566U CN 201720802193 U CN201720802193 U CN 201720802193U CN 207020566 U CN207020566 U CN 207020566U
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Abstract
The utility model provides a kind of terminal resistance calibration circuit, including：Terminal resistance, there is anode, negative terminal, intermediate level end and control terminal；First current source, the anode of first current source are connected to supply voltage, and the negative terminal of first current source is coupled to the anode of above-mentioned terminal resistance；Second current source, the anode of second current source couple the negative terminal of above-mentioned terminal resistance, the negativing ending grounding of second current source；Operational amplifier, the in-phase input end of the operational amplifier is connected to mid-level reference voltage, the inverting input of the operational amplifier couples the output end of the operational amplifier, and the output end of the operational amplifier couples the intermediate level end of above-mentioned terminal resistance；And finite state machine, the output end of the finite state machine couple the control terminal of the terminal resistance, to the terminal resistance output control signal.The utility model can export the terminal resistance close to target resistance, meet the required precision of SERDES transfer impedances matching.
Description
Technical field
It the utility model is related to electronic circuit field, more particularly to a kind of terminal resistance calibration circuit.
Background technology
SERDES (SERializer/DESerializer, the abbreviation of serializer/de-serializers) leads to as a kind of high speed serialization
Letter technology, extensively using data transfer between the chips.In order to obtain good data transfer effect, in transmitting terminal and reception
End is required for the terminal resistance of a fixed numbers, and terminal resistance resistance needed for each SERDES agreements may also be different, such as PCIE,
SATA protocol needs the terminal resistance that nominal value is 50 ohm, and USB3.0 agreements then need the terminal electricity that nominal value is 45 ohm
Resistance, but because the limitation of technique, it is difficult to the high-precision terminal resistance that resistance is equal to the fixed numbers is directly produced,
Therefore need in addition to calibrate the terminal resistance in chip, the termination resistance value in chip is approached the fixed number
Value, for convenience of stating, the resistance that resistance is equal to nominal value below is referred to as target resistance.
Utility model content
The utility model provides a kind of terminal resistance calibration circuit, can obtain high-precision terminal resistance, and ensure electricity
Road stability.
The utility model provides a kind of terminal resistance calibration circuit, including：
Terminal resistance, there is anode, negative terminal, intermediate level end and control terminal；
First current source, the anode of first current source are connected to supply voltage, and the negative terminal of first current source is coupled to
The anode of above-mentioned terminal resistance；
Second current source, the anode of second current source couple the negative terminal of above-mentioned terminal resistance, and second current source is born
End ground connection；
Operational amplifier, the in-phase input end of the operational amplifier are connected to mid-level reference voltage, the operation amplifier
The inverting input of device couples the output end of the operational amplifier, and the output end of the operational amplifier couples above-mentioned terminal
The intermediate level end of resistance；And
Finite state machine, the output end of the finite state machine couple the control terminal of the terminal resistance, to the terminal
Resistance output control signal.
Alternatively, terminal resistance calibration circuit also includes differential comparator, the first in-phase input end of the differential comparator
The anode of above-mentioned terminal resistance is coupled, the first inverting input of the differential comparator couples the negative terminal of above-mentioned terminal resistance, should
Second in-phase input end of differential comparator is coupled to the positive voltage of a differential reference voltage, and the second of the differential comparator is anti-phase
Input is coupled to the negative voltage of the differential reference voltage, and the output end of the differential comparator couples the defeated of the finite state machine
Enter end.
Alternatively, terminal resistance calibration circuit also includes subtracter and comparator, described in the anode of the subtracter couples
The anode of terminal resistance, the negative terminal of the negative terminal coupling terminal resistance of the subtracter；The in-phase input end of the comparator is connected to one
Reference voltage, the inverting input of the comparator couple the output end of the subtracter, described in the output end coupling of the comparator
The input of finite state machine.
In addition, terminal resistance calibration circuit can also include buffer, the output end of the buffer couples the finite state
The input of machine, the input of the buffer couple the output end of the differential comparator or the comparator.
Terminal resistance provided by the utility model calibrates circuit, is existed under the regulation of operational amplifier using two current sources
The anode and negative terminal of terminal resistance produce two voltages, and finite state machine is according to the difference and reference voltage or difference of the two voltages
Divide reference voltage difference result of the comparison de-regulation terminal resistance, be allowed to close to target resistance, compared with prior art, this practicality
The new influence for avoiding various disturbing factors in circuit, it is possible to increase the job stability of circuit, export high-precision close
In the terminal resistance of target resistance, meet required precision of the SERDES transmission for impedance matching.
Brief description of the drawings
Fig. 1 is the structural representation that the terminal resistance that the utility model embodiment provides calibrates circuit；
Fig. 2 is the structural representation of terminal resistance 100 in Fig. 1；
Fig. 3 is the structural representation that the terminal resistance that another embodiment of the utility model provides calibrates circuit；
Fig. 4 is the structural representation that the terminal resistance that the another embodiment of the utility model provides calibrates circuit；
Fig. 5 is a kind of structural representation of terminal resistance 200 in Fig. 3 and Fig. 4；
Fig. 6 is a kind of structural representation of operational amplifier 203 in Fig. 3 and Fig. 4；
Fig. 7 is another structural representation of operational amplifier 203 in Fig. 3 and Fig. 4.
Embodiment
It is new below in conjunction with this practicality to make the purpose, technical scheme and advantage of the utility model embodiment clearer
Accompanying drawing in type embodiment, the technical scheme in the embodiment of the utility model is clearly and completely described, it is clear that is retouched
The embodiment stated only is the utility model part of the embodiment, rather than whole embodiments.Based on the reality in the utility model
Example is applied, the every other embodiment that those of ordinary skill in the art are obtained under the premise of creative work is not made, is all belonged to
In the scope of the utility model protection.
Fig. 1 is the structural representation that the terminal resistance that the embodiment of the utility model one provides calibrates circuit.As shown in figure 1,
The anode of terminal resistance 100 is connected to the inverting input (while being also the negative terminal of current source 101) of comparator 102, terminal electricity
The negativing ending grounding of resistance 100, the coding of the control terminal input transmission of finite state machine 104 of terminal resistance 100；Comparator 102 it is same
Phase input is connected with reference voltage V ref, and output end is connected to the input of buffer 103；The output end of buffer 103 connects
The input of finite state machine 104 is connected to, the output end of finite state machine 104 is connected to the control terminal of terminal resistance 100.It is worth
It is noted that Fig. 1 only shows one embodiment of resistance terminal described in the utility model, terminal resistance school described in the utility model
Quasi- circuit can not also include buffer 103, and now, the output end of comparator 102 is connected directly to the defeated of finite state machine 104
Enter end.
Fig. 2 is the structural representation of terminal resistance 100 in Fig. 1.As shown in Fig. 2 control signal Ctr1, Ctr2, Ctr3,
Ctr4 is connected on the input of phase inverter 105,106,107,108 respectively, and the output end of phase inverter 105,106,107,108 connects respectively
In N-type metal-oxide-semiconductor NM11, NM21, NM31, NM41 grid；Resistance R11, R21, R31, R41 respectively with NM11, NM21, NM31,
NM41 drain electrode is connected, and is composed in series 4 branch roads, and together, the common point of all resistance forms terminal electricity to this 4 branch circuit parallel connections
The anode of resistance 100, the source electrode common point of all NMOS tubes form the negative terminal of terminal resistance 100.
Wherein, the in-phase input end input reference voltage Vref of comparator 102, the resistance of terminal resistance 100 are less than or waited
When target resistance, in the presence of current source 101, the anti-phase input terminal voltage of comparator 102 is correspondingly less than or waited
In or more than reference voltage V ref, when the homophase input terminal voltage of comparator 102 is more than anti-phase input terminal voltage, comparator
102 outputs are high level 1, are otherwise low level 0.The buffered device 103 of output of comparator 102 enters finite state machine after handling
104, it is assumed that initialization coding of the finite state machine 104 when upper electric is 0000, it can be seen from the structure of terminal resistance 100, this
When 4 branch roads be all turned on, overall parallel resistance is minimum, and is less than target resistance, and the anti-phase input terminal voltage of comparator 102 is small
In reference voltage V ref, therefore the output of comparator 102 is 1, promotes the coding of finite state machine 104 to add 1, in terminal resistance 100
Corresponding branch road disconnect, the increase of overall parallel resistance.Due to R41=2R31=4R21=8R11, it is switched on or switched off different branch
Road influences to differ for the resistance of terminal resistance 100, changes when the coding of finite state machine 104 from 0000 to 1111
During, the resistance of terminal resistance 100 constantly rises；Under the coding of a certain determination, the resistance of terminal resistance 100 is equal to or omited
During more than target resistance, the output of comparator 102 is 0, and the output of finite state machine 104 keeps constant；Terminal resistance 100 is realized
The target approached to target resistance.It is worth noting that, Fig. 2 only shows an implementation of resistance terminal described in the utility model
Example, the circuitry number of the first sub- resistance and the second sub- resistance included by the utility model can also be other situations.
Fig. 3 is the structural representation that the terminal resistance that another embodiment of the utility model provides calibrates circuit, such as Fig. 3 institutes
Show, the circuit includes：Terminal resistance 200, the first current source 201, the second current source 202, operational amplifier 203, differential ratio
Compared with device 204, buffer 205 and finite state machine 206, wherein, the terminal resistance 200 has anode, negative terminal, intermediate level end
And control terminal, the anode of wherein terminal resistance 200 are connected to the first in-phase input end and described of the differential comparator 204
The negative terminal of one current source 201, the negative terminal of terminal resistance 200 be connected to the differential comparator 204 the first inverting input and
The anode of second current source 202, the intermediate level end of terminal resistance 200 and the output end of the operational amplifier 203 connect
Connect；The anode of first current source 201 is connected to supply voltage VDD；The negativing ending grounding of second current source 202；It is described
The in-phase input end of operational amplifier 203 is connected to mid-level reference voltage Vcm, the operational amplifier 203 it is anti-phase defeated
Enter end to be connected with output end；Second in-phase input end of the differential comparator 204 and the positive voltage Vref+ of differential reference voltage
Connection, the negative voltage Vref- connections of the second inverting input and differential reference voltage, output end are defeated with the buffer 205
Enter end connection；The output end of the buffer 205 is connected with the input of the finite state machine 206；The finite state machine
206 output end is connected with the control terminal of the terminal resistance 200.It is worth noting that, Fig. 3 only show it is described in the utility model
One embodiment of resistance terminal, terminal resistance calibration circuit described in the utility model can not also include buffer 205, this
When, the output end of differential comparator 204 is connected directly to the input of finite state machine 206.
Fig. 4 is the structural representation that the terminal resistance that the another embodiment of the utility model provides calibrates circuit, with Fig. 3 phases
Than the differential comparator 204 is replaced with into subtracter 211 and comparator 212, anode and the terminal electricity of the subtracter 211
The anode connection of resistance 200, the negative terminal of the subtracter 211 is connected with the negative terminal of terminal resistance 200, the subtracter 211 it is defeated
Go out end to be connected with the inverting input of the comparator 212, the in-phase input end of the comparator 212 is connected to reference voltage
Vref, the output end of the comparator 212 are connected with the input of the buffer 205.
In the above two embodiments, first current source 201 can use p-type metal-oxide-semiconductor to realize, the p-type metal-oxide-semiconductor
Source electrode is connected to supply voltage VDD, and grid is connected to the first bias voltage Bias P, and drain electrode is connected to the terminal resistance 200
Anode.Second current source 202 uses N-type metal-oxide-semiconductor, and the source ground of the N-type metal-oxide-semiconductor, it is inclined that grid is connected to second
Voltage Bias N are put, drain electrode is connected to the negative terminal of the terminal resistance 200.
In the above two embodiments, the control terminal of the terminal resistance 200 receives from the output end of finite state machine 206
To a control signal, and the negative circuit contained by terminal resistance 200 is distributed in step-by-step.The terminal resistance 200 also includes：First
Sub- resistance and the second sub- resistance, wherein, the first sub- resistance includes controllable a plurality of branch road in parallel, wherein each bar branch road
Resistance value it is proportional；The a plurality of branch that the second sub- resistance includes with a plurality of branch road is corresponding in turn in the described first sub- resistance
Road, corresponding two branch parameters can use identical control signal with identical；The negative circuit include with it is described
The equal phase inverter of branch road quantity in first sub- resistance, the output end of each phase inverter, which is connected in the described first sub- resistance, to be corresponded to
The control terminal of branch road；The first parallel connected end of a plurality of branch road forms the anode of terminal resistance in the first sub- resistance；Described first
The second parallel connected end of a plurality of branch road is connected with the first parallel connected end of a plurality of branch road in the described second sub- resistance in sub- resistance, forms institute
State the intermediate level end of terminal resistance；The second parallel connected end of a plurality of branch road forms the terminal resistance in the second sub- resistance
Negative terminal；The input of all phase inverters forms the control terminal of the terminal resistance in the negative circuit.
Alternatively, each bar branch road in the described first sub- resistance includes the resistance and NMOS tube of series connection, resistance between each branch road
Resistance and NMOS tube channel width-over-length ratio successively into a ratio, and between each branch road between the resistance ratio of resistance and each branch road
The channel width-over-length ratio ratio of NMOS tube is identical；One end of resistance is connected to a bit in each branch road, and the point is the described first sub- resistance
The first parallel connected end；The other end of resistance is connected to the drain electrode of NMOS tube in the branch road in each branch road, NMOS tube in each branch road
Grid is respectively connecting to correspond to the output end of phase inverter in the negative circuit；The source electrode of NMOS tube is connected to separately in each bar branch road
A bit, another point is the second parallel connected end of the described first sub- resistance.
Accordingly, each branch road in the described second sub- resistance also includes the resistance and NMOS tube of series connection, electricity in different branch
Resistance and NMOS tube parameter corresponded to respectively with the described first sub- resistance branch road resistance and
The parameter of NMOS tube can be with identical；The drain electrode of NMOS tube is connected to a bit in each branch road, and the point is second son
First parallel connected end of resistance；The source electrode of NMOS tube is connected with one end of resistance in each branch road in each branch road, NMOS tube in each branch road
Grid be correspondingly connected to correspond to the grid of each branch road NMOS tube in the described first sub- resistance；The other end of resistance connects in each branch road
Another point is connected to, another point is the second parallel connected end of the described second sub- resistance.
Specifically, as shown in figure 5, in case of the first sub- resistance includes 4 branch roads, terminal resistance 200 includes 8
Resistance, 8 N-type metal-oxide-semiconductors and 4 phase inverters, wherein, the first sub- resistance includes tie point, the second branch road, the 3rd branch road and the
Four branch roads, the tie point include first resistor R1 and the first NMOS tube NM1, second branch road include second resistance R2 and
Second NMOS tube NM2, the 3rd branch road include 3rd resistor R3 and the 3rd NMOS tube NM3, and the 4th branch road includes the 4th
Resistance R4 and the 4th NMOS tube NM4, the first resistor R1, second resistance R2,3rd resistor R3 and the 4th resistance R4 resistance
Proportional successively, proportionate relationship can be 1：2：4：8, i.e. R4=2R3=4R2=8R1, correspondingly, described first
NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 channel width-over-length ratio are also proportional successively,
And proportionate relationship is identical with the first resistor R1, second resistance R2,3rd resistor R3 and the 4th resistance R4 proportionate relationship,
It is 1：2：4：8.Second sub- resistance includes the 5th branch road, the 6th branch road, the 7th branch road and the 8th branch road, and the 5th branch road includes
5th resistance R5 and the 5th NMOS tube NM5, the 6th branch road include the 6th resistance R6 and the 6th NMOS tube NM6, and the described 7th
Branch road includes the 7th resistance R7 and the 7th NMOS tube NM7, and the 8th branch road includes the 8th resistance R8 and the 8th NMOS tube NM8,
The 5th resistance R5, the 6th resistance R6, the 7th resistance R7 and the 8th resistance R8 resistance can respectively with the first resistor
R1, second resistance R2,3rd resistor R3 and the 4th resistance R4 resistance are identical, as R4=2R3=4R2=8R1, then R8=
2R7=4R6=8R5, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 can
With the parameter phase with the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 respectively
Together, channel width-over-length ratio also meets 1：2：4：8；Negative circuit includes the first phase inverter Inv1, the second phase inverter Inv2, the 3rd anti-phase
Device Inv3 and the 4th phase inverter Inv4.Fig. 4 only shows one embodiment of resistance terminal described in the utility model, the utility model institute
Including the first sub- resistance and the circuitry number of the second sub- resistance can also be other situations, such as four branch roads and more than, it is or few
In four branch roads.
As shown in figure 5, the first resistor R1, second resistance R2,3rd resistor R3 and the 4th resistance R4 one end difference
Drain electrode with the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 is connected；
The first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 grid point
The first phase inverter Inv1, the second phase inverter Inv2, the 3rd phase inverter Inv3 and the 4th phase inverter Inv4 output end are not connected to；
The first resistor R1, second resistance R2,3rd resistor R3 and the 4th resistance the R4 other end are connected to a bit, structure
Into the first parallel connected end of the described first sub- resistance；
The first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 source electrode connect
It is connected to the second parallel connected end for a little forming the first sub- resistance；
The 5th resistance R5, the 6th resistance R6, the 7th resistance R7 and the 8th resistance R8 one end are respectively with the described 5th
NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 source electrode connection；
The 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 grid point
The first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube NM4 grid are not connected to；
The 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 drain electrode connect
It is connected to the first parallel connected end for a little forming the second sub- resistance；
The 5th resistance R5, the 6th resistance R6, the 7th resistance R7 and the 8th resistance the R8 other end are connected to a bit, structure
Into the second parallel connected end of the described second sub- resistance.
As shown in figure 5, the number of phase inverter contained by negative circuit and the number of branches contained by the first sub- resistance and the
Number of branches contained by two sub- resistance, three are identical.And the branch road contained by the phase inverter and the first sub- resistance contained by negative circuit
It is corresponding.
As shown in figure 5, the coding step-by-step of finite state machine output is divided into control signal Ctr1, control signal Ctr2, control
Signal Ctr3 and control signal Ctr4, it is corresponding to distribute to the first phase inverter Inv1, the second phase inverter Inv2, the 3rd phase inverter
Inv3 and the 4th phase inverter Inv4, it is corresponding control the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3 and
The break-make of 4th NMOS tube, the first sub- resistance is set to switch between R1/15~8R1.In each branch circuit parallel connection of the second sub- resistance
In the case of, the first phase inverter Inv1, the second phase inverter Inv2, the 3rd phase inverter Inv3 and the 4th phase inverter Inv4 can also be passed through
The 5th NMOS tube NM5 corresponding to control, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 break-make,
The second sub- resistance is set to switch between R5/15~8R5.
For example, if be encoded to 4 the 0001 of finite state machine output, distribute to the first phase inverter Inv1, the
Two phase inverter Inv2, the 3rd phase inverter Inv3 and the 4th phase inverter Inv4 control signal Ctr1, control signal Ctr2, control letter
Number Ctr3 and control signal Ctr4 is followed successively by 0,0,0,1, corresponding after inverted processing to control the first NMOS tube NM1, the
The state of two NMOS tube NM2, the 3rd NMOS tube NM3 and the 4th NMOS tube is followed successively by logical, logical, switching.5th NMOS tube
NM5, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 8th NMOS tube NM8 are as the same.Now first contained by terminal resistance 200
Sub- resistance is 4R1/7, and the second sub- resistance is 4R5/7.
As shown in figure 5, according to an embodiment of the present utility model, every corresponding with the second sub- resistance of the first sub- resistance
Bar branch parameters can be with identical, i.e., the first ohmically each resistance of son can be equal to corresponding on the second sub-circuit with each NMOS tube
Each resistance and each NMOS tube, such as first resistor R1 is equal to the 5th resistance R5, and the first NMOS tube NM1 is equal to the 5th
NMOS tube NM5.According to another embodiment of the present utility model, the first ohmically each resistance of son can not also wait with each NMOS tube
Each resistance and each NMOS tube corresponding to being same as on the second sub-circuit, such as first resistor R1 are not equal to the 5th resistance R5, with
And first NMOS tube NM1 be not equal to the 5th NMOS tube NM5.
Terminal resistance described in the utility model calibrates circuit, is initialized after upper electricity, input mid-level reference electricity
Vcm is pressed, but level reference voltage Vcm does not have driving force, can not externally provide electric current, being directly accessed circuit can introduce
Very big deviation, therefore as shown in Figure 3 and 4, amplifier 203 is accessed in the form of unit gain, to provide a voltage with being somebody's turn to do
Level reference voltage Vcm is equal, but has the voltage Vcm ' of driving force, and above-mentioned terminal resistance calibration circuit is with voltage Vcm '
Center, electric current caused by the first current source 201 is injected to the first sub- resistance of terminal resistance 200, the second current source 202 will be flowed to
Electric current injection terminal resistance 200 the second sub- resistance, voltage Vr1 is obtained in the anode of terminal resistance 200, in terminal resistance
200 negative terminal obtains voltage Vr2, then voltage Vr1 is exported to the first in-phase input end of the differential comparator 204 shown in Fig. 3,
Voltage Vr2 is exported to the first inverting input of the differential comparator 204 shown in Fig. 3, comparison voltage Vr1 and voltage Vr2's
Difference Vr1-Vr2 and differential reference voltage difference Vref+-Vref- size, make as far as possible voltage Vr1 and voltage Vr2 difference Vr1-
Vr2 levels off to differential reference voltage Vref+-Vref-.
In fact, what is compared inside the differential comparator 204 shown in Fig. 3 is that voltage Vr1 and voltage Vr2 difference subtracts
Differential reference voltage is poor, i.e. the size of (Vr1-Vr2)-between (Vref+-Vref-) and 0, if (Vr1-Vr2)-(Vref+-
Vref-) it is more than 0, then the differential comparator 204 shown in Fig. 3 exports high level 1, is otherwise low level 0.Differential ratio shown in Fig. 3
Enter finite state machine 206 after being handled compared with the buffered device 205 of the output end of device 204, finite state machine 206 is with a clock frequency
The output of the differential comparator 204 shown in Fig. 3 is detected, if the output of the differential comparator 204 shown in Fig. 3 is 0, limited shape
The state of state machine 206 adds 1, if the output of differential comparator 204 shown in Fig. 3 is 1, the state of finite state machine 206 subtracts 1.When having
The initial code for limiting state machine 206 is 0000, i.e. the control signal of its output to terminal resistance 200 is 0000, terminal resistance 200
Contained inverter circuit controls each bar branch road to be all turned on, and now the overall parallel resistance of terminal resistance 200 is minimum, and is set
Surely it is less than target resistance so that (Vr1-Vr2)-(Vref+-Vref-)<Differential comparator 204 shown in 0, Fig. 3 exports low level
0, the state of finite state machine 206 adds 1, and the coding of finite state machine 206 is changed into 0001, controls anti-phase contained by terminal resistance 200
The overall parallel resistance increase of device circuit control terminal resistance 200, said process constantly circulates, total until terminal resistance 200
Body parallel resistance is more than target resistance, and the output level of differential comparator 204 shown in Fig. 3 is changed into 1 from 0, now locks limited shape
The state of state machine 206, make the overall parallel resistance of terminal resistance 200 closest to target resistance.When the initialization of finite state machine 206
Coding is 1111, then the overall parallel resistance of terminal resistance 200 is significantly greater than target resistance, the differential comparator shown in Fig. 3
204 outputs are 1, and the state of finite state machine 206 is gradually reduced, and the overall parallel resistance of terminal resistance 200 also reduces, until terminal
The overall parallel resistance of resistance 200 is less than target resistance.Certainly, if the branch road of the first sub- resistance of increase terminal resistance 200
Number, the digit of finite state machine 206 also accordingly increase, and can obtain resistance more accurately closer to the terminal resistance of target resistance
200。
And the differential comparator 204 shown in Fig. 3 is replaced with subtraction by the terminal resistance calibration circuit of the embodiment shown in Fig. 4
Device 211 and comparator 212, i.e., voltage Vr1 and voltage Vr2 mathematic interpolation is first carried out inside subtracter 211, then in comparator
212 compared with reference voltage V ref, that is, compares the size of (Vr1-Vr2) between-Vref and 0, if (Vr1-Vr2)-Vref is big
In 0, then the output high level 1 of comparator 212 shown in Fig. 4, is otherwise low level 0.The output end of comparator 212 shown in Fig. 4
The ratio between buffered device 205 enters finite state machine 206 after handling, finite state machine 206 is detected shown in Fig. 4 with a clock frequency
Compared with the output of device 212, if the output of the comparator 212 shown in Fig. 4 is 0, the state of finite state machine 206 adds 1, if Fig. 4
The shown output of comparator 212 is 1, then the state of finite state machine 206 subtracts 1.When the initial code of finite state machine 206 is
0000, i.e. the control signal of its output to terminal resistance 200 is 0000, and the inverter circuit control contained by terminal resistance 200 is each
Bar branch road is all turned on, and now the overall parallel resistance of terminal resistance 200 is minimum, and is set less than target resistance so that
(Vr1–Vr2)–Vref<Comparator 212 shown in 0, Fig. 4 exports low level 0, and the state of finite state machine 206 adds 1, finite state
The coding of machine 206 is changed into 0001, controls the overall parallel connection of the inverter circuit control terminal resistance 200 contained by terminal resistance 200
Resistance increase, said process constantly circulates, until the overall parallel resistance of terminal resistance 200 is more than target resistance, Fig. 4 it is shown it
The output level of comparator 212 is changed into 1 from 0, now locks the state of finite state machine 206, makes the overall electricity in parallel of terminal resistance 200
Hinder closest to target resistance.When the initialization coding of finite state machine 206 is 1111, then terminal resistance 200 is overall in parallel
Resistance is significantly greater than target resistance, and the output of comparator 212 shown in Fig. 4 is 1, and the state of finite state machine 206 is gradually reduced, terminal
The overall parallel resistance of resistance 200 also reduces, until the overall parallel resistance of terminal resistance 200 is less than target resistance.Certainly, such as
The circuitry number of first sub- resistance of fruit increase terminal resistance 200, the digit of finite state machine 206 also accordingly increase, can obtained
Resistance is more accurately closer to the terminal resistance 200 of target resistance.
Further, since first current source 201 occurs in some cases with electric current caused by the second current source 202
Not quite identical situation, now, the electric current of difference need to extract or inject from the operational amplifier 203, while described
Charge injection effect be present during the NMOS tube switch of each bar branch road in terminal resistance 200, larger transient current can be produced, equally
Need to extract or inject from the operational amplifier 203, therefore it is required that amplifier has good current regulation ability.
The operational amplifier 203 can use A class operational amplifiers, and structure is as shown in fig. 6, can also use AB classes to transport
Amplifier is calculated, structure is as shown in Figure 7.When 203 using A class operational amplifiers, its peak point current amplitude of oscillation is inclined no more than direct current
Put.Because its metal-oxide-semiconductor bias voltage (M6/M8/M4M/M11 grid voltages) is all fixed, therefore direct current biasing electricity
Stream is also fixed, can not externally provide the electric current more than biasing.When 203 using AB class operational amplifiers, its direct current biasing
Electric current is smaller than the peak point current amplitude of oscillation, and under identical bias current, AB classes amplifier provides bigger current swing, meets electricity
Road demand.The output impedance of other AB class amplifiers is lower, and when being extracted to amplifier or Injection Current, it is steady to be more beneficial for voltage Vcm '
Due to quiescent point.Therefore, the utility model embodiment preferentially uses AB class operational amplifiers.
In summary, the terminal resistance calibration circuit that the utility model embodiment provides, using two current sources in terminal
The anode and negative terminal of resistance produce two voltages, and differential comparator is by comparing the difference and differential reference voltage of the two voltages
To control the coding that finite state machine exports, finally make the stable target resistance of terminal resistance output, compared with prior art, this
Utility model avoids the influence of various disturbing factors in circuit, it is possible to increase the job stability of circuit, output are high-precision
Target resistance, meet required precision of the SERDES transmission for impedance matching.
It is described above, only specific embodiment of the present utility model, but the scope of protection of the utility model is not limited to
In this, any one skilled in the art is in the technical scope that the utility model discloses, the change that can readily occur in
Change or replace, should all cover within the scope of protection of the utility model.Therefore, the scope of protection of the utility model should be with power
The protection domain that profit requires is defined.
Claims (10)
1. a kind of terminal resistance calibrates circuit, it is characterised in that including：
Terminal resistance, there is anode, negative terminal, intermediate level end and control terminal；
First current source, the anode of first current source are connected to supply voltage, and the negative terminal of first current source is coupled to above-mentioned
The anode of terminal resistance；
Second current source, the anode of second current source couple the negative terminal of above-mentioned terminal resistance, and the negative terminal of second current source connects
Ground；
Operational amplifier, the in-phase input end of the operational amplifier are connected to mid-level reference voltage, the operational amplifier
Inverting input couples the output end of the operational amplifier, and the output end of the operational amplifier couples above-mentioned terminal resistance
Intermediate level end；And
Finite state machine, the output end of the finite state machine couple the control terminal of the terminal resistance, to the terminal resistance
Output control signal.
2. terminal resistance according to claim 1 calibrates circuit, it is characterised in that also including differential comparator, the difference
First in-phase input end of comparator couples the anode of above-mentioned terminal resistance, the first inverting input coupling of the differential comparator
The negative terminal of above-mentioned terminal resistance, the second in-phase input end of the differential comparator are coupled to the positive voltage of differential reference voltage, should
Second inverting input of differential comparator is coupled to the negative voltage of differential reference voltage, the output end coupling of the differential comparator
The input of the finite state machine.
3. terminal resistance according to claim 2 calibrates circuit, it is characterised in that also including buffer, the buffer
Output end couples the input of the finite state machine, and the input of the buffer couples the output end of the differential comparator.
4. terminal resistance according to claim 1 calibrates circuit, it is characterised in that also includes：
Subtracter, the anode of the subtracter couple the anode of the terminal resistance, the negative terminal coupling terminal resistance of the subtracter
Negative terminal；And
Comparator, the in-phase input end of the comparator are connected to reference voltage, subtract described in the inverting input coupling of the comparator
The output end of musical instruments used in a Buddhist or Taoist mass, the output end of the comparator couple the input of the finite state machine.
5. terminal resistance according to claim 4 calibrates circuit, it is characterised in that also including buffer, the buffer
Output end couples the input of the finite state machine, and the input of the buffer couples the output end of the comparator.
6. terminal resistance according to claim 1 calibrates circuit, it is characterised in that the terminal resistance includes：First son
Resistance, the second sub- resistance, and negative circuit, wherein the first sub- resistance includes controllable a plurality of branch road in parallel, wherein
The resistance value of each bar branch road is proportional；
The second sub- resistance includes a plurality of branch road corresponding with a plurality of branch road in the described first sub- resistance；And
The negative circuit includes multiple phase inverters corresponding with a plurality of branch road in the described first sub- resistance, and each phase inverter is corresponding
Control the corresponding branch road in the described first sub- resistance and in the second sub- resistance.
7. terminal resistance according to claim 6 calibrates circuit, it is characterised in that a plurality of branch road in the first sub- resistance
The first parallel connected end form terminal resistance anode；
The first of the second parallel connected end of a plurality of branch road and a plurality of branch road in the described second sub- resistance is in parallel in the first sub- resistance
End connection, form the intermediate level end of the terminal resistance；
The second parallel connected end of a plurality of branch road forms the negative terminal of the terminal resistance in the second sub- resistance；And
The input of all phase inverters forms the control terminal of the terminal resistance in the negative circuit.
8. terminal resistance according to claim 7 calibrates circuit, it is characterised in that each bar branch in the first sub- resistance
Road includes the resistance and NMOS tube of series connection, in each bar branch road the channel width-over-length ratio of the resistance of resistance and NMOS tube successively into
Ratio, the two proportionate relationship are identical；
The drain electrode of one end of resistance and NMOS tube connects in each bar branch road, the grid difference of NMOS tube in each bar branch road
It is connected to the output end that phase inverter is corresponded in the negative circuit；
The other end of resistance is connected to the first parallel connected end for a little forming the first sub- resistance in all branch roads；And
The source electrode of NMOS tube is connected to the second parallel connected end that another point forms the first sub- resistance in all branch roads.
9. terminal resistance according to claim 7 calibrates circuit, it is characterised in that each bar branch in the second sub- resistance
Road includes the resistance and NMOS tube of series connection, in each bar branch road the channel width-over-length ratio of the resistance of resistance and NMOS tube successively into
Ratio, the two proportionate relationship are identical；
The drain electrode of one end of resistance and NMOS tube connects in each bar branch road, the grid difference of NMOS tube in each bar branch road
It is connected to the output end that phase inverter is corresponded in the negative circuit；
The drain electrode of NMOS tube is connected to the first parallel connected end for a little forming the second sub- resistance in all branch roads；And
The other end of resistance is connected to the second parallel connected end that another point forms the second sub- resistance in all branch roads.
10. terminal resistance according to claim 1 calibrates circuit, it is characterised in that the operational amplifier uses AB classes
Operational amplifier.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720802193.1U CN207020566U (en) | 2017-07-04 | 2017-07-04 | Terminal resistance calibrates circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720802193.1U CN207020566U (en) | 2017-07-04 | 2017-07-04 | Terminal resistance calibrates circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10411703B1 (en) | 2018-06-05 | 2019-09-10 | Samsung Electronics Co., Ltd. | Impedance matched clock driver with amplitude control |
| CN111221369A (en) * | 2018-11-23 | 2020-06-02 | 比亚迪股份有限公司 | Low dropout linear regulator |
| US10826497B2 (en) | 2018-06-05 | 2020-11-03 | Samsung Electronics Co., Ltd. | Impedance matched clock driver with amplitude control |
| CN116667838A (en) * | 2023-06-07 | 2023-08-29 | 上海韬润半导体有限公司 | Calibration circuit for multiplexing various types of resistors in chip |
-
2017
- 2017-07-04 CN CN201720802193.1U patent/CN207020566U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10411703B1 (en) | 2018-06-05 | 2019-09-10 | Samsung Electronics Co., Ltd. | Impedance matched clock driver with amplitude control |
| US10826497B2 (en) | 2018-06-05 | 2020-11-03 | Samsung Electronics Co., Ltd. | Impedance matched clock driver with amplitude control |
| CN111221369A (en) * | 2018-11-23 | 2020-06-02 | 比亚迪股份有限公司 | Low dropout linear regulator |
| CN111221369B (en) * | 2018-11-23 | 2022-01-07 | 比亚迪半导体股份有限公司 | Low dropout linear regulator |
| CN116667838A (en) * | 2023-06-07 | 2023-08-29 | 上海韬润半导体有限公司 | Calibration circuit for multiplexing various types of resistors in chip |
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