CN203445844U - Mbus (meter bus) decoding circuit - Google Patents
Mbus (meter bus) decoding circuit Download PDFInfo
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- CN203445844U CN203445844U CN201320608031.6U CN201320608031U CN203445844U CN 203445844 U CN203445844 U CN 203445844U CN 201320608031 U CN201320608031 U CN 201320608031U CN 203445844 U CN203445844 U CN 203445844U
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Abstract
The utility model discloses an Mbus (meter bus) decoding circuit, which comprises a sampling resistor connected in series with the positive terminal of an Mbus, a dynamic differential amplification circuit, a shifting and inverting amplification circuit and a single-end decoding unit. According to the Mbus decoding circuit, a voltage change on the sampling resistor passes through two stages of amplification units, and a voltage change on the Mbus is amplified to avoid the phenomenon of decoding incapability due to the fact that the voltage of the input end of the decoding unit is approximate to that of a working power supply when the load current of the Mbus is low, so that the decoding sensitivity is improved, and the bit error rate is lowered; in addition, the amplification circuits are added to amplify transmitted signals on the Mbus, and a resistance value of the sampling resistor can be greatly reduced, so that the loading capability of the Mbus is enhanced, the power consumption of the sampling resistor is also lowered, and the reliability of the whole machine is improved.
Description
Technical field
The application relates to data decode technical field, particularly relates to a kind of decoding circuit.
Background technology
Mbus bus is a kind of special in consuming the Mbus bus of data/address bus design that measuring instrument sum counter transmits information when uploading data, adopt curent change mode to realize, < < CJ/T188 family increases 11mA～20mA during the current value ratio no signal when the uploading data by metering instrumented data transmission technology condition > > requirement Mbus bus.
Refer to Fig. 1 and Fig. 2, Fig. 1 is the electrical block diagram of traditional decoding circuit, and Fig. 2 is that traditional each key point current/voltage of decoding circuit changes oscillogram.
Wherein, when Vout end uploading data, the current signal in bus is as the Io waveform in Fig. 2, and now electric current I o produces voltage drop Vr0 at the two ends of sample resistance R0, and the change in voltage of Vout end is specifically referring to Vout in Fig. 2.Capacitor C 2 has energy storage effect, and due to the existence of capacitor C 2, therefore, the voltage signal of inverting input 2 pin of voltage comparator U1 is relatively constant, specifically referring to V2 in Fig. 2; And the voltage signal of in-phase input end 3 pin is synchronizeed with the voltage signal in Mbus bus, concrete voltage waveform is referring to the V3 in Fig. 2.Only have after change in voltage in Mbus bus surpasses the voltage drop of diode D2, output 1 pin of voltage comparator U1 just can produce upset to be changed, i.e. voltage drop on sample resistance R0 only has over just effectively decoding after the voltage drop on diode D2, and decoding voltage waveform is out referring to the V1 in Fig. 2.
Current signal during due to Mbus bus uploading data increases 11mA～20mA during than no signal, and diode D2 adopts germanium diode, tube voltage drop is generally 0.2～0.3V, and for the useful signal of can efficient decoding uploading, the resistance of sample resistance R0 must be not less than R0=0.3V/11mA=27 Europe.
Requirement according to < < CJ/T188 family with metering instrumented data transmission technology condition > >, bus voltage when Mbus bus uploading data, in the time of should be than no signal, bus voltage be higher than 10V, bus voltage when the unloaded uploading data of Mbus bus is Vcc 15V, due to, sample resistance is 27 Europe, and therefore, bus load can not surpass (15V-10V)/27 Europe=185mA.
The working power voltage of Mbus bus is Mbus bus working power, its magnitude of voltage Vcc, and when Mbus bus uploading data, electric current flows through sample resistance R0, and produces pressure drop V thereon
?, that at Vout end, obtain is Vcc-V
r0if the static load electric current of Mbus bus is less, V
?less, therefore, the voltage of Vout end is close to Vcc.
There is following shortcoming in traditional decoding circuit:
At Mbus bus static load electric current 1o hour, the voltage of Vout end is close to Vcc, be greater than the V of the input common mode voltage 0 of voltage comparator U1～(Vcc-1.5), therefore static load electric current I o hour, there will be and cannot decode or error code phenomenon, cause the error rate of traditional decoding circuit high.
Because sample resistance is larger, had a strong impact on Mbus bus load ability.
When bus load electric current reaches 300mA, the power loss on sample resistance is 2.43W, and sample resistance caloric value is large, wastes energy, very high to the heat radiation requirement of complete machine, causes the reliability decrease of complete machine.
Patent content
For solving the problems of the technologies described above, the embodiment of the present application provides a kind of decoding circuit, has solved bus load electric current hour, decoding circuit decoding poor sensitivity, the shortcoming that the error rate is high, improved simultaneously bus load capacity, reduced the loss of sample resistance, technical scheme is specific as follows:
A decoding circuit, is characterized in that, comprising: be connected on sample resistance, dynamic difference amplifying unit, displacement paraphase amplifying unit and the single-ended decoding unit of Mbus bus, wherein:
Described dynamic difference amplifying unit is connected with Mbus bus, for the voltage signal after described sample resistance sampling in Mbus bus is changed, carry out dynamic difference amplification, offer described displacement paraphase amplifying unit, and its reference voltage is that Mbus bus working power voltage dividing potential drop obtains;
Described displacement paraphase amplifying unit is connected with described dynamic difference amplifying unit, for the voltage signal displacement paraphase of described dynamic difference amplifying unit output is amplified, and offers described decoding unit;
Described decoding unit is connected with described displacement paraphase amplifying unit, for the voltage signal receiving being carried out to single-ended decoding processing, obtains the useful signal transmitting in Mbus bus.
Preferably, described dynamic difference amplifying unit comprises:
By the 3rd divider resistance and the 4th divider resistance ground connection, the first electric capacity being in parallel with described the 4th divider resistance;
In-phase input end is connected in the points of common connection place of described the 3rd divider resistance and the 4th divider resistance; Between output and inverting input, by the 6th feedback resistance, be connected positive supply termination positive supply, the first operational amplifier of negative power end earth terminal;
Anode is connected with Mbus bus, the second diode that negative electrode is connected with the inverting input of described the first operational amplifier by the 5th input resistance.
Preferably, described displacement paraphase amplifying unit comprises:
The second operational amplifier, its in-phase input end input preset reference voltage, inverting input is connected with the output of described the first operational amplifier by the 7th input resistance, and the output of the second operational amplifier is connected with described inverting input by the 8th feedback resistance.
Preferably, described decoding circuit mainly comprises: tertiary voltage comparator, the 3rd diode, and the second electric capacity.
The series arm that described the 3rd diode and the tenth minute piezoresistance and the 11 divider resistance form, wherein the anode of the 3rd diode is connected with the output of described the second operational amplifier as one end of this series arm, the other end ground connection of this series arm;
The in-phase input end of described tertiary voltage comparator, by the 9th input resistance, be connected with the output of described the second operational amplifier, inverting input is connected with the common point of the described ten minute piezoresistance and the 11 divider resistance, output is connected in inverting input by the 3rd electric capacity, and by the 4th capacity earth;
Described the second Capacitance parallel connection is in the two ends of described the 11 divider resistance.
Preferably, the resistance of described sample resistance is not more than 10 Europe.
Preferably, the resistance of described sample resistance is 3.9 Europe.
Preferably, the resistance of described sample resistance is 3 Europe.
Preferably, the resistance of described sample resistance is 2 Europe.
The technical scheme being provided from above the embodiment of the present application, this Mbus decoding circuit, before traditional decoding circuit, increased two-stage amplifying circuit, be dynamic difference amplifying unit and displacement paraphase amplifying unit, signal transmission in Mbus bus is amplified, and carry out signal intensity coupling, avoided Mbus bus static load electric current hour, the phenomenon that the voltage of single-ended decoding unit input cannot be decoded close to working power voltage, thus decoding sensitivity, stability, the error rate that reduced improved; Simultaneously, can greatly reduce the resistance of sample resistance, because amplifying circuit can be amplified to the decoding request that meets decoding unit by the voltage signal on sample resistance, thereby strengthen the load capacity of Mbus bus, also reduced the power consumption of sample resistance, improved the reliability of complete machine simultaneously.In addition, because the multiplication factor of amplifying circuit is adjustable, make to be transferred to the voltage signal that the signal transmission in the reflection Mbus bus of decoding unit changes, can set being not more than within the scope of power source voltage Vcc, sensitivity and the reliability of decoding have been improved, curent change scope while meanwhile, making this decoding circuit can adapt to wider uploading data.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the application, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is traditional decoding circuit structural representation;
Fig. 2 is the electric signal waveform figure of traditional each key point of decoding circuit;
Fig. 3 is a kind of decoding circuit schematic diagram of the embodiment of the present application;
Fig. 4 is the structural representation of a kind of decoding circuit of the embodiment of the present application;
Fig. 5 is the electric signal waveform figure of a kind of each key point of decoding circuit of the embodiment of the present application.
Embodiment
For the application's above-mentioned purpose, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the application is described in further detail.
Refer to Fig. 3, Fig. 3 is a kind of decoding circuit theory diagram of the embodiment of the present application, and this decoding circuit comprises: the sample resistance R0 in Mbus bus, dynamic difference amplifying unit 1, displacement paraphase amplifying unit 2, and single-ended decoding unit 3, wherein:
Two inputs of dynamic difference amplifying unit 1 are connected with the Vout end of Mbus bus, for to Mbus bus voltage, the voltage signal after sample resistance R0 sampling carries out differential amplification, and offering described displacement paraphase amplifying unit 2, its reference voltage is the operating voltage Vcc of Mbus bus.
While having signal transmission in Mbus bus, in Mbus bus, can produce a current change quantity, this current signal variable quantity obtains the voltage variety in Mbus bus after sample resistance samples, and dynamic difference amplifying unit 1 is exactly that the paraphase that is shifted of the voltage variety in Mbus bus is amplified.
The voltage of dynamic difference amplifying unit 1 output is irrelevant with the static load the being connected size in Mbus bus, only relevant with voltage variety during signal transmission in Mbus bus, can automatically adapt to the static load variation in Mbus bus.
Displacement paraphase amplifying unit 2, for anti-phase amplification that the voltage signal of dynamic difference amplifying unit 1 output is shifted, and carries out after Signal Matching, offers described single-ended decoding unit 3.
The voltage signal obtaining due to dynamic difference amplifying unit 1 output, it is the anti-phase amplifying signal of the signal that transmits in Mbus bus, through displacement paraphase amplifying unit 2, be shifted after paraphase amplification and Signal Matching, obtain identical with the voltage signal change direction of transmitting in Mbus bus, the amplifying signal that amplitude is different, and this voltage signal is offered to single-ended decoding unit 3.
Single-ended decoding unit 3, by the voltage signal the receiving processing of decoding, obtains the useful signal transmitting in Mbus bus.The anti-phase amplification of voltage variety that dynamic difference amplifying unit 1 produces when Mbus bus is uploaded to signal, then carries out, after anti-phase amplification, offering decoding unit 3 through displacement paraphase amplifying unit 2, and the processing of decoding, obtains decoded True Data.
In the Mbus decoding circuit that the present embodiment provides, because described dynamic difference amplifying unit 1 is the anti-phase amplification of voltage variety producing during by Mbus bus transfer useful signal, the voltage signal of output is not subject to the impact of the static load size that connects in Mbus bus, the decoding effect of the decoding circuit that therefore the embodiment of the present application provides is not subject to the static load connecting in Mbus bus to change big or small impact, can automatically adapt to the variation of the static load connecting in Mbus bus.
The decoding circuit that the present embodiment provides, before decoding circuit, increased two-stage amplifying circuit, be dynamic difference amplifying unit and displacement paraphase amplifying unit, signal transmission in Mbus bus is amplified and Auto-matching, avoided Mbus bus static load electric current hour, the voltage of the input of decoding unit, close to working power voltage, has been avoided the phenomenon that cannot decode, has been reduced the error rate; And, after by amplifying circuit, the signal transmission in Mbus bus being amplified, meet decoding request, greatly reduced the resistance of sample resistance, thereby strengthened the load capacity of Mbus bus, thereby also reduced the power consumption of sample resistance, and improved the reliability of complete machine, saved the energy;
Because the multiplication factor of two-stage amplifying circuit is all adjustable, the voltage signal that makes to be transferred to decoding unit can be set being not more than within the scope of power source voltage Vcc, thereby improve sensitivity and the reliability of decoding, simultaneously, curent change scope when this decoding circuit can adapt to wider uploading data, in the time of can adapting to uploading data, the excursion of electric current is 8mA～50mA.
Refer to Fig. 4 and Fig. 5, the structural representation of a kind of decoding circuit that Fig. 4 is the embodiment of the present application; Fig. 5 is the oscillogram at each key point place of described decoding circuit.
As shown in Figure 4, dynamic difference amplifying unit comprises: the first operational amplifier U1, the second diode D2, the 3rd divider resistance R3, the 4th divider resistance R4, the first capacitor C 1, the five input resistance R5, and the 6th feedback resistance R6.
The 3rd divider resistance R3 and the 4th divider resistance R4 form series arm, and the 3rd divider resistance R3 is connected with the Vout end of described Mbus bus, the 4th divider resistance R4 one end is connected with the 3rd divider resistance R3, and the other end is as the other end ground connection of this series arm.The first capacitor C 1 is parallel to the two ends of described the 4th divider resistance R4.
The common point that the in-phase input end of the first operational amplifier U1 is connected with the 4th divider resistance R4 with the 3rd divider resistance R3 is connected, inverting input is connected with Mbus bus by the second diode D2, the 5th input resistance R5, wherein, the anode of the second diode D2 is connected with Mbus bus, negative electrode is connected in the inverting input of the first operational amplifier U1 by the first input resistance R5, the 6th feedback resistance R6 is connected between output and inverting input, forms feedback loop.The positive power source terminal of the first operational amplifier U1 meets working power Vcc in succession, negative power end ground connection.
The voltage signal of the in-phase input end of the first operational amplifier U1 is the voltage in the first capacitor C 1, therefore substantially constant; Mbus bus is when uploading signal, curent change is as shown in the voltage waveform of the Io in Fig. 5, the voltage waveform of Vout end is as shown in the Vout voltage waveform in Fig. 5, when bus voltage changes, because the in-phase input end of the first operational amplifier U1 is substantially constant, the voltage signal of inverting input changes with bus voltage; During monobus change in voltage, there is difference in the first in-phase input end of operational amplifier U1 and the voltage signal of inverting input, and the first operational amplifier U1 amplifies difference, and its voltage waveform is as shown in the V1 voltage waveform in Fig. 5.
The ratio of the first divider resistance R3 and the second divider resistance R4 in this dynamic difference amplifying unit, identical with the ratio of the first feedback resistance R6 with the first input resistance R5, i.e. R4/R3=R6/R5=k1, thus guarantee the linear amplification of the first operational amplifier U1.Because the second diode D2 forward conduction voltage drop Vd2 is greater than the forward conduction voltage drop Vd1 of the first diode D1, when the signal transmission in Mbus bus does not change, the cathode voltage Vd2k=Vout-Vd2 of the second diode D2, cathode voltage Vd1k=Vout-Vd1 lower than the first diode D1, make to have a fixedly difference between two inputs of the first operational amplifier U1, export a stable preset value.
As can be seen from the above, while not uploading useful signal in Mbus bus, a fixed value of the first operational amplifier U1 output, and the voltage Vout of the output end vo ut of this fixed value and Mbus bus end is irrelevant, also with Mbus bus on the voltage drop that produces on sample resistance R1 of static load irrelevant, be the impact that the output voltage of U1 is not subject to the static load size that connects in Mbus bus, only relevant with the forward conduction voltage drop of the first diode D1 and the second diode D2.
When Mbus bus is uploaded the voltage signal that useful signal produces, while there is small voltage variety Δ Vo, the voltage signal of the in-phase input end of the first operational amplifier U1 is Vd1k=Vout-Vd1, and the voltage signal of inverting input changes with the voltage signal of Vout end.
As seen from the above analysis, when uploading voltage signal that useful signal produces in Mbus bus and having a small changes delta Vo, the output of the first operational amplifier U1 can change this effectively to amplify k1 doubly, due to the difference between the first operational amplifier U1 two inputs, in Mbus bus, to have small change in voltage and fixing difference sum, can effectively amplify like this Vout end and change small voltage signal, prevent that decoding unit below from misreading code, improve decoding sensitivity.
Displacement paraphase amplifying unit mainly comprises: the second operational amplifier U2, its in-phase input end input has reference voltage Vj, its inverting input is connected with the output of described dynamic difference amplifying unit by the 7th input resistance R7, output is connected in described inverting input by the 8th feedback resistance R8, and suppose R8/R7=k2, its positive power source terminal is connected with working power Vcc, negative power end ground connection.
Concrete, described reference voltage Vj requires to set according to the input voltage of the decoding unit of the voltage signal of described dynamic difference amplifying unit output and rear class.
More than find out, while there is no signal intensity in Mbus bus, while being quiescent operation state, the voltage that amplitude is lower of dynamic difference amplifying unit output output, the amplitude of the amplitude of this voltage and predeterminated voltage Vj differs larger, at the voltage that amplitude is higher of the second operational amplifier U2 output output; During Mbus bus transmitting data, the voltage that amplitude is higher of dynamic difference amplifying unit output output, this voltage and predeterminated voltage Vj amplitude differ less, and at the voltage that amplitude is lower of output output of the second operational amplifier U2, concrete waveform is as shown in V2 waveform in Fig. 5.
As seen from Figure 5, after anti-phase amplification, the change in voltage waveform of its output is consistent with change in voltage waveform in Mbus bus, but the amplitude of voltage signal changes and to have increased, and the voltage magnitude of its output can reach decoding request by adjusting the voltage amplification factor of the second operational amplifier.
Decoding unit mainly comprises: voltage comparator U3, the 3rd diode D3, the second capacitor C 2, wherein:
The in-phase input end of voltage comparator U3, by the 9th input resistance R9, be connected in the output of described displacement paraphase amplifying unit, output is connected in in-phase input end by the second capacitor C 2, form positive feedback loop, and this output is connected with one end of pull-up resistor R12, the pull-up resistor R12 other end connects DC power supply Vcc, and meanwhile, this output is by the 4th capacitor C 4 ground connection.
The series arm that the 3rd diode D3 and the tenth minute piezoresistance R10 and the 11 divider resistance R11 form, be connected between the output and ground of described the second operational amplifier U2, the anode of the 3rd diode D3 is connected with the output of the second operational amplifier U2 as one end of this series arm, and the negative electrode of the 3rd diode D3 is by the tenth minute piezoresistance R10 and the 11 divider resistance R11 ground connection.Simultaneously, the inverting input of voltage comparator U3 is connected in the points of common connection place of the tenth minute piezoresistance R10 and the 11 divider resistance R11, the second capacitor C 2 is connected in parallel on the two ends of the 11 divider resistance R11, utilizing the tenth minute voltage on piezoresistance R10 is the second capacitor C 2 chargings, and the voltage in the second capacitor C 2 is remained unchanged substantially.
Due to the existence of the second capacitor C 2, the voltage signal of the inverting input of voltage comparator U3 is relatively stable, the voltage waveform as shown in V4 in Fig. 5; The voltage waveform of the voltage waveform of the in-phase input end of voltage comparator U3 as shown in V3 in Fig. 5, the waveform voltage signal of the output of same the second operational amplifier U2 is identical; The output of voltage comparator U3 is exported voltage signal in decoded Mbus bus, and the voltage waveform as shown in Vrx in Fig. 5 is about to the voltage signal that after the voltage signal amplification of Vout, voltage waveform direction that obtain and Vout is identical, voltage magnitude is different.
The embodiment of the present application adopts the principle of single-ended dynamic amplification, during by Mbus bus transfer useful signal, the variable quantity of the voltage signal of output end of main amplifies, to meet the decoding request of decoding unit below, avoided in Mbus bus static load electric current hour, the voltage of the input of decoding unit approaches the working power voltage Vcc of Mbus bus, thereby has avoided the phenomenon that cannot decode, reduced the error rate.
Simultaneously, existence due to amplifying circuit, sample resistance R0 in Mbus bus is reduced greatly, in the present embodiment, can make sample resistance R0 be decreased to 2 Europe, take Mbus bus working power voltage as 15V be example, voltage signal when signal is uploaded in the zero load of Mbus bus, the high 10V of voltage than Mbus bus during without signal transmission, now, the load current of Mbus bus can not surpass (15V-10V)/2 Europe=2500mA, far away the maximum load current 185mA when using traditional decoding circuit.
Sample resistance R0 reduces greatly, has reduced the electric energy that sample resistance consumes, and has saved the energy, and the caloric value on sample resistance reduces greatly, the requirement of the heat dispersion of complete machine is reduced, thereby improved the reliability of complete machine.
Because this circuit adopts two-stage amplifying circuit, the voltage variety producing when transmitting useful signal in Mbus bus amplifies, and the multiplication factor of two-stage amplifying circuit is all adjustable, making to be transferred to signal transmission in the Mbus bus of decoding unit can set being not more than within the scope of power source voltage Vcc, thereby improve sensitivity and the reliability of decoding, curent change scope while meanwhile, making this decoding circuit can adapt to wider uploading data.
In sum, the decoding circuit that the present embodiment provides, adopt single-ended dynamic amplification principle, avoid static load electric current in Mbus bus hour to occur the phenomenon that cannot decode, reduced the error rate, greatly improved the load capacity of Mbus bus, reduced the power consumption of sample resistance simultaneously, the heat dispersion of complete machine is not had to higher requirement, improved the reliability of complete machine, and decoding effect is not subject to the impact of the static load electric current dynamic change in Mbus bus.The present embodiment has provided dynamic difference amplifying unit, displacement paraphase amplifying unit; and the concrete circuit structure of decoding unit; this can not limit the application's protection range, and those skilled in the art can carry out change and the increase and decrease on the element in circuit according to the application's basic principle.
It will be appreciated by persons skilled in the art that operational amplifier, the electric capacity of the employing in the present embodiment, the parameter value of resistance can be determined as the case may be, the application does not limit this.
The above is only the application's embodiment; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the application's protection range.
Claims (8)
1. a Mbus decoding circuit, is characterized in that, comprising: be connected on sample resistance, dynamic difference amplifying unit, displacement paraphase amplifying unit and the single-ended decoding unit of Mbus bus, wherein:
Described dynamic difference amplifying unit is connected with Mbus bus, for the described sample resistance voltage signal of process in Mbus bus is changed, carry out dynamic difference amplification, offer described displacement paraphase amplifying unit, and its reference voltage is described Mbus bus working power voltage value;
Described displacement paraphase amplifying unit is connected with described dynamic difference amplifying unit, for the anti-phase amplification of voltage signal the displacement that described dynamic difference amplifying unit is exported, and offers described decoding unit;
Described decoding unit is connected with described displacement paraphase amplifying unit, for processing that the voltage signal receiving is decoded, obtains the useful signal transmitting in Mbus bus.
2. Mbus decoding circuit according to claim 1, is characterized in that, described dynamic difference amplifying unit comprises:
With described the 3rd divider resistance and the 4th divider resistance ground connection;
The first electric capacity being in parallel with described the 4th divider resistance; In-phase input end is connected in the points of common connection place of described the 3rd divider resistance and the 4th divider resistance, is connected positive supply termination positive supply, the first operational amplifier of negative power end ground connection between output and inverting input by the 6th feedback resistance;
Anode is connected with Mbus bus, the second diode that negative electrode is connected with the inverting input of the first operational amplifier by the 5th input resistance.
3. decoding circuit according to claim 2, is characterized in that, described displacement paraphase amplifying unit comprises:
The second operational amplifier, its in-phase input end input preset reference voltage, inverting input is connected with the output of described the first operational amplifier by the 7th input resistance, and the output of the second operational amplifier is connected with described inverting input by the 8th feedback resistance.
4. decoding circuit according to claim 3, is characterized in that, described decoding unit mainly comprises: tertiary voltage comparator, the 3rd diode, and the second electric capacity;
The series arm that described the 3rd diode and the tenth minute piezoresistance and the 11 divider resistance form, wherein the anode of the 3rd diode is connected with the output of described the second operational amplifier as one end of this series arm, the other end ground connection of this series arm;
The in-phase input end of described tertiary voltage comparator, by the 9th input resistance, be connected with the output of described the second operational amplifier, inverting input is connected with the common point of the described ten minute piezoresistance and the 11 divider resistance, output is connected in in-phase input end by the 3rd electric capacity, and by the 4th capacity earth;
Described the second Capacitance parallel connection is in the two ends of described the 11 divider resistance.
5. according to the decoding circuit described in claim 1-4 any one, it is characterized in that, the resistance of described sample resistance is not more than 10 Europe.
6. decoding circuit according to claim 5, is characterized in that, the resistance of described sample resistance is 3.9 Europe.
7. decoding circuit according to claim 5, is characterized in that, the resistance of described sample resistance is 3 Europe.
8. decoding circuit according to claim 5, is characterized in that, the resistance of described sample resistance is 2 Europe.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320608031.6U CN203445844U (en) | 2013-09-29 | 2013-09-29 | Mbus (meter bus) decoding circuit |
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| CN201320608031.6U CN203445844U (en) | 2013-09-29 | 2013-09-29 | Mbus (meter bus) decoding circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107833452A (en) * | 2017-11-15 | 2018-03-23 | 安徽南瑞中天电力电子有限公司 | A kind of strong type of load capacity III of MBUS buses, IV type collector |
| CN109240962A (en) * | 2017-07-11 | 2019-01-18 | 杭州海康威视数字技术股份有限公司 | A kind of MBUS master station signal processing unit and the equipment with it |
| CN109522260A (en) * | 2018-12-20 | 2019-03-26 | 苏州路之遥科技股份有限公司 | A kind of monobus communication signal repeat circuit |
-
2013
- 2013-09-29 CN CN201320608031.6U patent/CN203445844U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109240962A (en) * | 2017-07-11 | 2019-01-18 | 杭州海康威视数字技术股份有限公司 | A kind of MBUS master station signal processing unit and the equipment with it |
| CN107833452A (en) * | 2017-11-15 | 2018-03-23 | 安徽南瑞中天电力电子有限公司 | A kind of strong type of load capacity III of MBUS buses, IV type collector |
| CN109522260A (en) * | 2018-12-20 | 2019-03-26 | 苏州路之遥科技股份有限公司 | A kind of monobus communication signal repeat circuit |
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