CN109471825B - Mbus interface control circuit - Google Patents

Abstract

The invention provides an Mbus interface control circuit, which includes a level control reference module, which generates a reference voltage according to the control signal sent by the host, and sends the reference voltage to the voltage conversion and logic control module; a signal sampling receiving module, which performs voltage conversion and logic control. The control module samples the current signal and generates a data signal transmitted to the host based on the sampling signal; the logic current limiting protection module generates a control voltage based on the sampling signal and sends the control voltage to the voltage conversion and logic control module; the voltage conversion and logic control module , according to the reference voltage and control voltage, the current signal of the M_BUS interface module is controlled on and off, and the current signal is transmitted to the signal sampling receiving module; the M_BUS interface module is used to connect the subsequent MBUS slave circuit. Through logical control between hardware circuits, the present invention realizes overcurrent protection, power on and off and signal transmission control of the MBUS line, reduces losses to the greatest extent, and greatly improves the stability and reliability of the MBUS circuit.

Description

A kind of Mbus interface control circuit

Technical field

The invention relates to the technical fields of communication and Internet of Things, and in particular to an Mbus interface control circuit.

Background technique

Meter bus (M-Bus) is a new bus structure. The main feature of M-Bus is that it supplies power and transmits serial data simultaneously through two non-polar transmission lines, and each substation (confirmed with different IDs) is connected in parallel. On the M-Bus bus. When M-Bus is used in energy consumption intelligent management systems for various instruments or related devices, relevant data or signals can be collected and transmitted to the concentrator, and then transmitted to the main station through the corresponding interface. The use of M-Bus can greatly simplify the wiring and connection of energy consumption intelligent management systems in residential areas, offices and other places, and has the characteristics of simple structure, low cost and high reliability.

In the existing technology, commonly used M-Bus circuits include the following types:

1) The strength of the received signal and the stability of the signal output are improved through the logical combination of the pre-filtering differential amplification circuit and the signal output circuit, thereby increasing the number of nodes loaded, improving the load capacity of the circuit and the anti-interference ability of the circuit signal , this solution does not have the function of current abnormality detection. Once an overcurrent problem such as a short circuit occurs in the rear pole, it is easy to cause the front-stage circuit to burn out and become unrecoverable. In addition, because this solution uses a multi-stage amplification circuit and a filter circuit, the The MBUS receiving circuit alone is very complex. If transmitting related circuits are added, the entire MBUS interface will be more complex, larger in size, and more costly.

2) The circuit is built with discrete components and must be matched with a microcontroller and other controllers to achieve complete overload protection, signal transmission and power supply functions. This makes the entire system respond slowly and may cause the risk of system hang-up. Reliability Sex is low.

3) By simplifying the number of discrete components, the M-BUS interface circuit is completed, and MCU data is sent and received through the control of transistors and voltage divider resistors. In the circuit design, due to the difference in transistors, this solution will lead to different working circuits. The trigger current is different, which affects the consistency of the product, and easily causes the data receiving terminal RX to be in an intermediate state, which in turn leads to confusion of the sampling data. In addition, the current limiting protection function directly uses an overcurrent protection device. Once the rear pole is short-circuited, the overcurrent The current device will protect and disconnect the circuit. This time, the function of the interface circuit must be restored by manually replacing the device. The circuit does not have a self-restoring function and has poor practicality.

Contents of the invention

In view of the above problems, the present invention is proposed to provide an Mbus interface control circuit that overcomes the above problems or at least partially solves the above problems.

The embodiment of the present invention provides an Mbus interface control circuit, which includes a voltage conversion and logic control module, a level control reference module, a logic current limiting protection module, a signal sampling receiving module, and a level control reference module respectively connected to the voltage conversion and logic control module. M_BUS interface module;

The level control reference module is connected to the host and is used to generate a reference voltage according to the control signal sent by the host and send the reference voltage to the voltage conversion and logic control module;

The signal sampling receiving module is connected to the logic current limiting protection module and is used to sample the current signal of the voltage conversion and logic control module, generate a data signal transmitted to the host according to the sampling signal, and send the sampling signal to The logical current limiting protection module;

The logic current limiting protection module is used to generate a control voltage according to the sampling signal and send the control voltage to the voltage conversion and logic control module;

The voltage conversion and logic control module is used to control the current signal of the M_BUS interface module on and off according to the reference voltage and the control voltage, and at the same time transmit the current signal to the signal sampling receiving module;

The M_BUS interface module is used to connect the downstream MBUS slave circuit.

Wherein, the level control reference module includes resistors R1, R2, R3, R11, NMOS tube K1, PMOS tube K2, the TXD interface of the host is connected to the gate of the NMOS tube K1, and the source of the NMOS tube K1 The pole is connected to the ground network, the drain of the NMOS tube K1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the power supply network V1, and the drain of the NMOS tube K1 is also connected to the The gate of the PMOS tube K2 is connected, the drain of the PMOS tube K2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the power supply network V1, and the source of the PMOS tube K2 is simultaneously connected to the resistor. R2 and R3 are connected to the voltage conversion and logic control module, the other end of the resistor R2 is connected to the power network V1, and the other end of the resistor R3 is connected to the ground network.

Among them, the logic current limiting protection module includes resistors R6, R7, comparator U1 and PMOS tube K4. One end of the resistor R6 is connected to the power supply network V1, and the other end is connected to one end of the resistor R7 and at the same time connected to the comparator U1. The third pin of the resistor R7 is connected to the ground network, the fourth pin of the comparator U1 is connected to the signal sampling receiving module, and the fifth pin of the comparator U1 is connected to the power network V1 . The second pin of the comparator U1 is connected to the ground network, the first pin of the comparator U1 is connected to the gate of the PMOS tube K4, and the drain of the PMOS tube K4 is connected to the power network V1. The source of the PMOS tube K4 is connected to the voltage conversion and logic control module.

Wherein, the signal sampling receiving module includes a sampling resistor R8, a comparator U3, a sampling amplifier U4 and resistors R9 and R10. One end of the sampling resistor R8 is connected to the power supply network V2 and the third pin of the sampling amplifier U4 respectively. connection, the other end of the sampling resistor R8 is connected to the second pin of the sampling amplifier U4 and the voltage conversion and logic control module respectively, and the 4th pin of the sampling amplifier U4 is connected to the power supply network V2 , the fifth pin of the sampling amplifier U4 is connected to the ground network, the first pin of the sampling amplifier U4 is connected to the fourth pin of the comparator U3 and the logic current limiting protection module respectively, and the resistor One end of R9 is connected to the power network V1, the other end of the resistor R9 is connected to one end of the resistor R10 and the third pin of the comparator U3, and the other end of the resistor R10 is connected to the ground network. The fifth pin of the comparator U3 is connected to the power supply network V1, the first pin of the comparator U3 is connected to the RXD interface of the host, and the second pin of the comparator U3 is connected to the ground network.

Wherein, the voltage conversion and logic control module includes a first operational amplifier module U2, PMOS tube K3, resistors R4 and R5, and the second pin of the first operational amplifier module U2 is connected to the level control reference module. , the third pin of the first operational amplifier module U2 is connected to the logic current limiting protection module, the resistor R4 and R5 connection point P1 respectively, and the fourth pin of the first operational amplifier module U2 is connected to the power network V2 is connected, the fifth pin of the first operational amplifier module U2 is connected to the ground network, the first pin of the first operational amplifier module U2 is connected to the gate of the PMOS tube K3; the PMOS tube The source of K3 is connected to one end of the resistor R4 and the M_BUS interface module respectively, the drain of the PMOS tube K3 is connected to the signal sampling receiving module; the other end of the resistor R4 is connected to the resistor R5 One end of the resistor R5 is connected, and the other end of the resistor R5 is connected to the ground network and the M_BUS interface module respectively.

Wherein, the M_BUS interface module includes an MBUS+ interface and an MBUS- interface.

Wherein, the source of the PMOS tube K3 is connected to the MBUS+ interface of the M_BUS interface module, and the other end of the resistor R5 is connected to the MBUS- interface of the M_BUS interface module.

Wherein, the third pin of the first operational amplifier module U2 is connected to the source of the PMOS tube K4 of the logic current limiting protection module.

Wherein, the Mbus interface control circuit also includes a communication interface. The gate of the NMOS tube K1 of the level control reference module is connected to the TXD interface of the host through the communication interface. The comparator of the signal sampling receiving module The first pin of U3 is connected to the RXD interface of the host through the communication interface.

The Mbus interface control circuit provided by the embodiment of the present invention is a circuit built with integrated components and completely through logical control between hardware circuits to realize overcurrent protection, power on and off and signal transmission control of the MBUS line, especially When the circuit completes the detection and logic control process of over-current protection, it responds quickly, can reduce losses to the greatest extent, and has a self-recovery function. Since the logic control is implemented by hardware circuits, the integration level is high, which greatly improves the performance of the MBUS circuit. Stability and reliability.

The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are for the purpose of illustrating preferred embodiments only and are not to be construed as limiting the invention. Also throughout the drawings, the same reference characters are used to designate the same components. In the attached picture:

Figure 1 is a schematic structural diagram of an Mbus interface control circuit provided by an embodiment of the present invention;

Figure 2 is a circuit schematic diagram of a level control reference module provided by an embodiment of the present invention;

Figure 3 is a schematic circuit diagram of a logic current limiting protection module provided by an embodiment of the present invention;

Figure 4 is a schematic circuit diagram of a signal sampling receiving module provided by an embodiment of the present invention;

Figure 5 is a schematic circuit diagram of a voltage conversion and logic control module provided by an embodiment of the present invention;

FIG6 is a circuit diagram of an M_BUS interface module provided in an embodiment of the present invention;

FIG. 7 is an overall circuit diagram of an Mbus interface control circuit provided by an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a thorough understanding of the disclosure, and to fully convey the scope of the disclosure to those skilled in the art.

Those skilled in the art will understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the art to which the present invention belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined.

The embodiment of the present invention provides an Mbus interface control circuit, as shown in Figure 1, including a level control reference module 11, a voltage conversion and logic control module 12, a logic current limiting protection module 13, a signal sampling receiving module 14 and an M_BUS interface. Module 15, the level control reference module 11, the logic current limiting protection module 13, the signal sampling receiving module 14 and the M_BUS interface module 15 are respectively connected to the voltage conversion and logic control module 12, wherein:

The level control reference module 11 is connected to the host and is used to generate a reference voltage according to the control signal sent by the host and send the reference voltage to the voltage conversion and logic control module 12;

The signal sampling receiving module 14 is connected to the logic current limiting protection module 13 and is used to sample the current signal of the voltage conversion and logic control module 12, generate a data signal transmitted to the host according to the sampling signal, and send the sampled signal to the host. The signal is sent to the logical current limiting protection module 13;

The logic current limiting protection module 13 is used to generate a control voltage according to the sampling signal, and send the control voltage to the voltage conversion and logic control module 12;

The voltage conversion and logic control module 12 is used to control the current signal of the M_BUS interface module 15 on and off according to the reference voltage and the control voltage, and at the same time transmit the current signal to the signal sampling receiving module;

The M_BUS interface module 15 is used to connect the subsequent MBUS slave circuit.

The Mbus interface control circuit provided by the embodiment of the present invention is a circuit built with integrated components and completely through logical control between hardware circuits to realize overcurrent protection, power on and off and signal transmission control of the MBUS line, especially When the circuit completes the detection and logic control process of over-current protection, it responds quickly, can reduce losses to the greatest extent, and has a self-recovery function. Since the logic control is implemented by hardware circuits, the integration level is high, which greatly improves the performance of the MBUS circuit. Stability and reliability.

In a specific embodiment, the level control reference module 11 includes resistors R1, R2, R3, R11, NMOS transistor K1, and PMOS transistor K2. As shown in Figure 2, the TXD interface of the host is connected to the gate of the NMOS tube K1, the source of the NMOS tube K1 is connected to the ground network, and the drain of the NMOS tube K1 is connected to one end of the resistor R1 connected, the other end of the resistor R1 is connected to the power supply network V1, the drain of the NMOS tube K1 is also connected to the gate of the PMOS tube K2, the drain of the PMOS tube K2 is connected to one end of the resistor R11 connected, the other end of the resistor R11 is connected to the power supply network V1, the source of the PMOS tube K2 is connected to the resistors R2, R3 and the voltage conversion and logic control module, and the other end of the resistor R2 is connected to the power supply network V1. Network V1 is connected and the other end of resistor R3 is connected to the ground network.

The value of V_ref1 can be represented by (1) and (2):

When TXD is high:

V_ref1＝(V1*R3)/(R2+R3) (1)

When TXD is low:

V_ref1＝(V1*R3)/(R3+R11) (2)

For example: The main function of the level control reference module is to convert the TXD control signal sent from the host into the V_ref voltage and transmit it to the voltage conversion and logic control module. Specifically, take the parameters set in Figure 7 as an example. When the TXD sending signal is low, KI does not conduct. At this time, the G of K2 is extremely high and K2 does not conduct. Through the voltage dividing effect of R2 and R3, according to the formula (1) The voltage Vref1=1V output to module 2 is obtained; when the TXD sending signal is high, KI is turned on. At this time, the G of K2 is extremely low, K2 is turned on, and the voltage dividing effect of R2 and R3 fails. The voltage Vref1 output to module 2 of formula (2) is 3.2V.

In a specific embodiment, the logic current limiting protection module 13 includes resistors R6, R7, a comparator U1 and a PMOS tube K4. As shown in FIG3, one end of the resistor R6 is connected to the power supply network V1, and the other end is connected to one end of the resistor R7 and the third pin of the comparator U1. The other end of the resistor R7 is connected to the ground network. The fourth pin of the comparator U1 is connected to the signal sampling and receiving module, and the fifth pin of the comparator U1 is connected to the power supply network V1. The second pin of the comparator U1 is connected to the ground network, the first pin of the comparator U1 is connected to the gate of the PMOS tube K4, the drain of the PMOS tube K4 is connected to the power supply network V1, and the source of the PMOS tube K4 is connected to the voltage conversion and logic control module.

Specifically, the current limited by the logic current limiting protection module 13 is adjustable, and the current limit can be expressed by formula (3):

I＝ _Vref2 *α (3)

In the formula, R8 represents its corresponding resistance value, G represents the gain of the instrumentation amplifier, and its value can be selected according to different needs. V _ref represents the input voltage of the third pin of U1, α is the current gain parameter, and its value is determined by G and R8. Determined by value, I represents the limited current value.

For example: The function of the logic current limiting protection module 13 is realized by inputting the alarm voltage signal from the signal sampling receiving module through the 4th pin of U1, and through the voltage dividing effect of R6 and R7. It can be seen from the formula (3) that Vref2= The 1.65V voltage signal is input to the 3rd pin of U1. U1 controls the on and off of K4 by comparing the voltage of the 3rd pin and the 4th pin, thereby controlling the voltage conversion and the switch of the logic control module. Specifically, taking the parameters set in Figure 7 as an example, when the voltage of the 4th pin of U1 is less than Vref2 = 1.65V, the output terminal of the 1st pin of U1 is a voltage equal to the value of V1. At this time, the PMOS tube K4 is in the cut-off area. No conduction; when the voltage of the 4th pin of U1 is greater than 1.65V (the voltage feedback signal sent by the signal sampling receiving module is larger than Vref2, indicating that the MBUS rear pole circuit has a short circuit or other faults causing overcurrent), U1 The output terminal of pin 1 is 0V. At this time, the PMOS tube K4 is in the saturation zone and is fully turned on. At this time, the S pole of K4 will be output to the voltage conversion and logic control module, causing it to stop working normally, thereby achieving current limiting. protective effect.

In a specific embodiment, the signal sampling receiving module 14 includes a sampling resistor R8, a comparator U3, a sampling amplifier U4 and resistors R9 and R10. As shown in Figure 4, one end of the sampling resistor R8 is connected to the power supply network V2 and the third pin of the sampling amplifier U4, and the other end of the sampling resistor R8 is connected to the second tube of the sampling amplifier U4. pin, the voltage conversion and logic control module are connected, the 4th pin of the sampling amplifier U4 is connected to the power network V2, the 5th pin of the sampling amplifier U4 is connected to the ground network, the sampling amplifier U4 The first pin of is connected to the fourth pin of the comparator U3 and the logic current limiting protection module 13 respectively. One end of the resistor R9 is connected to the power network V1, and the other end of the resistor R9 is connected to the resistor R10. One end of the resistor R10 is connected to the third pin of the comparator U3, the other end of the resistor R10 is connected to the ground network, the fifth pin of the comparator U3 is connected to the power supply network V1, and the comparator U3 The first pin is connected to the RXD interface of the host, and the second pin of the comparator U3 is connected to the ground network.

For example: the function implementation of the signal sampling receiving module 14 takes the parameters set in Figure 7 as an example. The voltage difference ΔV across R8 is detected through U4, amplified by a certain multiple through internal processing of U4, and output to the 1st pin of U4. The 4th pin of the logic current limiting protection module and comparator U3, R9 and R10 output to the 3rd pin of U3 through voltage division, the reference voltage Vref3 = 0.8V, when the 4th pin voltage of U3 is greater than the 3rd pin of U3 When the pin voltage is low, the first pin of U3 outputs a low level. When the voltage of the 4th pin of U3 is less than the voltage of the 3rd pin of U3, the first pin of U3 outputs a high level and transmits the data signal to The receiving end of the host completes the data receiving function.

In a specific embodiment, the voltage conversion and logic control module 12 includes a first operational amplifier module U2, a PMOS tube K3, and resistors R4 and R5. As shown in Figure 5, the second pin of the first operational amplifier module U2 is connected to the level control reference module, and the third pin of the first operational amplifier module U2 is connected to the logic current limiting protection module respectively. The module, resistors R4 and R5 are connected to the connection point P1, the 4th pin of the first operational amplifier module U2 is connected to the power network V2, the 5th pin of the first operational amplifier module U2 is connected to the ground network, The first pin of the first operational amplifier module U2 is connected to the gate of the PMOS tube K3; the source of the PMOS tube K3 is connected to one end of the resistor R4 and the M_BUS interface module, so The drain of the PMOS tube K3 is connected to the signal sampling receiving module; the other end of the resistor R4 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the ground network and the M_BUS interface module respectively.

Specifically, the voltage values of key points P1, P2, and P3 can be expressed by the following formula:

V _P3 =0 (8)

Among them, R _mos is the internal resistance of K3, and _VP1 and _VP2 change dynamically as R _mos changes.

For example: the function implemented by the voltage conversion and logic control module 12 controls the working state of K3 by comparing the input values of the second and third pins of U2 and determining the output level of the first pin, and then through R4 and The voltage dividing function of R5 has low power consumption and accurately transmits the sending data to the M_BUS interface module. Specifically, taking the parameters set in Figure 7 as an example, when the input value of the second pin of U2 Vref1 = 1V, the internal circuit of the adjustment voltage conversion and logic control module works in a negative feedback state, and K3 works in the variable resistance area. At this time, the source output of K3 can be obtained from formulas (6) and (7) that V _P2 is 12V, and the voltage at point P1 remains at 1V, that is, the voltage of the third pin of U2 is at 1V. At this time, the MBUS+ voltage output to the M_BUS interface module is 12V, the MBUS-voltage that is V _P3 is 0V; when the input value of the second pin of U2 Vref1 = 3.2V, the internal circuit of the adjustment voltage conversion and logic control module works in a negative feedback state, and K3 works in the saturation zone. At this time The source output of K3 is 24V. Through the voltage dividing effect of R4 and R5, the voltage at point P1 is 2V, that is, the voltage of the third pin of U2 is 2V. Keep K3 working in the saturation zone. At this time, it is output to the MBUS+ of the M_BUS interface module. The voltage is 24V, MBUS-voltage is 0V. In addition, once the logic current limiting protection module sends a 3.3V voltage signal to the third pin of U2, then whether Vref1 is 1V or 3.2V, the first pin of U2 is 24V at this time, K3 is not conductive, MBUS+ and MBUS - Both are 0V. The logic current limiting protection module will only send out a 3.3V voltage signal when the downstream circuit is short-circuited or other faults cause large currents, thereby protecting the downstream circuit.

In the embodiment of the present invention, the M_BUS interface module 15 includes an MBUS+ interface and an MBUS- interface. As shown in Figure 6, the M_BUS interface module mainly includes interface terminals that can be connected to the rear Mbus slave circuit, and are used for the interface of the rear Mbus slave circuit. Wherein, the source of the PMOS tube K3 is connected to the MBUS+ interface of the M_BUS interface module, and the other end of the resistor R5 is connected to the MBUS- interface of the M_BUS interface module.

Further, the third pin of the first operational amplifier module U2 is connected to the source of the PMOS tube K4 of the logic current limiting protection module.

Further, the Mbus interface control circuit also includes a communication interface. The gate of the NMOS tube K1 of the level control reference module is connected to the TXD interface of the host through the communication interface. The comparison of the signal sampling receiving module The first pin of the device U3 is connected to the RXD interface of the host through the communication interface.

The Mbus interface control circuit provided by the embodiment of the present invention will not work when the host is not sending and receiving data, and therefore will not produce static loss; when the host is sending and receiving data, due to the feedback effect of the signal sampling receiving module, The logic current limiting protection module cooperates with the voltage conversion and logic control module to realize the function of automatic current limiting protection of the circuit, and realizes the adjustable current limiting size, which can suppress and prevent damage to the rear pole circuit. When the circuit completes the detection and logic control process of over-current protection, it responds quickly, can reduce losses to the greatest extent, and has a self-recovery function. Since the logic control is implemented by hardware circuits, the stability and reliability of the MBUS circuit are greatly improved. sex.

Those skilled in the art will understand that, although some embodiments herein include certain features included in other embodiments but not others, combinations of features of different embodiments are meant to be within the scope of the invention and form Different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that it can still be used Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent substitutions are made to some of the technical features; however, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (9)

1. The Mbus interface control circuit is characterized by comprising a voltage conversion and logic control module, and a level control reference module, a logic current limiting protection module, a signal sampling receiving module and an M_BUS interface module which are respectively connected with the voltage conversion and logic control module;

the level control reference module is connected with the host computer and used for generating reference voltage according to a control signal sent by the host computer and sending the reference voltage to the voltage conversion and logic control module;

the signal sampling receiving module is connected with the logic current limiting protection module and is used for sampling the current signal of the voltage conversion and logic control module, generating a data signal transmitted to a host according to the sampling signal and transmitting the sampling signal to the logic current limiting protection module;

the logic current limiting protection module is used for generating control voltage according to the sampling signal and sending the control voltage to the voltage conversion and logic control module;

the voltage conversion and logic control module is used for controlling the on-off of a current signal of the M_BUS interface module according to the reference voltage and the control voltage, and transmitting the current signal to the signal sampling receiving module;

the M_BUS interface module is used for connecting a post-stage MBUS slave circuit.

2. The Mbus interface control circuit according to claim 1, characterized in that the level control reference module includes resistors R1, R2, R3, R11, an NMOS tube K1 and a PMOS tube K2, the TXD interface of the host is connected to the gate of the NMOS tube K1, the source of the NMOS tube K1 is connected to the ground network, the drain of the NMOS tube K1 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the power network V1, the drain of the NMOS tube K1 is further connected to the gate of the PMOS tube K2, the drain of the PMOS tube K2 is connected to one end of the resistor R11, the other end of the resistor R11 is connected to the power network V1, the source of the PMOS tube K2 is connected to both the resistors R2, R3 and the voltage conversion and logic control module, the other end of the resistor R2 is connected to the power network V1, and the other end of the resistor R3 is connected to the ground network.

3. The Mbus interface control circuit according to claim 1, characterized in that the logic current limiting protection module comprises resistors R6 and R7, a comparator U1 and a PMOS tube K4, one end of the resistor R6 is connected to a power supply network V1, the other end is connected to one end of the resistor R7, the other end is simultaneously connected to a 3 rd pin of the comparator U1, the other end of the resistor R7 is connected to a ground network, a 4 th pin of the comparator U1 is connected to a signal sampling receiving module, a 5 th pin of the comparator U1 is connected to the power supply network V1, a 2 nd pin of the comparator U1 is connected to a ground network, a 1 st pin of the comparator U1 is connected to a gate of the PMOS tube K4, a drain of the PMOS tube K4 is connected to the power supply network V1, and a source of the PMOS tube K4 is connected to a voltage conversion and logic control module.

4. The Mbus interface control circuit according to claim 1, characterized in that the signal sampling receiving module comprises a sampling resistor R8, a comparator U3, a sampling amplifier U4 and resistors R9 and R10, wherein one end of the sampling resistor R8 is connected with a power supply network V2 and a 3 rd pin of the sampling amplifier U4 respectively, the other end of the sampling resistor R8 is connected with a 2 nd pin of the sampling amplifier U4 and the voltage conversion and logic control module respectively, a 4 th pin of the sampling amplifier U4 is connected with the power supply network V2, a 5 th pin of the sampling amplifier U4 is connected with a ground network, a 1 st pin of the sampling amplifier U4 is connected with a 4 th pin of the comparator U3 and a logic current limiting protection module respectively, one end of the resistor R9 is connected with a power supply network V1, the other end of the resistor R9 is connected with one end of the resistor R10 and a 3 rd ground network of the comparator U3 respectively, the other end of the resistor R10 is connected with a 3 rd pin of the comparator U4, the 5 th pin of the sampling amplifier U4 is connected with the power supply network V2, the 1 th pin of the comparator U3 is connected with the power supply network 3 rd pin of the comparator U1 and the interface is connected with the host.

5. The Mbus interface control circuit according to any one of claims 1-4, characterized in that the voltage conversion and logic control module includes a first operational amplifier module U2, a PMOS tube K3, and resistors R4 and R5, a 2 nd pin of the first operational amplifier module U2 is connected to the level control reference module, a 3 rd pin of the first operational amplifier module U2 is connected to a connection point P1 of the logic current limiting protection module and the resistors R4 and R5, a 4 th pin of the first operational amplifier module U2 is connected to a power network V2, a 5 th pin of the first operational amplifier module U2 is connected to a ground network, and a 1 st pin of the first operational amplifier module U2 is connected to a gate of the PMOS tube K3; the source electrode of the PMOS tube K3 is respectively connected with one end of the resistor R4 and the M_BUS interface module, and the drain electrode of the PMOS tube K3 is connected with the signal sampling receiving module; the other end of the resistor R4 is connected with one end of the resistor R5, and the other end of the resistor R5 is connected with a ground network and the M_BUS interface module respectively.

6. The Mbus interface control circuit according to claim 5, characterized in that the m_bus interface module includes an mbus+ interface and an Mbus-interface.

7. The Mbus interface control circuit according to claim 6, characterized in that the source of the PMOS transistor K3 is connected to the mbus+ interface of the m_bus interface module, and the other end of the resistor R5 is connected to the Mbus-interface of the m_bus interface module.

8. The Mbus interface control circuit according to claim 3, characterized in that the voltage conversion and logic control module includes a first operational amplifier module U2, a PMOS tube K3, and resistors R4 and R5, a 2 nd pin of the first operational amplifier module U2 is connected to the level control reference module, a 3 rd pin of the first operational amplifier module U2 is connected to a connection point P1 of the logic current limiting protection module, the resistors R4 and R5, a 4 th pin of the first operational amplifier module U2 is connected to a power network V2, a 5 th pin of the first operational amplifier module U2 is connected to a ground network, and a 1 st pin of the first operational amplifier module U2 is connected to a gate of the PMOS tube K3; the source electrode of the PMOS tube K3 is respectively connected with one end of the resistor R4 and the M_BUS interface module, and the drain electrode of the PMOS tube K3 is connected with the signal sampling receiving module; the other end of the resistor R4 is connected with one end of a resistor R5, and the other end of the resistor R5 is connected with a ground network and an M_BUS interface module respectively;

and the 3 rd pin of the first operational amplifier module U2 is connected with the source electrode of the PMOS tube K4 of the logic current limiting protection module.

9. The Mbus interface control circuit according to claim 5, further comprising a communication interface through which a gate of the NMOS tube K1 of the level control reference module is connected to the TXD interface of the host, and a 1 st pin of the comparator U3 of the signal sampling reception module is connected to the RXD interface of the host.