CN111835373B - Novel SWP interface circuit - Google Patents
Novel SWP interface circuit Download PDFInfo
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- CN111835373B CN111835373B CN201911099040.5A CN201911099040A CN111835373B CN 111835373 B CN111835373 B CN 111835373B CN 201911099040 A CN201911099040 A CN 201911099040A CN 111835373 B CN111835373 B CN 111835373B
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- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 7
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 description 6
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 6
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- 238000004891 communication Methods 0.000 description 4
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- 239000000872 buffer Substances 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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Abstract
The invention provides a novel SWP interface circuit, which comprises an electrostatic protection circuit, a receiving circuit and a transmitting circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, and the receiving circuit is connected with the transmitting circuit; in the novel SWP interface circuit, the fifth NMOS transistor, the sixth NMOS transistor and the second amplifier are introduced, so that the source-drain voltages of the third NMOS transistor and the fourth NMOS transistor are the same, the mismatching of mirror currents of the third NMOS transistor and the fourth NMOS transistor is effectively reduced, the static power consumption of the novel SWP interface circuit is effectively reduced, and the novel SWP interface circuit is simple in structure, easy to integrate and stable in output voltage.
Description
Technical Field
The invention relates to the technical field of integrated circuits of SIM card technology, in particular to a novel SWP interface circuit.
Background
The SWP SIM card is a new-specification security chip, the card number and the password are stored in the SIM card, and point-to-point communication is realized with the CLF (master device) through the SWP interface on the SIM (slave device) card. As shown in fig. 1, the SWP interface is a key circuit for implementing point-to-point communication between the SWP SIM card and the CLF terminal (not connected to the front end), and its performance is directly related to the communication quality between the SIM card and the CLF terminal.
In recent years, the mobile phone is no longer a simple communication tool, and becomes a reliable mobile payment tool, and plays an irreplaceable role in the fields of shopping, transportation, banking and the like, so that the design and research of a high-quality and low-cost SWP circuit have very important significance.
Referring to fig. 2, a SWP interface circuit structure commonly used at present is shown, and the working principle thereof is as follows: the SIM SWP interface on the SWP SIM card is a slave interface, the CLF SWP interface on the CLF end is a master interface, the CLF SWP interface is transmitted as a digital pulse modulation signal S1, the high-level duration time is 0.75T and is logic '1', and the high-level duration time is 0.25T and is logic '0', wherein 'T' is 1bit period time. The SIM SWP interface sends a current modulation signal S2, which is logic '1' when the current is drawn from the CLF end by 600uA to 1000uA, and is logic '0' when the current is drawn from the CLF end by-20 uA to 0uA. When the CLF terminal transmits the S1 signal at a high level, the SWP SIM card transmits the S2 signal by means of a pull-up current or a pull-out current, i.e., data is transmitted in a full duplex mode.
SWPI is an input/output port of an SWP interface circuit of the SWP SIM card, a first diode D1 and a second diode D2 are electrostatic protection circuits of the SWP interface, an input signal of the SWP interface circuit forms a low-pass filter through a first resistor R1 and a first capacitor C1, and after being shaped by a first stage Schmitt trigger ST, the input signal is output through two stages of buffers of a first inverter INV1 and a second inverter INV 2. Meanwhile, when the SWP SIM card receives a digital modulation signal S1 in a voltage domain as a high level signal, the SWP interface circuit transmits a digital modulation signal S2 in the current domain by means of a fourth NMOS transistor NM4 of a pull-down transistor or a fifth NMOS transistor NM5 of a switch transistor, when the digital modulation signal S2 in the current domain is at a high level, the fifth NMOS transistor NM5 is turned on, the fourth NMOS transistor NM4 pull-down current is 600uA to 1000uA, when S2 is at a low level, the fifth NMOS transistor NM5 is turned off, the fourth NMOS transistor NM4 is turned on, and the pull-down current is-20 uA to 0uA. The key circuit of the SWP SIM card is a transmitting circuit, and the transmitting circuit comprises a reference current IREF, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1 and a second PMOS transistor PM2 to form a current amplifying circuit.
However, the SWP SIM card SWP interface circuit has some disadvantages:
1. in the SWP interface circuit, the reference current IREF is relatively small, usually below 1uA, so that the amplification factor of the current amplifying circuit is 600 times to 1000 times, and the current amplifier is easy to mismatch, which causes the pull-down current of the fourth NMOS transistor NM4 to be too small or too large, and does not meet the SWP protocol requirement.
2. When the digital modulation signal S2 in the current domain is at a low level, 80uA of current in the second PMOS transistor PM2 flows away from the fifth NMOS transistor NM5, which is not beneficial for the design of the low power circuit.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a novel SWP interface circuit which comprises an electrostatic protection circuit, a receiving circuit and a transmitting circuit and has the characteristics of simple structure, easiness in integration and stable output voltage.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
a novel SWP interface circuit, which comprises an electrostatic protection circuit, a receiving circuit and a transmitting circuit;
the electrostatic protection circuit comprises a first diode and a second diode; the anode of the first diode is connected with the input and output end of the SWP interface circuit, the cathode of the first diode is connected with the power supply end VDD, the cathode of the second diode is connected with the input and output end of the SWP interface circuit, and the anode of the second diode is connected with the ground end VSS;
the receiving circuit comprises a first capacitor, a first resistor, a first schmitt trigger, a first inverter and a second inverter; one end of the first resistor is connected with the input and output end of the SWP interface circuit, the other end of the first resistor and one end of the first resistor are connected with the input end of the first Schmitt trigger, the other end of the first capacitor is grounded at the ground end VSS, the output end of the first Schmitt trigger is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is the output end of the SWP interface circuit, the power end of the first Schmitt trigger, the power end of the first inverter and the power end of the second inverter are connected with the power end VDD, and the ground end of the first Schmitt trigger, the ground end of the first inverter and the ground end of the second inverter are connected with the ground end VSS;
the transmitting circuit comprises a first reference current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first amplifier, a second amplifier and a third inverter; one end of the first reference current source is connected with the power supply end VDD, the other end of the first reference current source, the gate end and the drain end of the first NMOS transistor are connected with the positive input end of the first amplifier, the negative input end of the first amplifier, the gate end and the drain end of the second NMOS transistor are connected with the drain end of the first PMOS transistor, the gate end and the drain end of the second PMOS transistor are connected with the drain end of the fifth NMOS transistor, the gate end of the sixth NMOS transistor are connected with the output end of the second amplifier, the source end of the fifth NMOS transistor, the positive input end of the second amplifier are connected with the drain end of the third NMOS transistor, the gate end of the third NMOS transistor, the output end of the first amplifier, the gate end of the fourth NMOS transistor are connected with the drain end of the seventh NMOS transistor, the drain terminal of the fourth NMOS transistor, the negative input terminal of the second amplifier is connected with the source terminal of the sixth NMOS transistor, the drain terminal of the sixth NMOS transistor is connected with the input and output terminal, the gate terminal of the seventh NMOS transistor is connected with the output terminal of the third inverter, the input terminal of the third inverter is connected with the digital modulation signal of the current domain, the source terminal and the substrate of the first NMOS transistor, the source terminal and the substrate of the seventh NMOS transistor, the source terminal and the substrate of the third NMOS transistor, the source terminal and the substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, the substrate of the sixth NMOS transistor, the ground terminal of the first amplifier, the ground terminal of the second amplifier, the ground terminal and the VSS of the third inverter are connected with the source terminal and the substrate of the first PMOS transistor, the source terminal and the substrate of the second PMOS transistor, the power source terminal of the first amplifier, the power terminal of the second amplifier and the power terminal and the VDD of the third inverter.
Due to the adoption of the structure, compared with the prior art, the invention has the following advantages:
(1) In the novel SWP interface circuit, the fifth NMOS transistor, the sixth NMOS transistor and the second amplifier are introduced, so that the source-drain voltages of the third NMOS transistor and the fourth NMOS transistor are the same, and the mismatching of mirror currents of the third NMOS transistor and the fourth NMOS transistor is effectively reduced;
(2) In the novel SWP interface circuit, the first NMOS transistor, the second NMOS transistor and the first amplifier are introduced, so that the current of the third NMOS transistor is 80 times of the reference current IREF accurately, and the mismatch is not easy;
(3) In the novel SWP interface circuit, the fifth NMOS transistor and the sixth NMOS transistor are introduced, so that the static power consumption of the novel SWP interface circuit is effectively reduced;
(4) The novel SWP interface circuit has the advantages of simple structure, easy integration and stable output voltage.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of SWP interface circuit data transmission;
fig. 2 is a SWP circuit configuration diagram of a conventional SWP SIM card;
fig. 3 is a block diagram of a novel SWP interface circuit in an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 3, a novel SWP interface circuit structure diagram in an embodiment of the present invention is shown. The novel SWP interface circuit includes an electrostatic protection circuit 101, a receiving circuit 102, and a transmitting circuit 103.
The electrostatic protection circuit 101 includes a first diode D1 and a second diode D2; the positive pole of the first diode D1 is connected with the input and output end SWPI of the SWP interface circuit, the negative pole of the first diode D1 is connected with the power supply end VDD, the negative pole of the second diode D2 is connected with the input and output end SWPI of the SWP interface circuit, and the positive pole of the second diode D2 is connected with the ground end VSS.
The receiving circuit 102 includes a first capacitor C1, a first resistor R1, a first schmitt trigger ST, a first inverter INV1, and a second inverter INV2; one end of the first resistor R1 is connected with the input and output end SWPI of the SWP interface circuit, the other end of the first resistor R1 and one end of the first resistor R1 are connected with the input end of the first schmitt trigger ST, the other end of the first capacitor C1 is grounded VSS, the output end of the first schmitt trigger ST is connected with the input end of the first inverter INV1, the output end of the first inverter INV1 is connected with the input end of the second inverter INV2, the output end of the second inverter INV2 is the output end SWPO of the SWP interface circuit, the power end of the first schmitt trigger ST, the power end of the first inverter INV1 and the power end of the second inverter INV2 are connected with the power end VDD, and the ground end of the first schmitt trigger ST, the ground end of the first inverter INV1 and the ground end of the second inverter INV2 are connected with the ground end VSS.
The transmitting circuit 103 includes a first reference current source IREF, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, a first PMOS transistor PM1, a second PMOS transistor PM2, a first amplifier AMP1, a second amplifier AMP2, and a third inverter INV3; one end of the first reference current source IREF is connected to the power supply terminal VDD, the other end of the first reference current source IREF, the gate and drain of the first NMOS transistor NM1 are connected to the positive input terminal of the first amplifier AMP1, the negative input terminal of the first amplifier AMP1, the gate and drain of the second NMOS transistor NM2 are connected to the drain terminal of the first PMOS transistor PM1, the gate and drain of the second PMOS transistor PM2 are connected to the drain terminal of the fifth NMOS transistor NM5, the gate terminal of the sixth NMOS transistor NM6 are connected to the output terminal of the second amplifier AMP2, the source terminal of the fifth NMOS transistor NM5, the positive input terminal of the second amplifier AMP2 are connected to the drain terminal of the third NMOS transistor NM3, the gate terminal of the first NMOS transistor NM1, the output terminal of the fourth NMOS transistor NM4 are connected to the drain terminal of the seventh NMOS transistor NM7, the drain terminal of the fourth NMOS transistor NM4, the negative input terminal of the second amplifier AMP2 is connected to the source terminal of the sixth NMOS transistor NM6, the drain terminal of the sixth NMOS transistor NM6 is connected to the input/output terminal SWPI, the gate terminal of the seventh NMOS transistor NM7 is connected to the output terminal of the third inverter INV3, the input terminal of the third inverter INV3 is connected to the digital modulation signal S2 of the current domain, the source terminal and the substrate of the first NMOS transistor NM1, the source terminal and the substrate of the seventh NMOS transistor NM7, the source terminal and the substrate of the third NMOS transistor NM3, the source terminal and the substrate of the fourth NMOS transistor NM4, the substrate of the fifth NMOS transistor NM5, the substrate of the sixth NMOS transistor NM6, the ground terminal of the first amplifier AMP1, the ground terminal of the second amplifier AMP2, the ground terminal of the third inverter INV3 are connected to the ground terminal VSS, the source terminal and the substrate of the second PMOS transistor PM2, the source terminal and the source terminal of the second PMOS transistor PM2, the power supply terminal of the first amplifier AMP1, the power supply terminal of the second amplifier AMP2, and the power supply terminal of the third inverter INV3 are connected to the power supply terminal VDD.
Referring to fig. 3, the novel SWP interface circuit of the present invention operates as follows: when the SWP interface circuit works, an input/output end SWPI is an SWP input/output port of an SWP SIM card, a first diode D1 and a second diode D2 provide electrostatic protection for the SWP interface circuit, and after passing through a low-pass filter formed by a first resistor R1 and a first capacitor C1, an input signal of the SWP interface circuit is shaped by a first stage Schmitt trigger ST, and then passes through two stages of buffers of a first inverter INV1 and a second inverter INV2, and then a digital signal is output; meanwhile, when the SWP interface circuit receives a high level signal of the digital modulation signal S1 in the voltage domain, the SWP interface circuit transmits the digital modulation signal S2 in the current domain by means of the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 or the seventh NMOS transistor NM7 of the switch transistor, when the digital modulation signal S2 in the current domain is in the high level, the seventh NMOS transistor NM7 is turned on, the fourth NMOS transistor NM4 and the sixth NMOS transistor NM6 pull-down current is 600uA to 1000uA, when the digital modulation signal S2 in the current domain is in the low level, the seventh NMOS transistor NM7 is turned off, the fourth NMOS transistor NM4 is turned on, and the pull-down current is-20 uA to 0uA, thereby realizing the stability of the SWP interface circuit.
From the above, the embodiment of the present invention effectively improves the stability of the SWP interface circuit through the electrostatic protection circuit 101, the receiving circuit 102, and the transmitting circuit 103.
The above embodiments are merely illustrative of the basic idea of the present invention, and the constituent circuits according to the present invention are not drawn in accordance with the number, shape, arrangement of devices, and connection of constituent circuits in actual implementation. The type, number, connection mode, device arrangement mode and device parameters of each circuit can be changed randomly when the circuit is actually implemented.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent variation, obvious change, etc. of the known technology based on the technical proposal of the invention should fall within the protection scope of the invention.
Claims (1)
1. The novel SWP interface circuit is characterized by comprising an electrostatic protection circuit, a receiving circuit and a transmitting circuit;
the electrostatic protection circuit comprises a first diode and a second diode; the anode of the first diode is connected with the input and output end of the SWP interface circuit, the cathode of the first diode is connected with the power supply end VDD, the cathode of the second diode is connected with the input and output end of the SWP interface circuit, and the anode of the second diode is connected with the ground end VSS;
the receiving circuit comprises a first capacitor, a first resistor, a first schmitt trigger, a first inverter and a second inverter; one end of the first resistor is connected with the input and output end of the SWP interface circuit, the other end of the first resistor and one end of the first capacitor are connected with the input end of the first Schmitt trigger, the other end of the first capacitor is grounded to the ground end VSS, the output end of the first Schmitt trigger is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is the output end of the SWP interface circuit, the power end of the first Schmitt trigger, the power end of the first inverter and the power end of the second inverter are connected with the power end VDD, and the ground end of the first Schmitt trigger, the ground end of the first inverter and the ground end of the second inverter are connected with the ground end VSS;
the transmitting circuit comprises a first reference current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a first amplifier, a second amplifier and a third inverter; one end of the first reference current source is connected with the power supply end VDD, the other end of the first reference current source, the gate end and the drain end of the first NMOS transistor are connected with the positive input end of the first amplifier, the negative input end of the first amplifier, the gate end and the drain end of the second NMOS transistor are connected with the drain end of the first PMOS transistor, the gate end and the drain end of the second PMOS transistor are connected with the drain end of the fifth NMOS transistor, the gate end of the sixth NMOS transistor are connected with the output end of the second amplifier, the source end of the fifth NMOS transistor, the positive input end of the second amplifier are connected with the drain end of the third NMOS transistor, the gate end of the third NMOS transistor, the output end of the first amplifier, the gate end of the fourth NMOS transistor are connected with the drain end of the seventh NMOS transistor, the drain terminal of the fourth NMOS transistor, the negative input terminal of the second amplifier is connected with the source terminal of the sixth NMOS transistor, the drain terminal of the sixth NMOS transistor is connected with the input and output terminal, the gate terminal of the seventh NMOS transistor is connected with the output terminal of the third inverter, the input terminal of the third inverter is connected with the digital modulation signal of the current domain, the source terminal and the substrate of the first NMOS transistor, the source terminal and the substrate of the seventh NMOS transistor, the source terminal and the substrate of the third NMOS transistor, the source terminal and the substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, the substrate of the sixth NMOS transistor, the ground terminal of the first amplifier, the ground terminal of the second amplifier, the ground terminal and the VSS of the third inverter are connected with the source terminal and the substrate of the first PMOS transistor, the source terminal and the substrate of the second PMOS transistor, the power source terminal of the first amplifier, the power terminal of the second amplifier and the power terminal and the VDD of the third inverter.
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| CN201911099040.5A CN111835373B (en) | 2019-11-18 | 2019-11-18 | Novel SWP interface circuit |
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| CN201911099040.5A CN111835373B (en) | 2019-11-18 | 2019-11-18 | Novel SWP interface circuit |
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| CN111835373B true CN111835373B (en) | 2023-11-14 |
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| CN112118004B (en) * | 2020-11-19 | 2021-04-09 | 四川科道芯国智能技术股份有限公司 | SWP interface circuit and terminal |
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| CN111835373A (en) | 2020-10-27 |
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