CN111835334B

CN111835334B - Automatic calibration SWP slave interface circuit

Info

Publication number: CN111835334B
Application number: CN201911323706.0A
Authority: CN
Inventors: 孙志亮; 霍俊杰
Original assignee: Ziguang Tongxin Microelectronics Co Ltd
Current assignee: Ziguang Tongxin Microelectronics Co Ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2023-07-14
Anticipated expiration: 2039-12-20
Also published as: CN111835334A

Abstract

The invention provides an automatic calibration SWP slave interface circuit. The SWP slave interface circuit comprises an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, the receiving circuit is connected with the transmitting circuit, and the transmitting circuit is connected with the reference current generating circuit. The automatic calibration SWP slave interface circuit of the invention introduces the first digital control circuit and the reference current source generating circuit, can automatically calibrate the load modulation degree when the SWP slave interface transmits the voltage signal, avoids the load debugging of each chip, and reduces the production period and the cost; the automatic calibration SWP slave interface circuit is simple in structure and easy to integrate.

Description

Automatic calibration SWP slave interface circuit

Technical Field

The invention relates to the technical field of integrated circuits in high-capacity SIM card interface technology, in particular to an automatic SWP slave interface circuit.

Background

In recent years, mobile phones have not been simple communication devices, and have become portable entertainment and payment devices, where mobile payment plays an irreplaceable role in shopping, medical, communication, banking, and the like. The mobile payment has a plurality of solutions, wherein the SIM SWP (Single Wire Protocol) interface is connected with the NFC chip to realize point-to-point communication, which is a set of feasible solutions, as shown in fig. 1, and is a data transmission block diagram of the existing SWP interface circuit. The SWP interface circuit is configured to implement full duplex communication on a single line, i.e., a first digital modulation signal S1 in a voltage domain and a second digital modulation signal S2 in a current domain. Therefore, the design and research of the SWP interface circuit with high performance and low cost has very important significance.

Referring to fig. 2 and fig. 1, a SWP interface circuit structure is commonly used, and the working principle is as follows: the SWP interface of the SWP SIM card is used as a slave interface, the SWP interface on the NFC chip is used as a master interface, and the working principle is as follows: the SWP main interface transmits a voltage signal S1, adopts a level width modulation mode, and has a logic '1' as a high level in a 3/4 period and a logic '0' as a high level in a 1/4 period. The SWP transmits a current signal S2 from the interface, and adopts a load modulation mode; logic '1' when the voltage signal S1 is at a high level, the S1 modulation load is 600 uA-1 mA; when the voltage signal S1 is at a high level, the logic '0' is that the S1 modulation load is-20 uA-0 uA; the voltage signal S1 and the current signal S2 are superimposed on one single line to realize full duplex communication. SWPI is an input/output port of the SWP slave interface, the first diode D1 and the second diode D2 are electrostatic protection circuits of the SWP slave interface, the voltage signal S1 is firstly subjected to low-pass filter composed of a resistor R1 and a capacitor C1, and then is subjected to shaping by a Schmitt trigger ST, and is output to a digital circuit for processing after being subjected to a first inverter INV1 and a second inverter INV2 of a two-stage buffer. Meanwhile, when the received voltage signal S1 is a high level signal, SWP transmits a current signal S2 from the interface: when the fifth NMOS transistor NM5 is turned on, the pull-down current of the fourth NMOS transistor NM4 is 600 uA-1000 uA, and logic '1' is transmitted; when the fifth NMOS transistor NM5 is turned off, the fourth NMOS transistor NM4 is turned on, the pull-down current is between-20 uA and 0uA, and a logic "0" is transmitted.

However, the SWP slave interface circuit has some disadvantages:

1. in general, the reference current IREF is relatively small, usually less than 1uA, which makes the current amplification circuit amplify a factor between 600 to 1000 times, but the amplification factor of the current amplification circuit is difficult to control accurately, so that the current signal S2 does not meet the SWP protocol requirement.

2. In order to make the current signal S2 meet the SWP protocol requirements, load debugging is usually performed on each SWP SIM chip, which is time-consuming and labor-consuming and increases production cost.

Disclosure of Invention

In view of the above-mentioned shortcomings in the prior art, an object of the present invention is to provide an automatic calibration SWP slave interface circuit, which includes an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, and since a first digital control circuit and a reference current source generating circuit are introduced, the load modulation degree when the SWP slave interface circuit transmits a digital modulation signal is automatically calibrated; meanwhile, two resistors are newly introduced, so that load debugging of each chip is avoided, and the calibrated load modulation degree is more accurate.

In order to achieve the technical purpose, the invention adopts the following technical scheme:

the automatic calibration SWP slave interface circuit is characterized by comprising an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, the receiving circuit is connected with the transmitting circuit, the transmitting circuit is connected with the reference current generating circuit, the electrostatic protection circuit comprises a first diode and a second diode, the positive electrode of the second diode is connected with the input and output end of the electrostatic protection circuit, the negative electrode of the second diode is connected with a power supply end VDD, the negative electrode of the first diode is connected with the input and output end of the electrostatic protection circuit, and the positive electrode of the first diode is connected with a ground end VSS;

the receiving circuit comprises a first capacitor, a first resistor, a first Schmitt trigger, a first inverter and a second inverter, wherein one end of the first resistor is connected with the input and output end of the static protection circuit, the other end of the first resistor and one end of the first capacitor are connected with the input end of the first Schmitt trigger, the other end of the first capacitor is grounded to the ground end VSS, the output end of the first Schmitt trigger is connected with the input end of the first inverter, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter serves as the output end of the receiving circuit, the power end of the first Schmitt trigger, the power end of the first inverter and the power end of the second inverter are connected with the power end VDD, and the electric ground end of the first Schmitt trigger, the ground end of the first inverter and the ground end of the second inverter are connected with the ground end VSS;

the transmitting circuit comprises a first reference current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second resistor, a third resistor, a first comparator, a third inverter, a fourth inverter, a fifth inverter and a first digital control circuit, wherein the gate end and the drain end of the first NMOS transistor, the gate end of the second NMOS transistor and the drain end of the third NMOS transistor are connected and serve as input ends, the drain end of the second NMOS transistor is connected with the input and output ends of the electrostatic protection circuit, the source end of the second NMOS transistor, the drain end of the fourth NMOS transistor and the drain end of the fifth NMOS transistor are connected with the source end of the first PMOS transistor, the source end and the substrate of the third NMOS transistor, the substrate of the second NMOS transistor, the source end and the substrate of the first NMOS transistor, the source end and the substrate of the fourth NMOS transistor, the substrate of the fifth NMOS transistor, one end of the second resistor, one end of the third resistor, the ground end of the first comparator, the ground end of the first digital control circuit, the ground end of the third inverter, the ground end of the fourth inverter, the ground end of the fifth inverter and the ground end VSS are connected, the gate end of the third NMOS transistor is connected with the output end of the third inverter, the input end of the third inverter is connected with the digital modulation signal, the gate end of the fourth NMOS transistor is connected with the output end of the fourth inverter, the gate end of the fifth NMOS transistor, the input end of the fifth inverter is connected with the control signal end, the output end of the fifth inverter is connected with the gate end of the first PMOS transistor, the source end of the fifth NMOS transistor, the output end of the first PMOS transistor, the output end of the second inverter is connected with the positive input end of the second resistor, the other end of the third resistor and the output end of the first reference current source are connected with the negative input end of the first comparator, the output end of the first comparator is connected with the input end of the first digital control circuit, the output end of the first digital control circuit, the substrate of the first PMOS transistor, the power end of the first comparator, the power end of the first digital control circuit, the power end of the third inverter, the power end of the fourth inverter and the power end of the fifth inverter are connected with the power end VDD;

the reference current generating circuit comprises a second reference current source, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a drain terminal of the second PMOS transistor being connected with an input terminal of the transmitting circuit, a gate terminal of the second PMOS transistor, a gate terminal and a drain terminal of the third PMOS transistor, a source terminal and a substrate of the fourth PMOS transistor, a source terminal and a substrate of the fifth PMOS transistor, a source terminal and a substrate of the sixth PMOS transistor being connected with a drain terminal of the tenth NMOS transistor, a source terminal and a substrate of the second PMOS transistor, a source terminal and a substrate of the third PMOS transistor being connected with a power source terminal VDD, the gate end of the fourth PMOS transistor, the gate end of the fifth PMOS transistor, the gate end of the sixth PMOS transistor, the gate end of the seventh PMOS transistor are respectively connected with the first output end, the second output end, the third output end and the fourth output end of the emission circuit, the drain end of the fourth PMOS transistor, the drain end of the fifth PMOS transistor, the drain end of the sixth PMOS transistor and the drain end of the seventh PMOS transistor are respectively connected with the drain end of the sixth NMOS transistor, the drain end of the seventh NMOS transistor, the drain end of the eighth NMOS transistor and the drain end of the ninth NMOS transistor, the gate end of the sixth NMOS transistor, the gate end of the seventh NMOS transistor, the gate end of the eighth NMOS transistor, the gate end of the ninth NMOS transistor, the gate end of the tenth NMOS transistor, the gate end and the drain end of the eleventh NMOS transistor are disconnected with the output end of the second reference current source, the source end and the substrate of the sixth NMOS transistor, the source end and the substrate of the seventh NMOS transistor, the source end and the substrate of the eighth NMOS transistor and the substrate are disconnected, the source terminal and the substrate of the ninth NMOS transistor, the source terminal and the substrate of the tenth NMOS transistor, and the source terminal and the substrate of the eleventh NMOS transistor are connected to the ground terminal VSS.

The self-calibration SWP slave interface circuit of the invention adopts the structures of the static protection circuit, the receiving circuit, the transmitting circuit and the reference current generating circuit, and has the following beneficial effects:

(1) The automatic calibration SWP slave interface circuit of the invention introduces the first digital control circuit and the reference current source generating circuit, can automatically calibrate the load modulation degree when the SWP slave interface transmits the voltage signal, avoids the load debugging of each chip, and reduces the production period and the cost;

(2) The automatic calibration SWP circuit of the invention introduces the second resistor and the third resistor, and the resistors are easier to match compared with the MOS transistor, so that the load modulation degree after calibration is more accurate;

(3) The automatic calibration SWP slave interface circuit is simple in structure and easy to integrate;

drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

Fig. 1 is a block diagram of a conventional SWP interface circuit data transmission.

Fig. 2 is a diagram showing the configuration of SWP slave interface circuits of a conventional SWP SIM card.

FIG. 3 is a block diagram of an auto-calibrated SWP slave interface circuit embodying the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Referring to fig. 3, in the embodiment of the present invention, the self-calibration SWP slave interface circuit includes an electrostatic protection circuit 101, a receiving circuit 102, a transmitting circuit 103, and a reference current generating circuit 104, where the electrostatic protection circuit 101 is connected to the receiving circuit 102, the receiving circuit 102 is connected to the transmitting circuit 103, and the transmitting circuit 103 is connected to the reference current generating circuit 104.

Referring to fig. 3, in the embodiment of the invention, the electrostatic protection circuit 101 includes a first diode D1 and a second diode D2, wherein an anode of the second diode D2 is connected to an input/output terminal SWPI of the electrostatic protection circuit, a cathode of the second diode D2 is connected to a power supply terminal VDD, a cathode of the first diode D1 is connected to the input/output terminal SWPI of the electrostatic protection circuit, and an anode of the first diode D1 is connected to a ground terminal VSS;

referring to fig. 3, in the embodiment of the present invention, the receiving circuit 102 includes a first capacitor C1, a first resistor R1, a first schmitt trigger ST, a first inverter INV1, and a second inverter INV2, one end of the first resistor R1 is connected to the input/output SWPI of the electrostatic protection circuit, the other end of the first resistor R1, one end of the first capacitor C1 is connected to the input of the first schmitt trigger ST, the other end of the first capacitor C1 is connected to the ground VSS, the output end of the first schmitt trigger ST is connected to the input of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is used as the output SWPO of the receiving circuit, the power end of the first schmitt trigger ST, the power end of the first inverter INV1, the power end of the second inverter INV2 is connected to the power end VDD, the output end of the first inverter INV1 is connected to the ground.

Referring to fig. 3, in the embodiment of the present invention, the transmitting circuit 103 includes a first reference current source IREF1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a first PMOS transistor PM1, a second resistor R2, a third resistor R3, a first comparator COM, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, and a first digital control circuit Logic, wherein the gate terminal and the drain terminal of the first NMOS transistor NM1, the gate terminal of the second NMOS transistor NM2 are connected to the drain terminal of the third NMOS transistor NM3 and serve as the input terminal VB, the drain terminal of the second NMOS transistor NM2 is connected to the input/output terminal SWPI of the electrostatic protection circuit, the source terminal of the second NMOS transistor NM2, the drain terminal of the fourth NMOS transistor NM4, the drain terminal of the fifth NMOS transistor 5 is connected to the source terminal of the first PMOS transistor NM1, the source end and the substrate of the third NMOS transistor NM3, the substrate of the second NMOS transistor NM2, the source end and the substrate of the first NMOS transistor NM1, the source end and the substrate of the fourth NMOS transistor NM4, the substrate of the fifth NMOS transistor NM5, one end of the second resistor R2, one end of the third resistor R3, the ground end of the first comparator COM, the ground end of the first digital control circuit Logic, the ground end of the third inverter INV3, the ground end of the fourth inverter INV4, the ground end of the fifth inverter INV5 are connected with the ground end VSS, the gate end of the third NMOS transistor NM3 is connected with the output end of the third inverter INV3, the input end of the third inverter INV3 is connected with the digital modulation signal S2, the gate end of the fourth NMOS transistor NM4 is connected with the output end of the fourth inverter INV4, the input end of the fourth inverter INV4, the gate end of the fifth NMOS transistor NM5 is connected with the input end of the TRIEN 5, the output end of the fifth inverter INV5 is connected to the gate end of the first PMOS transistor PM1, the source end of the fifth NMOS transistor NM5, the drain end of the first PMOS transistor PM1, the other end of the second resistor R2 is connected to the positive input end of the first comparator COM, the other end of the third resistor R3, the output end of the first reference current source IREF1 is connected to the negative input end of the first comparator COM, the output end of the first comparator COM is connected to the input end of the first digital control circuit Logic, and the output end of the first digital control circuit Logic is swp_trim <3:0>, the substrate of the first PMOS transistor PM1, the power supply terminal of the first comparator COM, the power supply terminal of the first digital control circuit Logic, the power supply terminal of the third inverter INV3, the power supply terminal of the fourth inverter INV4, and the power supply terminal of the fifth inverter INV5 are connected to the power supply terminal VDD.

Referring to fig. 3, in the embodiment of the present invention, the reference current generating circuit 104 includes a second reference current source IREF2, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a drain terminal of the second PMOS transistor PM2 is connected to the input terminal VB of the transmitting circuit, a gate terminal and a drain terminal of the second PMOS transistor PM2, a gate terminal and a substrate of the third PMOS transistor PM3, a source terminal and a substrate of the fourth PMOS transistor PM4, a source terminal and a substrate of the fifth PMOS transistor PM5, a source terminal and a substrate of the sixth PMOS transistor PM6, a source terminal and a substrate of the seventh PMOS transistor PM7 are connected to a drain terminal of the tenth NMOS transistor NM10, the source and substrate of the second PMOS transistor PM2, the source and substrate of the third PMOS transistor PM3 are connected to the power supply terminal VDD, the gate terminal of the fourth PMOS transistor PM4, the gate terminal of the fifth PMOS transistor PM5, the gate terminal of the sixth PMOS transistor PM6, the gate terminal of the seventh PMOS transistor PM7 are connected to the first output terminal swp_trim <1>, the second output terminal swp_trim <2>, the third output terminal swp_trim <3>, the fourth output terminal swp_trim <4>, the drain terminal of the fourth PMOS transistor PM4, the drain terminal of the fifth PMOS transistor PM5 NM5, the drain terminal of the sixth PMOS transistor PM6, the drain terminal of the seventh PMOS transistor PM7 are connected to the drain terminal of the sixth NMOS transistor NM6, the drain terminal of the seventh NMOS transistor NM7, the drain terminal of the eighth NMOS transistor NM8, the drain terminal of the ninth NMOS transistor NM9, the drain terminal of the sixth NMOS transistor NM6, the drain terminal of the seventh NMOS transistor NM7, the gate terminal of the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the drain terminal of the seventh NMOS transistor NM6, the gate terminal NM7, the NMOS transistor NM8, respectively The gate terminal, gate terminal and drain terminal of the ninth NMOS transistor NM9, tenth NMOS transistor NM10, gate terminal and drain terminal of the eleventh NMOS transistor NM11 are connected to the output terminal of the second reference current source IREF2, the source terminal and substrate of the sixth NMOS transistor NM6, the source terminal and substrate of the seventh NMOS transistor NM7, the source terminal and substrate of the eighth NMOS transistor NM8, the source terminal and substrate of the ninth NMOS transistor NM9, the source terminal and substrate of the tenth NMOS transistor NM10, and the source terminal and substrate of the eleventh NMOS transistor NM11 are connected to the ground terminal VSS.

Referring to fig. 3, an auto-calibration SWP slave interface circuit of the present invention operates as follows:

first, when the control signal terminal trim_en is at a high level:

as shown in connection with fig. 1 and 3, SWP enters an auto-calibration mode from the interface circuit, and swp_trim <3 at the output of the Logic control of the first digital control circuit: the binary value of 0> is configured as 1000b by default, if the influence of temperature and process deviation on the current amplifier and the second reference current source IREF2 and the current mirror image failure are ignored, the load modulation degree when the SWP transmits logic 1 from the interface is 840uA, but in practice, the temperature, the process deviation and the current mirror image failure have influence on the current amplification factor and the deviation of the second reference current source IREF2, so that the load modulation degree when the SWP transmits logic 1 from the interface is not in the interval of 600 uA-1 mA, and the requirement of SWP protocol is exceeded.

Referring to fig. 1 and 3, in order to solve the above problem, the SWP SIM card firstly enables the control signal terminal trim_en to be at a high level every time of power-up, and the SWP enters an automatic calibration mode from the interface circuit, if the output of the first comparator COM is high, the first digital control circuit Logic reduces the output terminal swp_trim <3:0> until the first comparator COM output is low and serves as the optimal amplification factor of the power amplifier; if the first comparator COM output is low, the first digital control circuit Logic increases the output swp_trim <3:0> until the first comparator COM output is high and acts as the optimal amplification of the power amplifier. First-stage current amplification factor of current amplifier: according to the current mirror ratio NM 11:nm 10:nm 9:nm 8:nm 7:nm6=2:1:2:4:8:16, the output swp_trim <3:0> is greater than or equal to 0011b, the amplification factor is 4 uA-15.5 uA, step=0.5 uA, and the load modulation degree interval when SWP transmits logic 1 from the interface circuit is: 360-1240ua, step=40ua, and the load modulation degree interval can cover the changes of temperature, artwork difference and current mirror mismatch to the load modulation degree.

Second, when the control signal terminal trim_en is at low level:

referring to fig. 1, SWP enters a normal working mode from an interface circuit, SWPI is an input/output port of an SWP slave interface, a first diode D1 and a second diode D2 are electrostatic protection of the SWP interface, the SWP master interface circuit transmits voltage signals S1 to SWP from an input end SWPI of the interface circuit, the voltage signals S1 first pass through a first resistor R1 and a first capacitor C1 low-pass filter, and then pass through a first schmitt trigger ST for shaping, and then pass through a two-stage buffer, a first inverter INV1 and a second inverter INV2 for increasing signal driving capability, and then output to a digital circuit for processing. As shown in conjunction with fig. 1 and 3, when the SWP slave interface circuit receives the voltage signal S1 as a high level signal, the SWP slave interface circuit transmits the current signal S2 by pulling down the second NMOS transistor NM2 and the third NMOS transistor NM 3: when the third NMOS transistor NM3 is turned on, the pull-down current of the second NMOS transistor NM2 is 600 uA-1000 uA, and logic '1' is transmitted; when the third NMOS transistor NM3 is turned off, the second NMOS transistor NM2 is turned on, the pull-down current is between-20 uA and 0uA, and logic '0' is transmitted.

As can be seen from the above, in the embodiment of the present invention, the stability of SWP from the interface circuit is effectively improved and the production cost is reduced through the electrostatic protection circuit 101, the receiving circuit 102, the transmitting circuit 103 and the reference current generating circuit 104.

The above embodiments are merely illustrative of the basic idea of the present invention, and the constituent circuits according to the present invention are not drawn in accordance with the number, shape, arrangement of devices, and connection of constituent circuits in actual implementation. The type, number, connection mode, device arrangement mode and device parameters of each circuit can be changed randomly when the circuit is actually implemented.

The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent variation, obvious change, etc. of the known technology based on the technical proposal of the invention should fall within the protection scope of the invention.

Claims

1. An automatic calibration SWP slave interface circuit is characterized in that the SWP slave interface circuit comprises an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generation circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, the receiving circuit is connected with the transmitting circuit, the transmitting circuit is connected with the reference current generation circuit,

the electrostatic protection circuit comprises a first diode and a second diode, wherein the positive electrode of the second diode is connected with the input and output end of the electrostatic protection circuit, the negative electrode of the second diode is connected with the power supply end VDD, the negative electrode of the first diode is connected with the input and output end of the electrostatic protection circuit, and the positive electrode of the first diode is connected with the ground end VSS;