CN111835334A

CN111835334A - Automatic calibration SWP slave interface circuit

Info

Publication number: CN111835334A
Application number: CN201911323706.0A
Authority: CN
Inventors: 孙志亮; 霍俊杰
Original assignee: Beijing Unigroup Tsingteng Microsystems Co Ltd
Current assignee: Ziguang Tongxin Microelectronics Co Ltd
Priority date: 2019-12-20
Filing date: 2019-12-20
Publication date: 2020-10-27
Anticipated expiration: 2039-12-20
Also published as: CN111835334B

Abstract

The invention provides an automatic calibration SWP slave interface circuit. The SWP slave interface circuit comprises an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, the receiving circuit is connected with the transmitting circuit, and the transmitting circuit is connected with the reference current generating circuit. The automatic calibration SWP slave interface circuit of the invention introduces the first digital control circuit and the reference current source generating circuit, can automatically calibrate the load modulation degree when the SWP slave interface transmits the voltage signal, avoids the load debugging of each chip, and reduces the production period and the cost; the automatic calibration SWP slave interface circuit has a simple structure and is easy to integrate.

Description

Automatic calibration SWP slave interface circuit

Technical Field

The invention relates to the technical field of integrated circuits in the technology of high-capacity SIM card interfaces, in particular to an automatic calibration SWP slave interface circuit.

Background

In recent years, a mobile phone is no longer a simple communication device, and becomes a portable entertainment and payment device, wherein mobile payment plays an irreplaceable role in the fields of shopping, medical treatment, communication, banking and the like. Mobile payment has many solutions, wherein a SIM SWP (Single Wire Protocol) interface is connected to an NFC chip to implement peer-to-peer communication, which is a set of feasible solutions, as shown in fig. 1, and is a data transmission block diagram of an existing SWP interface circuit. The SWP interface circuit realizes full duplex communication on one single wire, namely a first digital modulation signal S1 in a voltage domain and a second digital modulation signal S2 in a current domain. Therefore, the design and research of high-performance and low-cost SWP interface circuits have very important significance.

Referring to fig. 2 and fig. 1, a common SWP interface circuit structure is shown, and the working principle thereof is as follows: the SWP interface of the SWP SIM card is used as a slave interface, the SWP interface on the NFC chip is used as a master interface, and the working principle is as follows: the SWP host interface transmits a voltage signal S1, and adopts a level width modulation scheme, where a logic "1" is at a high level during a 3/4 period, and a logic "0" is at a high level during a 1/4 period. The SWP transmits a current signal S2 from the interface and adopts a load modulation mode; when the voltage signal S1 is at high level, the modulation load of the S1 is 600 uA-1 mA, and the logic '1' is set; when the voltage signal S1 is at high level, the logic '0' modulates the load to-20 uA-0 uA by S1; the voltage signal S1 and the current signal S2 are superimposed on a single wire to achieve full duplex communication. The SWPI is an input/output port of the SWP slave interface, the first diode D1 and the second diode D2 are an electrostatic protection circuit of the SWP slave interface, and the voltage signal S1 firstly passes through a low-pass filter consisting of a resistor R1 and a capacitor C1, then is shaped by a Schmitt trigger ST, and then is output to a digital circuit for processing after passing through a first inverter INV1 and a second inverter INV2 of a two-stage buffer. Meanwhile, when the received voltage signal S1 is a high level signal, the SWP transmits a current signal S2 from the interface: when the fifth NMOS transistor NM5 is turned on, the pull-down current of the fourth NMOS transistor NM4 is 600uA to 1000uA, and logic "1" is transmitted; when the fifth NMOS transistor NM5 is turned off, the fourth NMOS transistor NM4 is turned on, and the pull-down current is at-20 uA to 0uA, transmitting a logic "0".

However, the SWP slave interface circuit has some disadvantages:

1. in general, the reference current IREF is relatively small, usually below 1uA, which makes the amplification factor of the current amplifying circuit between 600 times and 1000 times, but the amplification factor of the current amplifying circuit is difficult to control accurately, so that the current signal S2 does not meet the requirements of the SWP protocol.

2. In order to make the current signal S2 satisfy the SWP protocol requirements, load debugging is usually performed on each SWP SIM chip, which is time-consuming and labor-consuming, and increases the production cost.

Disclosure of Invention

In view of the above-mentioned deficiencies in the prior art, the present invention provides an automatic calibration SWP slave interface circuit, which comprises an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, wherein a first digital control circuit and a reference current generating circuit are introduced to automatically calibrate a load modulation degree when the SWP slave interface circuit transmits a digital modulation signal; meanwhile, two resistors are newly introduced, so that the load debugging of each chip is avoided, and the calibrated load modulation degree is more accurate.

In order to achieve the technical purpose, the technical scheme adopted by the invention is as follows:

an automatic calibration SWP slave interface circuit is characterized in that the SWP slave interface circuit comprises an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, wherein the electrostatic protection circuit is connected with the receiving circuit, the receiving circuit is connected with the transmitting circuit, the transmitting circuit is connected with the reference current generating circuit, the electrostatic protection circuit comprises a first diode and a second diode, the anode of the second diode is connected with the input and output end of the electrostatic protection circuit, the cathode of the second diode is connected with a power supply end VDD, the cathode of the first diode is connected with the input and output end of the electrostatic protection circuit, and the anode of the first diode is connected with a ground end VSS;

the receiving circuit comprises a first capacitor, a first resistor, a first Schmitt trigger, a first reverser and a second reverser, wherein one end of the first resistor is connected with the input end and the output end of the electrostatic protection circuit, the other end of the first resistor and one end of the first capacitor are connected with the input end of the first Schmitt trigger, the other end of the first capacitor is grounded to a ground terminal VSS, the output end of the first Schmitt trigger is connected with the input end of the first reverser, the output end of the first reverser is connected with the input end of the second reverser, the output end of the second reverser is used as the output end of the receiving circuit, and the power end of the first Schmitt trigger is connected with the power end of the second reverser, the power supply end of the first reverser and the power supply end of the second reverser are connected with a power supply end VDD, and the electric ground end of the first Schmitt trigger, the ground end of the first reverser and the ground end of the second reverser are connected with a ground end VSS;

the emission circuit comprises a first reference current source, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, a second resistor, a third resistor, a first comparator, a third inverter, a fourth inverter, a fifth inverter and a first digital control circuit, wherein a grid end and a drain end of the first NMOS transistor and a grid end of the second NMOS transistor are connected with a drain end of the third NMOS transistor and serve as input ends, a drain end of the second NMOS transistor is connected with an input end and an output end of the electrostatic protection circuit, a source end of the second NMOS transistor, a drain end of the fourth NMOS transistor and a drain end of the fifth NMOS transistor are connected with a source end of the first PMOS transistor, a source end and a substrate of the third NMOS transistor, a substrate of the second NMOS transistor, a source end and a substrate of the first NMOS transistor, a source end and a substrate of the fourth NMOS transistor, a first reference current source end and a drain end, A substrate of a fifth NMOS transistor, one end of a second resistor, one end of a third resistor, a ground end of a first comparator, a ground end of a first digital control circuit, a ground end of a third inverter, a ground end of a fourth inverter, and a ground end of a fifth inverter are connected with a ground VSS, a gate end of the third NMOS transistor is connected with an output end of the third inverter, an input end of the third inverter is connected with a digital modulation signal, a gate end of the fourth NMOS transistor is connected with an output end of the fourth inverter, an input end of the fourth inverter, a gate end of a fifth NMOS transistor, and an input end of the fifth inverter are connected with a control signal end, an output end of the fifth inverter is connected with a gate end of a first PMOS transistor, a source end of the fifth NMOS transistor, a drain end of the first PMOS transistor, and the other end of the second resistor are connected with a positive input end of the first comparator, the other end of the third resistor, a ground end of the first comparator, a ground end of the first digital control, The output end of the first reference current source is connected with the negative input end of the first comparator, the output end of the first comparator is connected with the input end of the first digital control circuit, and the output end of the first digital control circuit, the substrate of the first PMOS transistor, the power supply end of the first comparator, the power supply end of the first digital control circuit, the power supply end of the third inverter, the power supply end of the fourth inverter and the power supply end of the fifth inverter are connected with the power supply end VDD;

the reference current generating circuit comprises a second reference current source, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor and a seventh PMOS transistor, wherein the drain terminal of the second PMOS transistor is connected with the input terminal of the transmitting circuit, the gate terminal of the second PMOS transistor, the gate terminal and the drain terminal of the third PMOS transistor, the source terminal and the substrate of the fourth PMOS transistor, the source terminal and the substrate of the fifth PMOS transistor, the source terminal and the substrate of the sixth PMOS transistor, the source terminal and the substrate of the seventh PMOS transistor are connected with the drain terminal of the tenth NMOS transistor, the source terminal and the substrate of the second PMOS transistor, the source terminal and the substrate of the third PMOS transistor are connected with a VDD power supply terminal, the gate terminal of the fourth PMOS transistor, a drain terminal and the drain terminal of the fifth PMOS transistor are connected with, A gate terminal of the fifth PMOS transistor, a gate terminal of the sixth PMOS transistor, a gate terminal of the seventh PMOS transistor are respectively connected with the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the transmitting circuit, a drain terminal of the fourth PMOS transistor, a drain terminal of the fifth PMOS transistor, a drain terminal of the sixth PMOS transistor, a drain terminal of the seventh PMOS transistor are respectively connected with a drain terminal of the sixth NMOS transistor, a drain terminal of the seventh NMOS transistor, a drain terminal of the eighth NMOS transistor, a drain terminal of the ninth NMOS transistor, a gate terminal of the sixth NMOS transistor, a gate terminal of the seventh NMOS transistor, a gate terminal of the eighth NMOS transistor, a gate terminal of the ninth NMOS transistor, a gate terminal of the tenth NMOS transistor, a gate terminal and a drain terminal of the eleventh NMOS transistor are connected with an output terminal of the second reference current source, a substrate and a gate terminal of the sixth NMOS transistor, a substrate and a substrate of the seventh NMOS transistor, an eighth NMOS transistor, a substrate and a substrate of the eighth NMOS transistor, a drain terminal and a drain terminal of the sixth, The source end and the substrate of the ninth NMOS transistor, the source end and the substrate of the tenth NMOS transistor, and the source end and the substrate of the eleventh NMOS transistor are connected with the ground terminal VSS.

The self-calibration SWP slave interface circuit adopts the structures of the electrostatic protection circuit, the receiving circuit, the transmitting circuit and the reference current generating circuit, and has the following beneficial effects:

(1) the automatic calibration SWP slave interface circuit of the invention introduces the first digital control circuit and the reference current source generating circuit, can automatically calibrate the load modulation degree when the SWP slave interface transmits the voltage signal, avoids the load debugging of each chip, and reduces the production period and the cost;

(2) the automatic calibration SWP circuit of the invention introduces the second resistor and the third resistor, and the resistors are easier to match compared with MOS transistors, so that the load modulation degree after calibration is more accurate;

(3) the automatic calibration SWP slave interface circuit has a simple structure and is easy to integrate;

drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a block diagram of data transmission of a conventional SWP interface circuit.

Fig. 2 is a structure diagram of an SWP slave interface circuit of a conventional SWP SIM card.

Fig. 3 is a block diagram of an auto-calibrating SWP slave interface circuit embodying the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Referring to fig. 3, in the embodiment of the invention, the slave interface circuit for automatic SWP calibration includes an esd protection circuit 101, a receiving circuit 102, a transmitting circuit 103, and a reference current generating circuit 104, wherein the esd protection circuit 101 is connected to the receiving circuit 102, the receiving circuit 102 is connected to the transmitting circuit 103, and the transmitting circuit 103 is connected to the reference current generating circuit 104.

Referring to fig. 3, in the embodiment of the invention, the esd protection circuit 101 includes a first diode D1 and a second diode D2, the anode of the second diode D2 is connected to the input/output terminal SWPI of the esd protection circuit, the cathode of the second diode D2 is connected to the power terminal VDD, the cathode of the first diode D1 is connected to the input/output terminal SWPI of the esd protection circuit, and the anode of the first diode D1 is connected to the ground terminal VSS;

referring to fig. 3, in the embodiment of the invention, the receiving circuit 102 includes a first capacitor C1, a first resistor R1, a first schmitt trigger ST, a first inverter INV1 and a second inverter INV2, one end of the first resistor R1 is connected to the input/output end SWPI of the electrostatic protection circuit, the other end of the first resistor R1 and one end of the first capacitor C1 are connected to the input end of the first schmitt trigger ST, the other end of the first capacitor C1 is connected to the ground terminal VSS, the output end of the first schmitt trigger ST is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, the output end of the second inverter INV2 is used as the output end SWPO of the receiving circuit, the power end of the first schmitt trigger ST, the power end of the first inverter INV1, the second inverter 2 are connected to the power end VDD, and the ground end of the first schmitt trigger ST is connected to the ground terminal VDD, The ground of the first inverter INV1 and the ground of the second inverter INV2 are connected to the ground VSS.

Referring to fig. 3, in the embodiment of the present invention, the emission circuit 103 includes a first reference current source IREF1, a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a fifth NMOS transistor NM5, a first PMOS transistor PM1, a second resistor R2, a third resistor R3, a first comparator COM, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a first digital control circuit Logic control, wherein a gate terminal and a drain terminal of the first NMOS transistor NM1, a gate terminal of the second NMOS transistor NM2 are connected to a drain terminal of the third NMOS transistor NM3 and serve as an input terminal VB, a drain terminal of the second NMOS transistor NM2 is connected to an input output terminal SWPI of the electrostatic protection circuit, a source terminal of the second NMOS transistor NM2, a drain terminal of the fourth NMOS transistor NM4, a drain terminal of the fifth NMOS transistor NM5 are connected to a drain terminal PM1 of the first NMOS transistor PM1, a source terminal and a substrate of the third NMOS transistor NM3, a substrate of the second NMOS transistor NM2, a source terminal and a substrate of the first NMOS transistor NM1, a source terminal and a substrate of the fourth NMOS transistor NM4, a substrate of the fifth NMOS transistor NM5, one end of the second resistor R2, one end of the third resistor R3, a ground terminal of the first comparator COM, a ground terminal of the first digital control circuit Logic control, a ground terminal of the third inverter INV3, a ground terminal of the fourth inverter INV4, a ground terminal of the fifth inverter INV5 are connected to the ground terminal VSS, a gate terminal of the third NMOS transistor NM3 is connected to an output terminal of the third inverter INV3, an input terminal of the third inverter INV3 is connected to the digital modulation signal S2, a gate terminal of the fourth NMOS transistor NM4 is connected to an output terminal of the fourth inverter INV4, an input terminal of the fourth inverter 4, an input terminal of the fifth NMOS transistor NM5, a gate terminal of the fifth NMOS transistor NM5 and an input terminal of the inverter INV 68525 are connected to the gate control signal EN _ INV3, an output end of the fifth inverter INV5 is connected to a gate end of the first PMOS transistor PM1, a source end of the fifth NMOS transistor NM5, a drain end of the first PMOS transistor PM1, and the other end of the second resistor R2 are connected to a positive input end of the first comparator COM, the other end of the third resistor R3 and an output end of the first reference current source IREF1 are connected to a negative input end of the first comparator COM, an output end of the first comparator COM is connected to an input end of the first digital control circuit Logic control, and an output end of the first digital control circuit Logic control is SWP _ TRIM < 3: 0>, the substrate of the first PMOS transistor PM1, the power supply terminal of the first comparator COM, the power supply terminal of the first digital control circuit Logic control, the power supply terminal of the third inverter INV3, the power supply terminal of the fourth inverter INV4, the power supply terminal of the fifth inverter INV5 are connected to the power supply terminal VDD.

Referring to fig. 3, in the embodiment of the invention, the reference current generating circuit 104 includes a second reference current source IREF2, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7, an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a drain terminal of the second PMOS transistor PM2 is connected to the input terminal VB of the emission circuit, a gate terminal of the second PMOS transistor PM2, gate and drain terminals of the third PMOS transistor PM3, source and substrate terminals of the fourth PMOS transistor PM4, PMOS and substrate terminals of the fifth PMOS transistor PM5, source and substrate terminals of the sixth PMOS transistor PM6, NM and substrate terminals of the seventh PMOS transistor PM5 are connected to the drain terminal terminals of the tenth NMOS transistor NM10, and drain terminal terminals of the PMOS transistors 7 7324, and the PMOS transistors PM 573 2, A source terminal and a substrate of the third PMOS transistor PM3 are connected to a power supply terminal VDD, a gate terminal of the fourth PMOS transistor PM4, a gate terminal of the fifth PMOS transistor PM5, a gate terminal of the sixth PMOS transistor PM6, and a gate terminal of the seventh PMOS transistor PM7 are respectively connected to the first output terminal SWP _ TRIM <1>, the second output terminal SWP _ TRIM <2>, the third output terminal SWP _ TRIM <3>, and the fourth output terminal SWP _ TRIM <4> of the transmitter circuit, a drain terminal of the fourth PMOS transistor PM4, a drain terminal of the fifth PMOS transistor PM5, a drain terminal of the sixth PMOS transistor PM6, and a drain terminal of the seventh PMOS transistor PM7 are respectively connected to a drain terminal of the sixth NMOS 6, a drain terminal of the seventh NMOS 7, a drain terminal of the eighth NMOS transistor NM8, a drain terminal of the ninth NMOS transistor NM9, a gate terminal of the sixth NMOS transistor NM6, a gate terminal of the seventh NMOS 9634, a gate terminal of the eighth NMOS 393638, a gate terminal of the NMOS 369638, a ninth NMOS 368938, a drain terminal of the NMOS transistor NM 9625, a gate terminal of the ninth NMOS 3638, and a drain terminal of the NMOS, A gate terminal of the tenth NMOS transistor NM10, a gate terminal and a drain terminal of the eleventh NMOS transistor NM11 are connected to an output terminal of the second reference current source IREF2, a source terminal and a substrate of the sixth NMOS transistor NM6, a source terminal and a substrate of the seventh NMOS transistor NM7, a source terminal and a substrate of the eighth NMOS transistor NM8, a source terminal and a substrate of the ninth NMOS transistor NM9, a source terminal and a substrate of the tenth NMOS transistor NM10, and a source terminal and a substrate of the eleventh NMOS transistor NM11 are connected to a ground terminal VSS.

Referring to fig. 3, an automatic calibration SWP slave interface circuit of the present invention works as follows:

first, when the control signal terminal TRIM _ EN is at a high level:

referring to fig. 1 and 3, when SWP enters the automatic calibration mode from the interface circuit, the first digital control circuit Logiccontrol output terminal SWP _ TRIM < 3: the binary value of 0> output is configured as 1000b by default, if the influence of temperature and process deviation on the current amplifier and the second reference current source IREF2 and the current mirror mismatching are neglected, the load modulation degree when the SWP transmits logic 1 from the interface is 840uA, but actually the temperature, the process deviation and the current mirror mismatching have influence on the current amplification factor and the second reference current source IREF2 deviation, so that the load modulation degree when the SWP transmits logic 1 from the interface is probably not in the 600 uA-1 mA interval, and the requirement of the SWP protocol is exceeded.

To solve the above problem, as shown in fig. 1 and fig. 3, each time the first enable control signal terminal TRIM _ EN of the SWP SIM card is powered up, the SWP enters the automatic calibration mode from the interface circuit, and if the output of the first comparator COM is high, the first digital control circuit Logic control decreases the output terminal SWP _ TRIM < 3: 0> binary value of output until the first comparator COM output is low and is used as the optimal amplification factor of the power amplifier; if the first comparator COM output is low, the first digital control circuit Logic control increases the output SWP _ TRIM < 3: 0> binary value of the output until the first comparator COM output is high and acts as the optimum amplification of the power amplifier. Current amplifier first stage current amplification factor: according to the current mirror ratio NM 11: NM 10: NM 9: NM 8: NM 7: NM6 as 2: 1: 2: 4: 8: 16, the output end SWP _ TRIM < 3: binary value of 0> output is greater than or equal to 0011b, the amplification factor is 4 uA-15.5 uA, step is 0.5uA, and the SWP is in a load modulation degree interval when the SWP transmits logic 1 from the interface circuit: the load modulation degree interval can cover the changes of temperature, handicraft difference and current mirror failure to the load modulation degree.

Secondly, when the control signal terminal TRIM _ EN is at a low level:

referring to fig. 1, the SWP slave interface circuit enters a normal operation mode, the SWPI is an input/output port of the SWP slave interface, the first diode D1 and the second diode D2 are electrostatic protection of the SWP interface, the SWP master interface circuit transmits the voltage signal S1 to the input end SWPI of the SWP slave interface circuit, the voltage signal S1 firstly passes through the first resistor R1 and the first capacitor C1 low-pass filter, then is shaped by the first schmitt trigger ST, and then passes through the first inverter INV1 and the second inverter INV2 of the two-stage buffer to increase the signal driving capability, and then is output to the digital circuit for processing. As shown in fig. 1 and 3, when the SWP slave interface circuit receives the voltage signal S1 as a high level signal, the SWP slave interface circuit transfers the current signal S2 by pulling down the second NMOS transistor NM2 and the third NMOS transistor NM 3: when the third NMOS transistor NM3 is turned on, the pull-down current of the second NMOS transistor NM2 is 600uA to 1000uA, and logic "1" is transmitted; when the third NMOS transistor NM3 is turned off, the second NMOS transistor NM2 is turned on, and the pull-down current is at-20 uA to 0uA, transmitting a logic "0".

As can be seen from the above, in the embodiment of the present invention, the stability of the SWP slave interface circuit is effectively improved and the production cost is reduced through the electrostatic protection circuit 101, the receiving circuit 102, the transmitting circuit 103 and the reference current generating circuit 104.

The above embodiments are merely illustrative of the basic idea of the present invention, and the constituent circuits related to the present invention are not drawn in terms of the number of constituent circuits, shapes, arrangement of devices, and connection modes in actual implementation. The actual implementation of the method can be changed freely according to the type, number, connection mode, device arrangement mode and device parameters of each circuit.

The above-mentioned embodiments are only preferred embodiments of the present invention, and do not limit the extension of the technical solution of the present invention. Any modifications, equivalent changes and obvious changes of the known technology made by the technical proposal of the invention by the technical personnel in the field are all within the protection scope of the invention.

Claims

1. An automatic calibration SWP slave interface circuit, wherein the SWP slave interface circuit comprises an electrostatic protection circuit, a receiving circuit, a transmitting circuit and a reference current generating circuit, the electrostatic protection circuit is connected with the receiving circuit, the receiving circuit is connected with the transmitting circuit, the transmitting circuit is connected with the reference current generating circuit, wherein,

the electrostatic protection circuit comprises a first diode and a second diode, wherein the anode of the second diode is connected with the input end and the output end of the electrostatic protection circuit, the cathode of the second diode is connected with a power supply end VDD, the cathode of the first diode is connected with the input end and the output end of the electrostatic protection circuit, and the anode of the first diode is connected with a ground end VSS;