CN211880375U - Single wire transmission circuit - Google Patents
Single wire transmission circuit Download PDFInfo
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- CN211880375U CN211880375U CN202020282747.1U CN202020282747U CN211880375U CN 211880375 U CN211880375 U CN 211880375U CN 202020282747 U CN202020282747 U CN 202020282747U CN 211880375 U CN211880375 U CN 211880375U
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Abstract
The utility model discloses a single-wire transmission circuit, which comprises a charging module, a voltage level detecting module and a bolt-lock module; the bolt-lock module is used for converting an input pulse signal into a control signal and starting the charging module according to the control signal; the charging module is used for charging the capacitor according to a preset logic rule; the voltage level detection module is used for judging the charged capacitance value and determining a level logic signal according to the capacitance value; the bolt-lock module is also used for receiving the level logic signal returned by the voltage level detection module and outputting the level logic signal in a single pulse mode, so that the output signal of the single-wire transmission circuit or the breakpoint continuous transmission circuit of the cascade data of the light-emitting diode integrated circuit is shaped, and the area of the layout can be effectively reduced.
Description
Technical Field
The utility model relates to a circuit control technical field especially relates to a single line transmission circuit.
Background
The traditional single-wire transmission data transmission mode of the cascade signal of the light-emitting diode integrated circuit is as follows:
an Integrated Circuit (IC) receives data transmitted from a controller, and since a signal transmitted by the controller in a single-wire transmission architecture is transmitted to the IC through only one transmission line, each bit of data is defined to be composed of two high and low level bits, and a data logic "1" or "0" is determined by a time ratio of the high and low level bits.
Each integrated circuit receives the signal from the controller, deducts its own display data, and then transmits the other data to the next integrated circuit. In the transmission process, due to the variation of the manufacturing process and the influence of the stray capacitance of the line, the signal waveform has a slight delay in the transition state, however, the rising delay time and the falling delay time of the signal waveform are different, and once the number of integrated circuits is increased, the time ratio of the high level and the low level of the signal is possibly incorrect, so that the data needs to be shaped and then transmitted to the next integrated circuit.
As shown in fig. 1 and 2, the conventional signal reforming circuit includes a built-in oscillator for generating an oscillation signal with a fixed frequency, and the frequency of the oscillation signal is divided to generate a time ratio of two levels.
The first drawback of this re-shaping circuit is that the design accuracy of the oscillator module is very high, and the reset waveform is incorrect once the oscillation frequency is shifted. The second disadvantage is that the design precision requirement is high, and a band gap reference (bandgap) constant voltage circuit and a comparator circuit are often used, which occupies a large layout area.
Novel content
To solve the above technical problem, the present novel embodiment provides a single-wire transmission circuit. The embodiment of the present invention provides a single line transmission circuit, including: the charging module, the voltage level detection module and the bolt-lock module;
the bolt-lock module is used for converting an input pulse signal into a control signal and starting the charging module according to the control signal;
the charging module is used for charging the capacitor according to a preset logic rule;
the voltage level detection module is used for judging the charged capacitance value and determining a level logic signal according to the capacitance value;
the bolt-lock module is also used for receiving the level logic signal returned by the voltage level detection module and outputting the level logic signal in a single pulse mode.
Optionally, the charging module includes a first charging unit and a second charging unit, where the first charging unit charges the capacitor with a first current, and the second charging unit charges the capacitor with a second current, where a current value of the second current is greater than a current value of the first current.
Optionally, the charging module is configured to charge the capacitor according to a preset logic rule, and includes:
when the level logic signal is a high level signal, the charging module charges the capacitor by using the first charging unit;
and when the level logic signal is a low level signal, the charging module charges the capacitor by adopting the second charging unit.
Optionally, the charging module charges the capacitor by using the first charging unit, and includes:
under the condition that the first switch is turned on, the second switch is turned on and the third switch is turned off, the charging module charges the capacitor by adopting a first current.
Optionally, the charging module charges the capacitor by using the second charging unit, and includes:
and under the conditions that the first switch is turned on, the second switch is turned on and the third switch is turned on, the charging module charges the capacitor by adopting a second current.
Optionally, the voltage level detecting module is configured to determine the charged capacitance value, and determine a level logic signal according to the capacitance value, and includes:
the voltage level detection module judges the charged capacitance value;
if the charged capacitance value is smaller than a preset state-transition input voltage critical value, outputting a low level signal;
and if the charged capacitance value is larger than the preset state-transition input voltage critical value, outputting a high level signal.
Optionally, the circuit further comprises a reset module, and the reset module is configured to reset the latch module.
Optionally, the first switch, the second switch and the third switch are all CMOS transistors.
Optionally, the latch module includes two nor gates, and output ends of the two nor gates are respectively used as inputs for carrying one nor gate.
In the technical solution provided in the present invention, a single-wire transmission circuit is provided, which includes a charging module, a voltage level detecting module, and a latch module; the bolt-lock module is used for converting an input pulse signal into a control signal and starting the charging module according to the control signal; the charging module is used for charging the capacitor according to a preset logic rule; the voltage level detection module is used for judging the charged capacitance value and determining a level logic signal according to the capacitance value; the bolt-lock module is also used for receiving the level logic signal returned by the voltage level detection module and outputting the level logic signal in a single pulse mode, so that the shaping of the output signal of the breakpoint continuous transmission circuit is realized, and the area of the layout can be effectively reduced.
Drawings
FIG. 1 is a schematic diagram of a prior art logic for transferring data in an integrated circuit;
FIG. 2 is a schematic diagram of an embodiment of output signal shaping of a conventional integrated circuit;
fig. 3 is a schematic structural diagram of a single-wire transmission circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a single-wire transmission circuit according to another embodiment of the present invention;
fig. 5 is a schematic circuit diagram of signal shaping of a single-wire transmission integrated circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without inventive step, are within the scope of the present invention.
Referring to fig. 3, a single-line transmission circuit according to an embodiment of the present invention includes: a charging module 102, a voltage level detecting module 103 and a latch module 101;
the latch module 101 is configured to convert an input pulse signal into a control signal, and turn on the charging module according to the control signal;
the charging module 102 is configured to charge a capacitor according to a preset logic rule;
the voltage level detection module 103 is configured to determine a charged capacitance value and determine a level logic signal according to the capacitance value;
the latch module 101 is further configured to receive the level logic signal returned by the voltage level detection module, and output the level logic signal in a form of a single pulse.
Specifically, the input part of the circuit of the whole embodiment has a fixed pulse signal, namely an input pulse signal and a transmission logic signal, the fixed pulse signal generates a control signal after passing through a bolt-lock circuit, namely a bolt-lock module, and a charging circuit is opened, namely a charging module is started, and the charging module starts to charge a capacitor; the transmission logic signal, i.e., the level logic signal, is a signal that is maintained at a high level when a logic "1" is confirmed and is maintained at a low level when a logic "0" is confirmed by the previous logic determination.
The voltage level detection module 103 is configured to determine the charged capacitance value, determine a level logic signal according to the capacitance value, that is, the transmission logic signal described above, and return the level logic signal to the latch module, so as to output the shaped single pulse signal.
The single-wire transmission circuit provided by the embodiment of the invention comprises a charging module, a voltage level detection module and a bolt-lock module; the bolt-lock module is used for converting an input pulse signal into a control signal and starting the charging module according to the control signal; the charging module is used for charging the capacitor according to a preset logic rule; the voltage level detection module is used for judging the charged capacitance value and determining a level logic signal according to the capacitance value; the bolt-lock module is also used for receiving the level logic signal returned by the voltage level detection module and outputting the level logic signal in a single pulse mode, so that the shaping of the output signal of the breakpoint continuous transmission circuit is realized, and the area of a layout can be effectively reduced.
Optionally, the charging module includes a first charging unit and a second charging unit, where the first charging unit charges the capacitor with a first current, and the second charging unit charges the capacitor with a second current, where a current value of the second current is greater than a current value of the first current.
Specifically, the charging module is a dual-current charging circuit, which can provide a large current and a small current to charge the capacitor, for example, the current value of the second current is larger than that of the first current.
Optionally, the charging module is configured to charge the capacitor according to a preset logic rule, and includes:
when the level logic signal is a high level signal, the charging module charges the capacitor by using the first charging unit;
and when the level logic signal is a low level signal, the charging module charges the capacitor by adopting the second charging unit.
Specifically, the dual-current charging circuit charges the capacitor according to a data logic judgment circuit, i.e., a preset logic rule, and different data logic judgment circuits charge different currents to the capacitor, so that different high level time is caused, and further, the shaping effect of the output waveform is achieved.
Optionally, the charging module charges the capacitor by using the first charging unit, and includes:
under the condition that the first switch is turned on, the second switch is turned on and the third switch is turned off, the charging module charges the capacitor by adopting a first current.
Optionally, the charging module charges the capacitor by using the second charging unit, and includes:
and under the conditions that the first switch is turned on, the second switch is turned on and the third switch is turned on, the charging module charges the capacitor by adopting a second current.
Fig. 4 is a schematic diagram of a single-wire transmission circuit according to another embodiment of the present invention, as shown in fig. 4, the input signals in this embodiment are a start pulse signal and a transmission logic signal, where the start pulse signal is an input pulse signal, and the transmission logic signal is a level logic signal, and after the previous logic determination, a high level signal is maintained when logic "1" has been confirmed, and a low level signal is maintained when logic "0" has been confirmed.
When the input pulse signal passes through the latch circuit, SW1 and SW2 are turned on, VC starts to charge, and the capacitor voltage reaches the threshold value of the input voltage of the voltage level detection circuit, the output is transited and resets the latch circuit to form a single pulse output, wherein SW1 is a first switch, SW2 is a second switch, and SW3 is a third switch.
When the transmission logic signal is at high level, i.e. "1", the switch SW3 is turned off, and the capacitor is only supplied with the first current, i.e. the current I1The charging of the capacitor is slow, the VC voltage level rises slowly from 0V, and the time for reaching the transition input voltage threshold of the voltage level detection circuit is long, so the wave width of the circuit generating single pulse is wide.
When the transmission logic signal is at low level "0", the switch SW3 is turned on, and the capacitor is powered by the second current, i.e. the current I1And I2Meanwhile, the capacitor is charged quickly, the VC potential rises quickly from 0V, and the time for reaching the transition input voltage threshold value of the voltage level detection circuit is short, so that the wave width of the circuit for generating single pulse is narrow.
Optionally, the voltage level detecting module is configured to determine the charged capacitance value, and determine a level logic signal according to the capacitance value, and includes:
the voltage level detection module judges the charged capacitance value;
if the charged capacitance value is smaller than a preset state-transition input voltage critical value, outputting a low level signal;
and if the charged capacitance value is larger than the preset state-transition input voltage critical value, outputting a high level signal.
It should be noted that the preset transition input voltage threshold may be set according to actual needs, and is not specifically limited in the present embodiment.
For example, if the charged capacitance value is 2.1V, the preset transition state input voltage threshold value is 3.5V, and 2.1V is smaller than 3.5V, a low level signal is output, i.e., "0";
if the capacitor is charged all the time, the capacitance value after charging is 3.7V, and at this time, 3.7V is less than 3.5V, a high level signal is output, that is, "1" is output.
Optionally, the circuit further comprises a reset module, and the reset module is configured to reset the latch module.
Specifically, the circuit further comprises a resetting module which is used for resetting the signal of the bolt-lock module and starting the pulse shaping of the next round.
Optionally, the first switch, the second switch and the third switch are all CMOS transistors.
Optionally, the latch module includes two nor gates, and output ends of the two nor gates are respectively used as inputs for carrying one nor gate.
Fig. 5 is a schematic circuit diagram of signal shaping of a single-wire transmission integrated circuit according to the present invention, as shown in fig. 5, an inverter I _11 receives an input pulse signal WIN, an output terminal of the inverter I _11 is connected to a nor gate, and then to each cmos, and finally, a level logic signal I _252_ VC3 is returned to an input terminal of the nor gate, an output terminal of the nor gate is connected to two inverter gates, and an output of the inverter gate is a shaped pulse signal.
The present invention further provides a single-wire transmission circuit for cascade data of a light emitting diode integrated circuit, which includes n single-wire transmission circuits as described above, where n is a positive integer greater than 0.
Specifically, the single-wire transmission circuit of the light emitting diode integrated circuit cascade data comprises n single-wire transmission circuits, namely a single-wire transmission circuit 1 and a single-wire transmission circuit 2 …, wherein D1 and D2 … Dn are private data of the single-wire transmission circuit 1 and the single-wire transmission circuit 2 …, and the digits of D1 and D2 … Dn are n digits;
further comprising a controller for sending transmission data C1, C2, D1, D2, … Dn to the single-wire transmission circuit 1; an output terminal DO of the single-wire transmission circuit 1 is connected to an input terminal DIN of the single-wire transmission circuit 2, and an output terminal DO of the single-wire transmission circuit 2 is connected to an input terminal DIN of the single-wire transmission circuit 3.
The single-wire transmission circuit 1 intercepts and stores D1, then outputs C1C2D2D3 … Dn to the single-wire transmission circuit 2, the single-wire transmission circuit 2 intercepts and stores D2, then outputs C1C2D3D4 … Dn to the single-wire transmission circuit 3, the single-wire transmission circuit 3 intercepts and stores D3, then outputs C1C2D4D5 … Dn to the integrated circuit 4, and the … single-wire transmission circuit n-1 intercepts and stores Dn-1, then outputs C1C2Dn to the single-wire transmission circuit Dn.
The present invention further provides a single-line transmission circuit of cascade data of a light emitting diode integrated circuit, which includes a charging module, a voltage level detecting module and a latch module; the bolt-lock module is used for converting an input pulse signal into a control signal and starting the charging module according to the control signal; the charging module is used for charging the capacitor according to a preset logic rule; the voltage level detection module is used for judging the charged capacitance value and determining a level logic signal according to the capacitance value; the bolt-lock module is also used for receiving the level logic signal returned by the voltage level detection module and outputting the level logic signal in a single pulse mode, so that the output signal of the single-wire transmission circuit or the breakpoint continuous transmission circuit of the cascade data of the light-emitting diode integrated circuit is shaped, and the area of the layout can be effectively reduced.
The above examples are only intended to illustrate the novel solution and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the present invention.
Claims (9)
1. A single-wire transmission circuit, comprising: the charging module, the voltage level detection module and the bolt-lock module;
the bolt-lock module is used for converting an input pulse signal into a control signal and starting the charging module according to the control signal;
the charging module is used for charging the capacitor according to a preset logic rule;
the voltage level detection module is used for judging the charged capacitance value and determining a level logic signal according to the capacitance value;
the bolt-lock module is also used for receiving the level logic signal returned by the voltage level detection module and outputting the level logic signal in a single pulse mode.
2. The circuit of claim 1, wherein the charging module comprises a first charging unit and a second charging unit, wherein the first charging unit charges the capacitor with a first current, and the second charging unit charges the capacitor with a second current, wherein a current value of the second current is greater than a current value of the first current.
3. The circuit of claim 2, wherein the charging module is configured to charge the capacitor according to a preset logic rule, and comprises:
when the level logic signal is a high level signal, the charging module charges the capacitor by using the first charging unit;
and when the level logic signal is a low level signal, the charging module charges the capacitor by adopting the second charging unit.
4. The circuit of claim 3, wherein the charging module charges the capacitor with the first charging unit, comprising:
under the condition that the first switch is turned on, the second switch is turned on and the third switch is turned off, the charging module charges the capacitor by adopting a first current.
5. The circuit of claim 3, wherein the charging module charges the capacitor with the second charging unit, comprising:
and under the conditions that the first switch is turned on, the second switch is turned on and the third switch is turned on, the charging module charges the capacitor by adopting a second current.
6. The circuit of claim 3, wherein the voltage level detection module is configured to determine the charged capacitance value and determine a level logic signal according to the capacitance value, and the determination comprises:
the voltage level detection module judges the charged capacitance value;
if the charged capacitance value is smaller than a preset state-transition input voltage critical value, outputting a low level signal;
and if the charged capacitance value is larger than the preset state-transition input voltage critical value, outputting a high level signal.
7. The circuit of claim 1, further comprising a reset module for resetting the latch module.
8. The circuit of claim 4 or 5, wherein the first switch, the second switch, and the third switch are all CMOS transistors.
9. The circuit of claim 1, wherein the latch module comprises two nor gates, and the output terminals of the two nor gates are respectively used as the input of one nor gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020282747.1U CN211880375U (en) | 2020-03-10 | 2020-03-10 | Single wire transmission circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020282747.1U CN211880375U (en) | 2020-03-10 | 2020-03-10 | Single wire transmission circuit |
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| Publication Number | Publication Date |
|---|---|
| CN211880375U true CN211880375U (en) | 2020-11-06 |
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| CN202020282747.1U Active CN211880375U (en) | 2020-03-10 | 2020-03-10 | Single wire transmission circuit |
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Legal Events
| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Single line transmission circuit Effective date of registration: 20220316 Granted publication date: 20201106 Pledgee: Pingtan Comprehensive Experimental Zone Xinping Financing Guarantee Co.,Ltd. Pledgor: Kaiqiang Technology (Pingtan) Co.,Ltd. Registration number: Y2022980002676 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20230830 Granted publication date: 20201106 Pledgee: Pingtan Comprehensive Experimental Zone Xinping Financing Guarantee Co.,Ltd. Pledgor: Kaiqiang Technology (Pingtan) Co.,Ltd. Registration number: Y2022980002676 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Single line transmission circuit Effective date of registration: 20230919 Granted publication date: 20201106 Pledgee: Pingtan Comprehensive Experimental Zone Xinping Financing Guarantee Co.,Ltd. Pledgor: Kaiqiang Technology (Pingtan) Co.,Ltd. Registration number: Y2023980057302 |
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| PE01 | Entry into force of the registration of the contract for pledge of patent right |