CN219918909U

CN219918909U - Level conversion circuit, chip and electronic equipment

Info

Publication number: CN219918909U
Application number: CN202321221413.3U
Authority: CN
Inventors: 叶学锋; 刘帅锋
Original assignee: Hefei Chipsea Electronics Technology Co Ltd
Current assignee: Hefei Chipsea Electronics Technology Co Ltd
Priority date: 2023-05-17
Filing date: 2023-05-17
Publication date: 2023-10-27
Anticipated expiration: 2033-05-17

Abstract

The application discloses a level conversion circuit, a chip and electronic equipment, wherein the level conversion circuit comprises a switch module, a pull-up module and a hysteresis comparison module; the switch module is provided with a first end for receiving an input signal, and the input signal is positioned in a first power domain independent of a second power domain; the switch module and the pull-up module are connected to the first node so as to adjust a node level signal of the first node according to an input signal, wherein the node level signal is opposite to the input signal; the hysteresis comparison module is connected to the first node to output an output signal in the second power domain according to the node level signal, and the output signal is in phase opposition to the node level signal. The level conversion circuit has a simple structure, can convert an input signal in a first power domain into an output signal in a second power domain, realizes the level conversion of signals under the condition of ensuring small circuit area and lower power consumption, improves the reliability of the level conversion circuit, and expands the application scene of the level conversion circuit.

Description

Level conversion circuit, chip and electronic equipment

Technical Field

The present application relates to the field of circuit technologies, and in particular, to a level shift circuit, a chip, and an electronic device.

Background

For integrated circuits, the level shifter circuit is a bridge for analog to digital communication. The digital circuit power supply is generally from a low dropout linear regulator (Low Dropout Regulator, LDO), the voltage is relatively low (such as 1.2V) and the withstand voltage of the adopted transistor is also low; in analog circuits, the supply voltage is relatively high (e.g., 1.8V/3.3V, etc.). When the analog-digital signals need to be mutually transmitted for communication, the level conversion circuit can convert the digital low-voltage signals into the analog high-voltage domain for communication with the analog, and convert the analog high-voltage signals into the digital low-voltage domain for communication with the digital.

Currently, if the power domains corresponding to the signals to be converted are associated, a reset release signal may be used as a Level Shift (LSH) gating signal to monitor, so as to prevent logic leakage caused by floating of the LSH output suspension signal.

However, if the power domain to which the signal to be converted corresponds is not relevant, LSH is cumbersome to handle and may require a sacrifice in power consumption and area in exchange for circuit function.

Disclosure of Invention

In view of the above, the present utility model provides a level shift circuit, a chip and an electronic device, so as to solve the above technical problems.

In a first aspect, the present application provides a level shift circuit, including a switch module, and a pull-up module and a hysteresis comparison module respectively operating in a second power domain;

the switch module is provided with a first end for receiving an input signal, and the input signal is positioned in a first power domain independent of a second power domain;

the switch module and the pull-up module are connected to the first node so as to adjust a node level signal of the first node according to an input signal, wherein the node level signal is opposite to the input signal;

the hysteresis comparison module is connected to the first node to output an output signal in the second power domain according to the node level signal, and the output signal is in phase opposition to the node level signal.

The level conversion circuit is simple in structure, can convert an input signal located in a first power domain into an output signal located in a second power domain, and the first power domain and the second power domain are mutually independent, so that the level conversion of signals is realized under the condition that the circuit area is small and the power consumption is low, the reliability of the level conversion circuit is improved, and the application scene of the level conversion circuit is expanded.

In a second aspect, the present application further provides a chip, including the level shifter circuit described above.

In a third aspect, the present application further provides an electronic device, including a device main body, and the chip or the level conversion circuit provided in the device main body.

The level conversion circuit provided by the application receives an input signal to be converted through a switch module, wherein the input signal is positioned in a first power domain, the switch module and a pull-up module are connected to a first node, and the node level signal of the first node is regulated according to the input signal, wherein the node level signal is opposite to the input signal, then an output signal opposite to the node level signal is output through a hysteresis comparison module connected to the first node, and the node level signal is opposite to the input signal, so that the output signal is in phase with the input signal, and the output signal is positioned in a second power domain independent of the first power domain, so that the input signal positioned in the first power domain is converted into an output signal in the second power domain which is not related to the first power domain, and the communication between analog and digital is realized; the level conversion circuit has a simple structure, can realize the conversion of signals on two mutually independent power domains under the conditions of ensuring small circuit area and lower power consumption, improves the reliability of the level conversion circuit, and expands the application scene of the level conversion circuit.

These and other aspects of the application will be more readily apparent from the following description of the embodiments.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a first circuit configuration of a level shifter circuit in the related art;

fig. 2 is a schematic diagram of a second circuit configuration of a level shifter circuit in the related art;

FIG. 3 is a logic timing diagram of a signal of the level shifter circuit shown in FIG. 2;

fig. 4 is a schematic diagram of an application scenario of a level shifter circuit according to an embodiment of the present application;

FIG. 5 is a block diagram of a level shifter circuit provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of a connection relationship of a switch module according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a switch module according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a pull-up module provided in an embodiment of the present application;

Fig. 9 is a schematic diagram of a first structure of a first impedance unit according to an embodiment of the present application;

fig. 10 is a schematic diagram of a second structure of the first impedance unit provided in the embodiment of the present application;

fig. 11 is a schematic diagram of a third structure of the first impedance unit provided in the embodiment of the present application;

fig. 12 is a schematic diagram of a fourth configuration of the first impedance unit provided in the embodiment of the present application;

fig. 13 is a schematic diagram of a fifth configuration of the first impedance unit provided in the embodiment of the present application;

FIG. 14 is a block diagram of a hysteresis comparison block provided in an embodiment of the present application;

FIG. 15 is a schematic diagram of a structure of a Schmitt trigger provided in an embodiment of the present application;

FIG. 16 is a schematic diagram showing a first connection relationship between a second impedance unit and a Schmitt trigger according to an embodiment of the present application;

FIG. 17 is a schematic diagram showing a second connection relationship between a second impedance unit and a Schmitt trigger according to an embodiment of the present application;

FIG. 18 is a schematic diagram showing a third connection relationship between a second impedance unit and a Schmitt trigger according to an embodiment of the present application;

FIG. 19 is a schematic diagram of another embodiment of a level shifter circuit provided in an embodiment of the present application;

FIG. 20 is a schematic diagram of a filter module according to an embodiment of the present application;

FIG. 21 is a schematic diagram of a further block diagram of a level shifter circuit provided in an embodiment of the present application;

FIG. 22 is a schematic diagram of a first buffer module according to an embodiment of the present application;

FIG. 23 is a schematic diagram of a further block diagram of a level shifter circuit provided in an embodiment of the present application;

FIG. 24 is a schematic diagram of a second buffer module according to an embodiment of the present application;

fig. 25 is a schematic circuit diagram of a level shifter circuit according to an embodiment of the present application;

fig. 26 is a signal logic timing diagram of the level shifter circuit shown in fig. 25.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application.

In order to enable those skilled in the art to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the present application in the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In describing embodiments of the present application, words such as "exemplary" or "such as" are used to mean illustrated, described, or described. Any embodiment or design described as "exemplary" or "such as" in an embodiment of the application is not necessarily to be construed as preferred or advantageous over another embodiment or design. The use of words such as "example" or "such as" is intended to present relative concepts in a clear manner.

In addition, the term "plurality" in the embodiments of the present application means two or more, and in view of this, the term "plurality" may be understood as "at least two" in the embodiments of the present application. "at least one" may be understood as one or more, for example as one, two or more. For example, including at least one means including one, two or more, and not limiting what is included, e.g., including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A and B and C, may be included.

It should be noted that, in the embodiment of the present application, "and/or" describe the association relationship of the association object, which means that three relationships may exist, for example, a and/or B may be represented: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship.

It should be noted that in embodiments of the present application, "connected" may be understood as electrically connected, and two electrical components may be connected directly or indirectly between the two electrical components. For example, a may be directly connected to B, or indirectly connected to B via one or more other electrical components.

The first pole/first end of each transistor employed in the embodiments of the present application is one of the source and the drain, and the second pole/second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor may be symmetrical in structure, the source and drain may be indistinguishable in structure, that is, the first pole/first terminal and the second pole/second terminal of the transistor in embodiments of the present application may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole/first terminal of the transistor is the source and the second pole/second terminal is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole/first terminal of the transistor is the drain and the second pole/second terminal is the source.

In the circuit structure provided by the embodiment of the application, the first node, the second node and other nodes do not represent actually existing components, but represent the junction points of the related coupling in the circuit diagram, that is, the nodes are equivalent nodes formed by the junction points of the related coupling in the circuit diagram.

Before describing the level shift circuit, the chip and the electronic device of the present application, the relevant background information of the embodiments of the present application will be described first.

For integrated circuits, level shifting circuits are a bridge for analog and digital communication. For low power consumption and low delay design, the digital circuit power supply is generally from a low dropout linear regulator (Low Dropout Regulator, LDO), the voltage is relatively low (such as 1.2V) and the withstand voltage of the adopted transistor is also low; in analog circuits, the power supply voltage is relatively high (e.g., 1.8V/3.3V, etc.) in order for all circuit blocks to function properly.

When the modules need to mutually send data for communication, if a level conversion circuit is not provided, the analog logic circuit may generate larger leakage if a low-voltage signal from the digital is transmitted to the analog interface; in contrast, the transmission of the high voltage signal from the analog to the digital interface may cause reliability problems, for example, the low voltage tube works under high voltage for a long time, the leakage current leakage at the gate terminal may be large, and meanwhile, the gate oxide layer may be broken down, which is difficult to ensure the performance and the service life of the device; therefore, the level shifting circuit is particularly important, and the main functions of the level shifting circuit are to shift a digital low-voltage signal to an analog high-voltage domain to communicate with analog, and shift an analog high-voltage signal to a digital low-voltage domain to communicate with digital.

In addition, a corresponding level shifting module is also required inside the analog circuit, for example, in some communication modes (such as power down mode), a module that normally operates in the main power supply may need to switch to the battery VBAT domain, because it is not known which voltage of the main power supply and the battery VBAT is higher, and thus a level shifting module is also required at the time of switching.

If the power domains corresponding to the signals to be converted are related, the reset release signal of the Level conversion module can be used as a gating signal of Level Shift (LSH) to monitor, so as to prevent logic leakage caused by floating of the LSH output suspension signal. For example, assuming that the LDO is operating in a main power DVDD to generate a voltage of VDD1V2, if the signal in the digital VDD1V2 domain is to be converted to DVDD, the Ready signal of the LDO can be used as the LSH gating signal, which is used in the DVDD domain to indicate whether the LDO output voltage has been fully established.

For the level conversion circuit with correlation between power domains, two circuit structures shown in fig. 1 and 2 are mainly adopted in the related art, wherein the power domain where the input signal VIN is located is VDD1, the power domain where the output signal OUT is located is VDD2, the EN signal is a flag bit indicating whether the VDD1 domain has electricity or not, the EN signal is located under the VDD2 domain, if the EN signal is at a low level, the VDD1 domain is not electrified, and if the EN signal is at a high level, the VDD1 domain is electrified.

Referring to fig. 1, when the VDD1 domain is not powered, the EN signal is low, the transmission gates of the M1 pipe input terminal and the M2 pipe input terminal are turned off, the gate terminal of the M1 pipe is pulled up to the VDD2 domain, the gate terminal of the M2 pipe is pulled down to the ground, so the node L2 is pulled up to the VDD2 domain, and the output signal OUT is low.

When the VDD1 domain is electrified, the EN signal is at a high level, and the transmission gates of the input end of the M1 pipe and the input end of the M2 pipe are opened; when the input signal VIN is at a high level, the gate terminal of the M2 pipe is at a high level, the node L2 is pulled down to ground, and the output signal OUT is at a high level.

Referring to fig. 2 and 3, when the VDD1 domain is not powered, the EN signal is at a low level, and the ENA signal is at a low level through the output signal OUT output by the and gate; when the VDD1 domain is powered on, the EN signal is high, when the input signal VIN is high, the M1 gate terminal is high, the node L2 is pulled up to the VDD2 domain, and the output signal OUT is high.

As can be appreciated from the above examples, the VDD1 domain and VDD2 domain in fig. 1 and 2 are two power domains that are associated, whereas if the power domains corresponding to the signals that need to be converted are not associated, the present LSH is relatively cumbersome to handle, and may require sacrificing power consumption and area in exchange for circuit functions.

Based on this, the embodiment of the application provides a level conversion circuit, a chip and an electronic device, which are respectively described in detail below.

Referring to fig. 4, fig. 4 is a schematic diagram of an application scenario of the level shifter circuit provided in the embodiment of the application, and the level shifter circuit 100 may be integrated in a micro control unit (Micro Controller Unit, MCU) 200.

It is understood that the micro control unit 200 may be a general-purpose MCU or a dedicated MCU.

In other application scenarios, the level shifter 100 may be independent of the MCU, and may be specifically determined according to the actual application scenario.

It will be understood by those skilled in the art that the application environment shown in fig. 4 is only an application scenario adapted to the solution of the present application, and is not limited to the application scenario of the solution of the present application, and the level conversion circuit or the MCU integrated with the level conversion circuit of the present application may be applied to application scenarios such as communications, audio power amplifiers, power devices, automobiles, and the like, and is not limited herein specifically.

Referring to fig. 5, fig. 5 is a schematic block diagram of a level shifter circuit according to an embodiment of the present application, where the level shifter circuit 100 may include a switch module 110, and a pull-up module 120 and a hysteresis comparison module 130 respectively operating in a second power domain.

Wherein the switch module 110 is provided with a first end for receiving an input signal, which is located in a first power domain independent of a second power domain.

The switch module 110 and the pull-up module 120 are connected to the first node L1 to adjust a node level signal of the first node L1 according to the input signal, wherein the node level signal is opposite to the input signal.

The hysteresis comparison module 130 is connected to the first node L1 to output an output signal in the second power domain according to the node level signal, wherein the output signal is inverted from the node level signal.

In the embodiment of the application, the first power domain and the second power domain are two independent power domains, wherein the voltage of the first power domain can be higher than that of the second power domain, and the voltage of the second power domain can also be higher than that of the first power domain. That is, the level shift circuit of the present embodiment can level shift signals of two power domains whose magnitude relation is unknown.

The input signal may be an analog signal or a digital signal. For example, if the input signal is an analog signal, the output signal may be a digital signal; if the input signal is a digital signal, the output signal may be an analog signal. In the embodiment of the present application, the types of the input signal and the output signal may be determined according to the actual application scenario, which is not limited herein.

In the embodiment of the present application, the switch module 110 may adjust its own switch state according to the received input signal, so as to cooperate with the pull-up module 120, so that the node level signal at the first node L1 is opposite to the input signal. For example, if the input signal is high, the node level signal is low; conversely, if the input signal is low, the node level signal at that time is high.

It will be appreciated that in the case where no input signal is input or the first power domain is powered down, this may be considered as the case where the input signal is low, and the node level signal may also be high.

In the embodiment of the present application, the switch module 110, the pull-up module 120 and the hysteresis comparison module 130 are connected to the first node L1, so that the node level signal can be input to the hysteresis comparison module 130, and the output signal in the second voltage domain is obtained by inverting the node level signal with the input signal through the hysteresis comparison module 130.

For example, if the input signal is high, the node level signal is low, and since the output signal is inverted from the node level signal, the output signal is in phase with the input signal and is high; if the input signal is low, the node level signal is high, and the output signal is inverted from the node level signal, so that the output signal is in phase with the input signal and is low.

According to the level conversion circuit 100 provided by the embodiment of the application, the input signal to be converted is received through the switch module 110, the input signal is located in the first power domain, the switch module 110 and the pull-up module 120 are connected to the first node L1, the node level signal of the first node is regulated according to the input signal, wherein the node level signal is opposite to the input signal, then the output signal opposite to the node level signal is output through the hysteresis comparison module 130 connected to the first node L1, and because the node level signal is opposite to the input signal, the output signal is in phase with the input signal, and the output signal is located in the second power domain independent of the first power domain, so that the input signal located in the first power domain is converted into the output signal on the second power domain which is not related to the first power domain, and the communication between analog and digital is realized; the level conversion circuit 100 has a simple structure, can realize the conversion of signals on two mutually independent power domains under the condition of ensuring small circuit area and lower power consumption, improves the reliability of the level conversion circuit 100, and expands the application scene of the level conversion circuit 100.

Next, a detailed description of the modules shown in fig. 5 and the specific embodiments that may be employed in the practical application will be continued.

As shown in fig. 6, in some embodiments of the present application, the second terminal of the switch module 110 and the output terminal of the pull-up module 120 are connected to the first node L1, and the third terminal of the switch module 110 is connected to the first logic low terminal 101.

The second terminal of the switch module 110 and the third terminal of the switch module 110 may be used to be turned on when the input signal is at a high level, so that the first node L1 is equipotential with the first logic low level terminal 101;

conversely, the second terminal of the switch module 110 and the third terminal of the switch module 110 may be configured to be turned off when the input signal is at a low level, so that the first node L1 is equipotential with the output terminal of the pull-up module 120.

In the embodiment of the present application, when the input signal is at the high level, the switch module 110 may be turned on in response to the input signal at the high level, so that the second terminal and the third terminal are electrically turned on, and because the third terminal of the switch module 110 is connected to the first logic low level terminal 101, when the second terminal and the third terminal of the switch module 110 are electrically turned on, the potential of the first node L1 is equal to the potential of the first logic low level terminal 101, that is, the first node L1 is pulled down to be at the same potential as the first logic low level terminal 101, so that the node level signal at the moment is at the low level, that is, is opposite to the input signal at the high level.

When the input signal is at a low level, the switch module 110 may be turned off in response to the low level input signal, so that the second end and the third end are electrically disconnected, and since the pull-up module 120 operates in the second power domain, the two ends of the pull-up module 120 have a voltage difference when the second power domain is powered, so that the output end of the pull-up module is at a high level, and since the second end and the third end of the switch module 110 are electrically disconnected, the potential of the first node L1 is equal to the potential of the output end of the pull-up module 120, and the first node L1 is pulled up to a high level, that is, the node level signal is at a high level, that is, opposite to the low level input signal.

As shown in fig. 7, in some embodiments of the present application, the switch module 110 may include a first transistor MN1, a control terminal of the first transistor MN1 is configured to receive an input signal, a first terminal of the first transistor MN1 and the pull-up module 120 are connected to the first node L1, and a second terminal of the first transistor MN1 is connected to the first logic low terminal 101.

In the embodiment of the present application, the first logic low level terminal 101 is set to the ground GND, it can be appreciated that in some other application scenarios, the first logic low level terminal 101 may be set to other ports or units capable of providing a low level, which is not limited herein.

The first transistor MN1 may be an N-channel Metal-Oxide-semiconductor field effect transistor (MOSFET), i.e., an NMOS transistor, and the gate of the first transistor MN1 is configured to receive an input signal, the source of the first transistor MN1 is connected to the ground GND, and the drain of the first transistor MN1 and the pull-up module 120 are connected to the first node L1.

As can be seen from the characteristics of the NMOS transistor, when the input signal is at the high level, the gate of the first transistor MN1 is applied with the high level, the source and the drain of the first transistor MN1 are turned on, so that the potential of the first node L1 is pulled down to the ground, i.e., the low level, and the node level signal is at the low level; when the input signal is at a low level, the source and the drain of the first transistor MN1 are disconnected, and the potential of the first node L1 is equal to the potential of the output terminal of the pull-up module 120 on the premise that the second power domain is powered on, so that the node level signal is at a high level.

When no input signal is input or the first power domain is not powered, the gate of the first transistor MN1 is in a high-resistance state, and the drain and the source are disconnected, and when the second power domain is powered, the potential of the first node L1 is equal to the potential of the output end of the pull-up module 120, and the node level signal is also in a high level.

In the embodiment of the present application, the reset release gating signal is not required to be generated to monitor the LSH, and the node level signal is continuously kept at the high level under the condition that the first power domain is powered off and the second power domain is powered on, so that the output signal of the level conversion circuit 100 is always fixed to be output at the low level.

It can be appreciated that the first transistor MN1 may be any existing controllable switching device, such as a triode, an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), or the like, besides an NMOS transistor, and the type of the first transistor may be determined according to an actual application scenario, which is not limited in this embodiment.

Referring to fig. 8, fig. 8 is a schematic diagram of a pull-up module according to an embodiment of the application, in some embodiments of the application, the pull-up module 120 may include a first impedance unit 1201, a first end of the first impedance unit 1201 is connected to the voltage source 102 of the second power domain, and a second end of the first impedance unit 1201 and the switch module 110 are connected to the first node L1.

As can be seen from the description of the above embodiments, the potential of the first node L1 is equal to the potential of the output terminal of the pull-up module 120 when the switch module 110 is turned off, and thus the first impedance unit 1201 can be used to pull up the potential of the first node L1 when the switch module 110 is not turned on.

In some embodiments of the present application, the first impedance unit 1201 may include at least one resistor element, each resistor element being serially connected in turn, a first end of the first resistor element being connected to the voltage source 102 of the second power domain, and a second end of the second resistor element being connected to the first node L1.

As shown in fig. 9, as a first example, the first impedance unit 1201 includes a first resistor R1, one end of the first resistor R1 is connected to the voltage source 102 of the second power domain, and the other end is connected to the first node L1.

When the input signal is at a low level or the first power domain is not powered, the switch module 110 is turned off, and since the second power domain is powered, there is a voltage drop across the first resistor R1, so that the potential of the first node L1 is pulled up to a high level due to the first resistor R1, thereby making the node level signal at a high level.

As shown in fig. 10, as a second example, the first impedance unit 1201 includes a first resistor R1 and a second resistor R2 connected in series, a first end of the first resistor R1 being connected to the voltage source 102 of the second power domain, and a second end of the second resistor R2 being connected to the first node L1.

Similarly, when the input signal is at a low level or the first power domain is not powered, the switch module 110 is turned off, and since the second power domain is powered, there is a voltage drop across the first resistor R1 and the second resistor R2, and thus the potential of the first node L1 is pulled up to a high level due to the presence of the first resistor R1 and the second resistor R2, so that the node level signal is at a high level.

It will be appreciated that, in some other application scenarios, the first impedance unit 1201 may further include more resistors connected in series, each resistor may be connected in series sequentially to form a resistor string connected between the voltage source 102 and the first node L1, and the resistance value of the resistor string may determine the speed of the rising/falling edge of the logic level transition, generally, the larger the resistance value, the lower the speed, and the smaller the power consumption, so that the number of resistors and the resistance value of the first impedance unit 1201 may be determined in consideration of the requirements of the power consumption and the speed in the actual application scenarios, which is not limited herein.

In other embodiments of the present application, the first impedance unit 1201 may include at least one P-type transistor, wherein a control terminal of each P-type transistor is connected to the first node L1, a first terminal of the first-terminal P-type transistor is connected to the voltage source 102 of the second power domain, and a second terminal of the first-terminal P-type transistor is connected to a first terminal of a next P-type transistor adjacent thereto; the first end of the terminal P-type transistor is connected to the second end of the last P-type transistor adjacent to the first end of the terminal P-type transistor, and the second end of the terminal P-type transistor is connected to the first node L1.

As shown in fig. 11, as a third example, the first impedance unit 1201 includes a second transistor MP2, a control terminal, i.e., a gate and a drain, of the second transistor MP2 is connected to the first node L1, and a source of the second transistor MP2 is connected to the voltage source 102 of the second power domain.

When the input signal is at a low level or the first power domain is not powered, the switch module 110 is turned off, and when the voltage source 102 is powered, the second transistor MP2 is turned on, and there is a voltage drop between the gate and the source, so that the potential of the first node L1 is gradually pulled up to a high level due to the second transistor MP2, so that the node level signal is at a high level.

As shown in fig. 12, as a fourth example, the first impedance unit 1201 includes a second transistor MP2 and a third transistor MP3, control terminals, i.e., gates, of the second transistor MP2 and the third transistor MP3 are respectively connected to the first node L1, a source of the second transistor MP2 is connected to the voltage source 102 of the second power domain, a drain of the second transistor MP2 is connected to a source of the third transistor MP3, and a drain of the third transistor MP3 is connected to the first node L1.

Similarly, when the input signal is at a low level or the first power domain is not powered, the switch module 110 is turned off, and the second transistor MP2 and the third transistor MP3 are turned on when the voltage source 102 is powered, so that the potential of the first node L1 is gradually pulled up to a high level due to the second transistor MP2 and the third transistor MP3, thereby making the node level signal at a high level.

In an embodiment of the present application, the second transistor MP2 and the third transistor MP3 may be P-channel Metal-Oxide-semiconductor field effect transistors (MOSFETs), i.e., PMOS transistors.

It will be appreciated that in some other application scenarios, the first impedance unit 1201 may further include more P-type transistors, and the number of P-type transistors may be determined according to the actual application scenario, which is not limited herein.

Based on the descriptions of the above embodiments, in further embodiments of the present application, the first impedance unit 1201 may include at least one resistive element and at least one P-type transistor.

The resistor elements are connected in series in sequence, a first end of the first end resistor element is connected with the control end of each P-type transistor and a second end of the tail end P-type transistor, and a second end of the tail end resistor element is connected with the first node L1.

The first end of the first-end P-type transistor is connected with the voltage source 102 of the second power domain, the second end of the first-end P-type transistor is connected with the first end of the next P-type transistor adjacent to the first-end P-type transistor, and the first end of the tail-end P-type transistor is connected with the second end of the last P-type transistor adjacent to the first-end P-type transistor.

As shown in fig. 13, as a fifth example, the first impedance unit 1201 includes a first resistor R1, a second transistor MP2, and a third transistor MP3, control terminals, i.e., gates, of the second transistor MP2 and the third transistor MP3 are respectively connected to a first terminal of the first resistor R1, a source of the second transistor MP2 is connected to the voltage source 102 of the second power domain, a drain of the second transistor MP2 is connected to a source of the third transistor MP3, a drain of the third transistor MP3 is also connected to a first terminal of the first resistor R1, and a second terminal of the first resistor R1 is connected to the first node L1.

In this embodiment, when the input signal is at a low level or the first power domain is not powered, the switch module 110 is turned off, and when the voltage source 102 is powered, the potential of the first node L1 is gradually pulled up to a high level due to the second transistor MP2, the third transistor MP3 and the first resistor R1, so that the node level signal is at a high level.

It can be appreciated that the resistance in the first impedance unit 1201 and the specifications of the transistors may be determined according to the practical application scenario, for example, if power consumption needs to be saved, the resistance of the first resistor R1 may be relatively large, and the aspect ratio of the second transistor MP2 and the third transistor MP3 may be relatively small.

Referring to fig. 14, in some embodiments of the present application, the hysteresis comparison module 130 may include a schmitt trigger 1301, wherein an input terminal of the schmitt trigger 1301 is connected to the first node L1, a high-level pin of the schmitt trigger 1301 is connected to the voltage source 102 of the second power domain, and a low-level pin of the schmitt trigger 1301 is connected to the second logic low-level terminal 103.

The schmitt trigger 1301 may be configured to output an output signal of a high level when the node level signal is a low level, and output an output signal of a low level when the node level signal is a high level.

Since the schmitt trigger 1301 in this embodiment can be used for waveform shaping and inversion, the schmitt trigger 1301 in this embodiment can output an output signal of a high level when the node level signal is a low level and an output signal of a low level when the node level signal is a high level to ensure that the output signal of the level shift circuit coincides with the phase of the input signal of the level shift circuit.

In this embodiment, the schmitt trigger 1301 may be any type of schmitt trigger currently available, including but not limited to a schmitt trigger composed of a gate circuit, an integrated schmitt trigger, etc., and may be specifically determined according to an actual application scenario, which is not limited herein.

As shown in fig. 15, fig. 15 is a schematic diagram of a schmitt trigger provided in the embodiment of the present application, wherein the schmitt trigger 1301 is one of integrated schmitt triggers, in the embodiment, the voltage source 102 of the second power domain generates the power voltage VDD2, the second logic low level 103 is set to the ground GND, the schmitt trigger 1301 includes a fourth transistor MN4, a fifth transistor MN5, a sixth transistor MP6, a seventh transistor MP7, an eighth transistor MP8, a ninth transistor MN9, a tenth transistor MN10 and an eleventh transistor MP11, wherein the fourth transistor MN4, the fifth transistor MN5, the ninth transistor MN9 and the tenth transistor MN10 are NMOS transistors, the sixth transistor MP6, the seventh transistor MP7, the eighth transistor MP8 and the eleventh transistor MP11 are PMOS transistors, and the specific circuit connection structure is omitted herein.

Since there may be voltage fluctuations at the voltage source 102 or the ground GND that affect the normal operation of the schmitt trigger 1301, in some embodiments of the present application, the hysteresis comparison module 130 may further include a second impedance unit that may be connected between the schmitt trigger 1301 and the voltage source 102 of the second power domain and/or between the schmitt trigger 1301 and the second logic low level terminal 103.

Specifically, as shown in fig. 16, as an example, the second impedance unit may include a third resistor R3, where one end of the third resistor R3 is used to receive the supply voltage VDD2 generated by the voltage source 102, and the other end is connected to the gate of the tenth transistor MN10, so as to avoid the impact of the fluctuation of the supply voltage VDD2 on the device.

As another example, as shown in fig. 17, the second impedance unit may include a fourth resistor R4, one end of the fourth resistor R4 is connected to the ground GND, and the other end is connected to the gate of the eleventh transistor MP11, so as to avoid the voltage fluctuation of the ground GND from striking the device.

As yet another example, as shown in fig. 18, the second impedance unit may include a third resistor R3 and a fourth resistor R4, wherein one end of the third resistor R3 is used for receiving the power supply voltage VDD2 generated by the voltage source 102, and the other end is connected to the gate of the tenth transistor MN 10; one end of the fourth resistor R4 is connected to the ground GND, and the other end is connected to the gate of the eleventh transistor MP11, so as to avoid the impact of the power voltage VDD2 and the voltage fluctuation of the ground GND on the device.

Referring to fig. 19, in some embodiments of the present application, the level shifter circuit 100 may further include a filtering module 140, wherein a first end of the filtering module 140 is connected to the first node L1, and a second end of the filtering module 140 is connected to the third logic low level end 104 to perform filtering processing on the node level signal.

In the embodiment of the present application, by setting a filtering module 140 at the first node L1, the node level signal input to the hysteresis comparing module 130 can be filtered, so as to eliminate interference signals such as burrs, clutters, and the like, which may exist in the node level signal.

As shown in fig. 20, as an embodiment, the filtering module 140 may include a filtering capacitor C1, where one end of the filtering capacitor C1 is connected to the first node L1, and the other end of the filtering capacitor C1 is connected to the third logic low level end 104, and in this embodiment, the third logic low level end 104 is set to the ground GND.

In this embodiment, according to the characteristic that the voltages at the two ends of the capacitor cannot be suddenly changed, the filtering capacitor C1 absorbs burrs, clutters and the like in the node level signal, so that the node level signal input to the hysteresis comparison module 130 is ensured to be free from interference, and the reliability of the level conversion circuit is improved.

It can be appreciated that in some other application scenarios, the filtering module 140 may be any existing filtering circuit such as an LC filtering circuit and an RC filtering circuit, which may be specifically determined according to the actual application scenario, and is not limited herein.

Referring to fig. 21, in some embodiments of the present application, the level shifter circuit 100 may further include a first buffer module 150 operating in the first power domain, where an input terminal of the first buffer module 150 is connected to a signal input terminal of the input signal to receive the input signal; an output terminal of the first buffer module 150 is connected to a first terminal of the switch module 110.

In the embodiment of the present application, the first buffer module 150 may be any existing buffer, as shown in fig. 22, and as an example, the first buffer module 150 includes two serial not gates. It will be appreciated that in other application scenarios, the first buffer module 150 may also have more NOT gates. It should be noted that the number of the not gates included in the first buffer module 150 should be even, so as to avoid inverting the input signal input to the switch module 110.

Of course, in some application scenarios, the number of the not gates may be allowed to be odd, and at this time, the output signal output finally is only required to be inverted once through the inverter, so that the phase of the output signal is ensured to be consistent with that of the input signal.

Referring to fig. 23, in some embodiments of the present application, the level shifter circuit 100 may further include a second buffer module 160 operating in the second power domain, an input terminal of the second buffer module 160 is connected to an output terminal of the hysteresis comparator module 130, and an output terminal of the second buffer module 160 is configured to output an output signal.

In the embodiment of the present application, the second buffer module 160 may be any existing buffer, as shown in fig. 24, and as an example, the second buffer module 160 includes two serial not gates. It will be appreciated that in other application scenarios, the second buffer module 160 may also include more NOT gates. It should be noted that the number of the not gates included in the second buffer module 160 should be even, so as to avoid the inversion of the output signal and the input signal.

Of course, in some application scenarios, the number of the NOT gates may be allowed to be odd, and at this time, the output signal is only inverted once through the inverter, so that the phase of the output signal is consistent with that of the input signal.

On the basis of the above embodiments, the present application also provides a chip, which may include the level shifter circuit as in any of the embodiments of fig. 5 to 24. The Chip may be an integrated circuit (Integrated Circuit, IC), or microcircuit, microchip, wafer/Chip (Chip), which may be, but is not limited to, a System On Chip (SOC), system in package (System In Package, SIP) Chip.

The chip is provided with the level conversion circuit of the above embodiment, so that the level conversion circuit of any one of the above embodiments has all the advantages, and will not be described herein.

The embodiment of the application also provides electronic equipment, which can comprise an equipment main body and the chip or the level conversion circuit arranged in the equipment main body. The electronic device may be, but is not limited to, a body weight scale, a body fat scale, a nutritional scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a vehicle-mounted charger, an adapter, a display, a universal serial bus (Universal Serial Bus, USB) docking station, a stylus, a true wireless smart (True Wireless Stereo, TWS) headset, an automobile center control unit, an automobile, an intelligent wearable device, a mobile terminal, an intelligent home device.

Wherein, intelligent wearing equipment includes but is not limited to intelligent wrist-watch, intelligent bracelet, cervical vertebra massage appearance. Mobile terminals include, but are not limited to, smartphones, notebook computers, tablet computers, point-of-sale terminals (point of sales terminal, POS). The intelligent household equipment comprises, but is not limited to, an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp.

The electronic device is provided with the level conversion circuit of the above embodiment, so that the level conversion circuit of any one of the above embodiments has all the advantages, and will not be described herein.

Referring to fig. 25, fig. 25 is a schematic circuit diagram of a level shifter circuit according to an embodiment of the present application, wherein the level shifter circuit includes a first buffer including a first not gate N1 and a second not gate N2, a first transistor MN1, a pull-up unit including a first resistor R1, a second transistor MP2 and a third transistor MP3, a schmitt trigger including fourth transistors MN4 to MP11, an anti-impact unit including a third resistor R3 and a fourth resistor R4, and a second buffer including a third not gate N3 and a fourth not gate N4.

The first buffer is connected with the input end of the input signal VIN, works under the first power domain and is powered by the power voltage VDD1 of the first power domain; the second buffer is connected with the output end of the output signal OUT, works under the second power domain and is powered by the power supply voltage VDD2 of the second power domain;

the source of the second transistor MP2, the source of the seventh transistor MP7, the third resistor R3 and the source of the eleventh transistor MP11 are connected to the second power domain, and are also supplied by the power supply voltage VDD2 of the second power domain;

The source of the first transistor MN1, the source of the fourth transistor MN4, the fourth resistor R4 and the drain of the tenth transistor MN10 are connected to the ground GND.

The input signal VIN belongs to a first power domain, the output signal OUT belongs to a second power domain, and the first power domain and the second power domain are independent of each other, and the working principle of the level shift circuit according to the embodiment of the present application is described below with reference to fig. 25 and 26:

(1) When the first power domain is powered off and the second power domain is powered on, that is, no power supply voltage VDD1 is provided and no power supply voltage VDD2 is provided, the gate of the first transistor MN1 presents a high resistance state, the drain thereof, that is, the first node L1, is gradually pulled up to VDD2-Vsg2 due to the presence of the first resistor R1, the second transistor MP2 and the third transistor MP3, the Vsg2 is the voltage between the source and the gate of the second transistor MP2, and in order to save power consumption, the size of the first resistor R1 is relatively large, and the aspect ratio of the second transistor MP2 and the third transistor MP3 is relatively small.

The high level node voltage signal at the first node L1 is transmitted and inverted by the schmitt trigger, and the low level output signal OUT is output through the second buffer. It is noted that the input high level of the schmitt trigger is designed below the value of (VDD 2-Vsg 2) to ensure that the voltage state at the first node L1 can be normally identified.

(2) When both the first power domain and the second power domain have electricity, that is, the power voltage VDD1 and the power voltage VDD2 supply power simultaneously, if the input signal VIN is at a high level, the first transistor MN1 is turned on, and the first node L1 is connected to the ground GND, so that the first node L1 is pulled down to a low level, the node voltage signal at the low level at the first node L1 is transmitted and inverted by the schmitt trigger, and the output signal OUT at a high level is output by the second buffer, and at this time, the phase of the output signal OUT is consistent with that of the input signal VIN.

If the input signal VIN is at a low level, the first transistor MN1 is turned off, the potential of the first node L1 is pulled up to VDD2-Vsg2, the node voltage signal at the high level at the first node L1 is transmitted and inverted by the schmitt trigger, and the output signal OUT at the low level is output by the second buffer, and at this time, the output signal OUT is identical to the input signal VIN in phase.

The level conversion circuit of the embodiment has a simple structure, can maintain and output low-level output signals when the first power domain is powered off, does not need to reset and release the monitoring of the gate control signals, can realize the conversion of signals on two mutually independent power domains under the condition of ensuring small circuit area and lower power consumption, improves the application flexibility of the level conversion circuit, and expands the application scene of the level conversion circuit.

Although the present application has been described in terms of the preferred embodiments, it should be understood that the present application is not limited to the specific embodiments, but is capable of numerous modifications and equivalents, and alternative embodiments and modifications of the embodiments described above, without departing from the spirit and scope of the present application.

Claims

1. The level conversion circuit is characterized by comprising a switch module, a pull-up module and a hysteresis comparison module, wherein the pull-up module and the hysteresis comparison module are respectively operated in a second power domain;

the switch module is provided with a first end for receiving an input signal, and the input signal is positioned in a first power domain independent of the second power domain;

the switch module and the pull-up module are connected to a first node to adjust a node level signal of the first node according to the input signal, wherein the node level signal is opposite to the input signal;

The hysteresis comparison module is connected to the first node to output an output signal in the second power domain according to the node level signal, wherein the output signal is in phase opposition to the node level signal.

2. The level shifter circuit of claim 1, wherein the second terminal of the switch module and the output terminal of the pull-up module are connected to the first node, and the third terminal of the switch module is connected to a logic low level terminal;

the second end of the switch module and the third end of the switch module are used for being conducted when the input signal is in a high level so as to make the first node and the logic low level end equipotential;

the second end of the switch module and the third end of the switch module are used for being disconnected when the input signal is in a low level so as to make the first node and the output end of the pull-up module equipotential.

3. The level shifting circuit of claim 2, wherein the switching module comprises a first transistor having a control terminal for receiving the input signal, the first terminal of the first transistor and the pull-up module being connected to the first node, the second terminal of the first transistor being connected to the logic low level terminal.

4. The level shifting circuit of claim 1, wherein the pull-up module comprises a first impedance unit having a first end connected to the voltage source of the second power domain, and a second end connected to the first node with the switch module.

5. The level shifter circuit of claim 4, wherein the first impedance unit comprises at least one resistive element, each of the resistive elements being serially connected in series, a first end of a first resistive element being connected to the voltage source of the second power domain and a second end of a second resistive element being connected to the first node.

6. The level shifter circuit of claim 4, wherein the first impedance unit comprises at least one P-type transistor, the control terminal of each of the P-type transistors being connected to the first node, the first terminal of a head-end P-type transistor being connected to the voltage source of the second power domain, the second terminal of the head-end P-type transistor being connected to the first terminal of the next P-type transistor adjacent thereto; the first end of the terminal P-type transistor is connected with the second end of the last P-type transistor adjacent to the terminal P-type transistor, and the second end of the terminal P-type transistor is connected with the first node.

7. The level shifter circuit of claim 4, wherein the first impedance unit comprises at least one resistive element and at least one P-type transistor;

the resistor elements are sequentially connected in series, a first end of the head end resistor element is connected with the control end of each P-type transistor and a second end of the tail end P-type transistor, and a second end of the tail end resistor element is connected with the first node;

the first end of the head-end P-type transistor is connected with the voltage source of the second power domain, the second end of the head-end P-type transistor is connected with the first end of the next P-type transistor adjacent to the head-end P-type transistor, and the first end of the tail-end P-type transistor is connected with the second end of the last P-type transistor adjacent to the tail-end P-type transistor.

8. The level shifting circuit of claim 1, wherein the hysteresis comparison module comprises a schmitt trigger, an input of the schmitt trigger being connected to the first node, a high-level pin of the schmitt trigger being connected to a voltage source of the second power domain, a low-level pin of the schmitt trigger being connected to a logic low-level end;

the schmitt trigger is configured to output the output signal of a high level when the node level signal is of a low level, and output the output signal of a low level when the node level signal is of a high level.

9. The level shifting circuit of claim 8, wherein the hysteresis comparison module further comprises a second impedance unit connected between the schmitt trigger and a voltage source of the second power domain and/or between the schmitt trigger and the logic low level terminal.

10. The level shifter circuit of claim 1, further comprising a filter module having a first terminal coupled to the first node and a second terminal coupled to a logic low level terminal for filtering the node level signal.

11. The level shifter circuit of claim 10, wherein the filter module comprises a filter capacitor having one end connected to the first node and the other end connected to the logic low level end.

12. The level shifter circuit of claim 1, further comprising a first buffer module operating in the first power domain, an input of the first buffer module being coupled to the signal input of the input signal, an output of the first buffer module being coupled to the first end of the switch module.

13. The level shifter circuit of claim 1, further comprising a second buffer module operating in the second power domain, an input of the second buffer module being coupled to an output of the hysteresis comparison module, an output of the second buffer module being configured to output the output signal.

14. A chip comprising the level shifter circuit of any one of claims 1-13.

15. An electronic device comprising a device body and the chip of claim 14 or the level shifter circuit of any one of claims 1-13 provided to the device body.